CN105743536B - A kind of rf control unit and radio frequency time control method - Google Patents
A kind of rf control unit and radio frequency time control method Download PDFInfo
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- CN105743536B CN105743536B CN201410756605.3A CN201410756605A CN105743536B CN 105743536 B CN105743536 B CN 105743536B CN 201410756605 A CN201410756605 A CN 201410756605A CN 105743536 B CN105743536 B CN 105743536B
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Abstract
The present invention relates to mobile communication field, a kind of rf control unit and radio frequency time control method are disclosed.Rf control unit includes clock generating module, common timing module and timing processing module.The fast clock generating unit of clock generating module generates fast clock signal, and the clock frequency of fast clock signal is not less than the clock frequency of any one clock signal in multiple clock signal；First timing unit of common timing module generates fast clock timing information according to fast clock signal；Timing sequence process module executes current radio frequency according to the present instruction information of fast clock timing information and the storage of timing sequence process inside modules and receives and dispatches event；Present instruction information includes multiple fast clock waiting times, and multiple fast clock waiting times convert according to the corresponding fast clock conversion ratio of current communication mode multiple current communication mode waiting times corresponding with current radio frequency transmitting-receiving event and obtained.To simplify the complexity of hardware in multi-mode communication system, while enhancing the scalability of multi-mode communication system.
Description
Technical field
The present invention relates to mobile communication field, in particular to a kind of rf control unit applied to multi-mode communication system and penetrate
Frequency time control method.
Background technique
In current 4G mobile communication system, there are many wireless communications mode and depositing, such as GSM, TD-SCDMA, WCDMA,
LTE and CDMA2000 etc..The physical layer software timing information basic there are two classes, one kind are a set of distinctive timing of each mode,
The common timing of the another kind of scene for the measurement of anomalous mode formula, the transmitting-receiving events conflict detection of multi-mode and multi-standby and sequence etc..This two
Class timing can all use when controlling radio frequency chip (RFIC), and the timing of two classes also needs to be mutually in step.
In baseband chip, it will usually there is the unit of a hardware to generate these timing informations, and these timings
Information can all be used for radio frequency timing controlled.Radio frequency control by taking tri- modular system of GSM, TD-SCDMA and LTE as an example, in baseband chip
The structure of device is as shown in Figure 1.RF timing control unit is segmented into four component parts, 10, four timings of clock generating module
Module 11a~11d, timing sequence process module 12 and peripheral control interface module 13.Clock generating module 10 generates multiple clock sources,
It is 4.33M, 10.24M, 30.72M and 26M respectively, and is separately input into four timing modules：GSM timing module 11a, TDS is fixed
When module 11b, LTE timing module 11c, common timing module 11d.It is peculiar fixed that timing module 11a~11c belongs to access module
When, i.e., a set of distinctive timing that each mode has.The timing information of common timing module 11d is for synchronizing each access mould
Formula timing, precision are low with respect to the requirement of access module.
As described above, although existing method can meet the needs of the RF timing of each access module very well, while
It is able to solve the problem of the synchronization of timing between mode, still, clock generating module is relative complex, needs multiple clock type.
If several clock frequencies do not have multiple proportion, then needing multiple PLL (frequency phase lock ring) just to realize, thus will increase
The area (cost) of baseband chip, while increasing the power consumption of timing module.Furthermore the type of timing module is increased, is realized
The complexity of logic is consequently increased；Correspondingly, in view of synchronize etc. that actual chip realizes between different clocks bus asks
Topic also increases the difficulty of the clock network design of baseband chip.From the scalability of system, if increasing a kind of wireless access mould
Formula, and the timing base of this mode is different with existing mode, then will increase corresponding in clock generating module, timing module
Unit, need to redesign chip and corresponding drive software, limit the scalability of chip platform in this way.
Furthermore, it is contemplated that the needs of the power saving of communication system, when the operation of no radio-frequency receiving-transmitting, can allow transceiver into
Enter the state of low-power consumption, the power supply and fast clock of the most of module of remaining of system can close.In order to guarantee that wireless communication is set
Standby (such as handheld terminal) needs a timing means in synchronizing on base station time to ensure to enter low-power consumption in system
When (sleep state) still be able to continue timing, but the power consumption of itself and corresponding chain road is then very low.Therefore, four
Respectively there is corresponding slow clock calibration circuit to calibrate slow clock signal inside a timing module.However, due to four timings
Module is respectively independent, so that the realization of four timing modules calibration is not exactly the same, the format of calibration output result is also inconsistent.
Summary of the invention
The purpose of the present invention is to provide a kind of rf control unit and radio frequency time control methods, and it is logical to not only simplify multimode
Hard-wired complexity in letter system, and enhance the scalability of multi-mode communication system.
In order to solve the above technical problems, embodiments of the present invention provide a kind of rf control unit, it is logical applied to multimode
Letter system, plurality of communication schemes correspond respectively to multiple clock signal, include：Clock generating module generates single comprising fast clock
Member, the fast clock generating unit is for generating fast clock signal, and the clock frequency of the fast clock signal is not less than described more
The clock frequency of any one clock signal in kind clock signal；Common timing module, include the first timing unit, described first
Timing unit is connected to the fast clock generating unit to generate fast clock timing information according to the fast clock signal；At timing
Module is managed, is connected to first timing unit, the timing sequence process module is according to the fast clock timing information and the timing
The present instruction information of processing module internal reservoir executes current radio frequency and receives and dispatches event, wherein the present instruction information includes
Multiple fast clock waiting times, each communication pattern have corresponding fast clock conversion ratio, and the current radio frequency receives and dispatches event pair
Should be in current communication mode, the multiple fast clock waiting time is according to the corresponding fast clock substitution ratio of the current communication mode
Value multiple current communication mode waiting times corresponding with current radio frequency transmitting-receiving event convert and obtain.
Embodiments of the present invention additionally provide a kind of radio frequency time control method, applied to including the more of rf control unit
Mould communication system, the rf control unit include sequentially connected clock generation module, common timing module and timing sequence process mould
Block, the clock generation module are used for for generating fast clock signal, the common timing module according to the fast clock signal
Fast clock timing information is generated, is comprised the steps of：The central processing unit is current according to belonging to current radio frequency transmitting-receiving event
Current radio frequency transmitting-receiving event is parsed into present instruction information by communication pattern, is worked as in the present instruction information comprising multiple
Preceding communication pattern waiting time；The corresponding fast clock of the current communication mode that the central processing unit obtains its internal reservoir changes
Calculate ratio；The central processing unit converts the multiple current communication mode waiting time according to the fast clock conversion ratio
At multiple fast clock waiting times；The present instruction information is downloaded to the timing sequence process module by the central processing unit,
Wherein, the timing sequence process module executes the current radio frequency according to the fast clock timing information and the present instruction information
Transmitting-receiving event.
In terms of existing technologies, clock generating module provided in the present invention includes fast clock to embodiment of the present invention
Unit is generated, the clock frequency for the fast clock signal that the fast clock generating unit generates is corresponding not less than plurality of communication schemes
The clock frequency of any one clock signal in multiple clock signal, and the present instruction letter of timing sequence process inside modules storage
Breath includes multiple fast clock waiting times, and each communication pattern has corresponding fast clock conversion ratio, the current radio frequency transmitting-receiving
Event corresponds to current communication mode, and the multiple fast clock waiting time is according to the corresponding fast clock of the current communication mode
Conversion ratio multiple current communication mode waiting times corresponding with current radio frequency transmitting-receiving event convert and obtain.To make
Replace the multiple timing modules for corresponding respectively to plurality of communication schemes in the prior art with a common timing module, and passes through
Multiple current communication mode waiting times are converted into multiple fast clock waiting times to execute to be implemented under different communication modes
Radio-frequency receiving-transmitting event not only simplifies hard-wired complexity in multi-mode communication system, and enhances multi-mode communication system
Scalability, that is, when system needs to newly increase a kind of communication pattern, the circuit knot of the rf control unit without redesigning system
Structure, and need to only make the conversion of corresponding timing information by the central processing unit of system.
In addition, the clock generation module also includes slow clock generating unit, the slow clock generating unit is for generating
Slow clock signal, the common timing module also include slow clock calibration unit, and the slow clock calibration unit is connected to described
Fast clock generating unit and the slow clock generating unit, the slow clock calibration unit to according to the fast clock signal and
The slow clock signal generates slow clock alignment ratio.Since a common timing module is used only, only need accordingly
One slow clock calibration unit is set, and exports a kind of calibration format, and avoids multiple timing module needs in the prior art
Multiple slow clock calibration units are arranged in correspondence with, a variety of calibration formats are exported.To not only further simplify the hardware of system
It realizes, and the prover time of system is unified.
In addition, the common timing module also includes the second timing unit, it is connected to the slow clock generating unit and institute
Timing sequence process module is stated, second timing unit generates slow clock timing information, the timing according to the slow clock signal
Processing module executes the current radio frequency according to the slow clock timing information and the present instruction information and receives and dispatches event.This reality
The reference mode that mode uses second order timing is applied, when timing processing module to be executed interval time between two continuous operations
When longer, the timing information for receiving slow clock timing information as timing control is switched to, to increase radio frequency timing control
Flexibility ratio.
Detailed description of the invention
Fig. 1 is the block diagram of timing control unit rf control unit in the prior art；
Fig. 2 is the block diagram of rf control unit according to the first embodiment of the present invention；
Fig. 3 is the block diagram of rf control unit according to the second embodiment of the present invention；
Fig. 4 is the flow chart of radio frequency time control method according to the third embodiment of the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to each reality of the invention
The mode of applying is explained in detail.However, it will be understood by those skilled in the art that in each embodiment of the present invention,
In order to make the reader understand this application better, many technical details are proposed.But even if without these technical details and base
In the various changes and modifications of following embodiment, each claim of the application technical side claimed also may be implemented
Case.
The first embodiment of the present invention is related to a kind of rf control units, are applied to multi-mode communication system.As shown in Fig. 2,
Rf control unit 1 includes clock generating module 10, common timing module 11, timing sequence process module 12 and peripheral interface module
13.Common timing module 11 is connected to clock generating module 10 and timing sequence process module 12, when peripheral interface module 13 is connected to
Sequence processing module 12.
In present embodiment, clock generating module 10 include fast clock generating unit 101, slow clock generating unit 102,
Fast signal source of clock A and slow clock signal source B.When fast clock generating unit 101 is connected to fast signal source of clock A to generate fast
Clock signal CLK1.Wherein, fast signal source of clock A is, for example, the clock signal of common 26M.Specifically, multi-mode communication system
It can be compatible with plurality of communication schemes, and each communication pattern corresponds to the clock signal of specific frequency, for example, gsm communication mode pair
It should correspond in clock signal, the LTE communication mode that the clock signal of 4.33M, TD-SCDMA communication pattern correspond to 10.24M
30.72M clock signal；Requirement of the i.e. different communication patterns to the time precision of timing control is different.Therefore, when fast
Clock, which generates the fast clock signal clk 1 that unit 101 generates, should can satisfy the compatible each communication pattern pair of the multi-mode communication system
The requirement of the time precision of timing control.In present embodiment, the multi-mode communication system is to be compatible with GSM, TD-SCDMA, LTE
For three kinds of communication patterns, select fast clock signal clk 1 for the clock signal of 30.72M.That is, fast clock generating unit 101 will
The signal source of clock of the 26M received carries out the processing of frequency multiplication and frequency dividing, to generate the fast clock signal of 30.72M.However, this
Embodiment is not intended to be limited in any this, the different communication patterns that those skilled in the art can be compatible according to the communication system
The suitable fast clock signal clk 1 of selection, as long as the time precision for meeting the fast clock signal clk 1 is right higher than each communication pattern institute
The time precision for the clock signal answered.
Slow clock generating unit 102 is connected to slow clock signal source B to generate slow clock signal CLK2.Wherein, slow clock
Signal source B is, for example, the clock signal of common 32K.In present embodiment, by slow clock signal CLK2 be set as 32K when
Clock signal.However, present embodiment is not intended to be limited in any this, those skilled in the art can select properly according to actual needs
Slow clock signal.
In present embodiment, common timing module 11 includes the first timing unit 111 and slow clock calibration unit 112.
First timing unit 111 is connected to fast clock generating unit 101, to generate fast clock timing information according to fast clock signal clk 1
T1.Specifically, the first timing unit 111 includes a counter and multiple latch, counter is to the fast clock received
Signal CLK1 count and is exported fast clock timing information T1 by multiple latch.
Slow clock calibration unit 112 is connected to fast clock generating unit 101 and slow clock generating unit 102, using fastly
Clock signal clk 1 verifies slow clock signal CLK2.Specifically, slow clock calibration unit 112 includes at least fast clock
Counter, slow clock counter, multiple registers and a computing unit.When multi-mode communication system works normally
(i.e. when fast clock generating unit 101 works), fast clock counter and slow clock counter are respectively used to fast clock
Signal CLK1 and slow clock signal CLK2 count and fast clock count value and slow clock count value is separately stored in deposit
In device.Computing unit periodically measures slow clock signal CLK2 using fast clock signal clk 1, i.e. computing unit periodically calculates
Fast multiple of the clock count value relative to slow clock count value in the same period, fast clock count value phase in the same period
Multiple for slow clock count value is slow clock alignment ratio.Slow clock calibration unit 112 is by slow clock calibration unit 112
It is stored in its internal register, using the calibration result as fast clock signal clk 1 to slow clock signal CLK2.?
When fast clock generating unit 101 is closed, which can be used directly to enter low function as system
After the state of consumption, the slow clock counter of slow clock calibration unit 112 continues the reference counted.Compared to existing technologies,
In present embodiment due to using a common timing module instead of multiple timing modules, so it is only necessary that with one it is slow when
Clock calibration unit 112, and a kind of calibration format is exported, the hardware configuration of rf control unit is not only simplified, and make system
Prover time obtain.
In present embodiment, timing sequence process module 12 includes multiple 1~N of serial device, and each serial device is connected to the
One timing unit 111.Each serial device executes current according to the present instruction information of fast clock timing information T1 and its internal reservoir
Radio-frequency receiving-transmitting event.Wherein, each serial device in timing sequence process module 12 is also attached to fast clock generating unit 101, each sequence
Device receives fast clock signal clk 1 using as internal reference clock.Peripheral interface module 13 is held for output timing processing module 12
The multiple control signal generated in radio-frequency receiving-transmitting event procedure before the trade.Peripheral interface module 13 for example connects comprising control DigRF
Mouth, GPO/RFFE interface (RF Front End Interface), GPO (General Purpose Output Ports) connect
Mouth, interruption (Interrupt) interface etc..Specific structure this field skill about timing sequence process module 12 and peripheral interface module 13
Art personnel are it is to be appreciated that details are not described herein again.
Second embodiment of the invention is related to a kind of rf control unit, as shown in figure 3, second embodiment is implemented with first
Mode is roughly the same, is in place of the main distinction：In second embodiment of the invention, common timing module 11 is also comprising the second meter
Shi Danyuan 113 is connected to each serial device of slow clock generating unit 102 and timing sequence process module 12.Second timing unit 113
Slow clock timing information is generated according to slow clock signal CLK2.Wherein, each serial device in timing sequence process module 12 is also attached to slowly
Clock generating unit 102, each serial device receive slow clock signal CLK2 using as internal reference clock.
In present embodiment, the second timing unit 113 includes a counter and multiple latch, and counter is to reception
The slow clock signal CLK2 arrived carries out timing and exports slow clock timing information T2 to timing sequence process module by multiple latch
12 each serial device, each serial device are currently penetrated according to fast clock timing information T1 and the present instruction information execution of its internal reservoir
Frequency transmitting-receiving event, or current radio frequency transmitting-receiving is executed according to the present instruction information of slow clock timing information T2 and its internal reservoir
Event.Specifically, when being separated by M fast clock signal clks 1 between the serial device two continuous operations to be executed, when M ratio
When larger, the bit wide of counter may be restricted and can not achieve in serial device instruction, and M can be divided into P CLK2 and Q
Each CLK1, i.e. M=N*P+Q, wherein N is the slow clock alignment ratio of slow 112 internal reservoir of clock calibration unit, i.e., with for the moment
Between fast multiple of the clock count value relative to slow clock count value in section.To which serial device can easier pass through delay P
Slow clock count value and Q fast clock count values realize two continuous operations with long period interval.Compared to existing
For having technology, present embodiment uses the reference mode of second order timing, i.e., the timing information that common timing module 11 exports divides
At two step-lengths：Fast clock timing information T1 and slow clock timing information T2.To when serial device to be executed two continuously
When interval time is longer between operation, the timing information for receiving slow clock timing information T2 as timing control is switched to, to increase
Add the flexibility ratio of radio frequency timing control.However, the number for the timing information that present embodiment exports common timing module 11 this
It is not intended to be limited in any.In other embodiment, according to actual needs, multi-mode communication system can be with the ginseng of other multistage timings
Examine mode, such as the timing of three ranks, quadravalence timing etc..
It is noted that each module involved in above-mentioned two embodiment is logic module, actually answering
In, a logic unit can be a physical unit, be also possible to a part of a physical unit, can also be with multiple
The combination of physical unit is realized.It, will be in above-mentioned two embodiment in addition, in order to protrude innovative part of the invention
It solves the less close unit of technical problem relationship proposed by the invention to introduce, but this does not indicate in present embodiment and does not deposit
In other units.
Third embodiment of the present invention is related to a kind of radio frequency time control method, applied to including the more of rf control unit
Mould communication system, rf control unit include at least sequentially connected clock generation module, common timing module, timing sequence process mould
Block.Clock generation module changes and slow clock signal for generating fast clock signal.Common timing module is used to be believed according to fast clock
Number and slow clock signal generate fast clock timing information and slow clock timing information respectively, and by fast clock timing information and it is slow when
Clock timing information is exported to timing sequence process module.As shown in figure 4, the radio frequency time control method that present embodiment provides includes step
Rapid S1 to step S7.
Step S1：Central processing unit current communication mode according to belonging to current radio frequency transmitting-receiving event receives the current radio frequency
Hair event is parsed into present instruction information, includes multiple current communication mode waiting times in present instruction information.
Specifically, central processing unit can successively handle multiple radio-frequency receiving-transmitting events sequentially in time, wherein multiple to penetrate
Frequency transmitting-receiving event may need to execute under a variety of different communication patterns.Since various communication patterns have a set of distinctive meter
When mode, i.e., various communication patterns correspond respectively to the clock signal of multi-frequency, and central processing unit handles current radio frequency transmitting-receiving
When event, the current communication mode according to belonging to the current radio-frequency receiving-transmitting event is needed to be parsed into the current radio-frequency receiving-transmitting event
Present instruction information includes multiple current communication mode waiting times in present instruction information.Wherein, current communication mode etc.
Refer to the clocking value that the clock signal according to corresponding to the current communication mode is calculated to duration.For example, gsm communication mode
The clock signal of corresponding 4.33M, then, the waiting time calculated under gsm communication mode are the clock signal using 4.33M
Corresponding clocking value when as timing signal.The specific number of current communication mode waiting time receives and dispatches event according to current radio frequency
The concrete operations content to be executed depending on.For example, the current communication mode waiting time in current radio frequency transmitting-receiving event is total
Share 6, respectively T1=31, T2=69, T3=58, T4=102, T5=100, T6=324.However present embodiment to this not
It imposes any restrictions.
Step S2：Central processing unit obtains the corresponding fast clock conversion ratio of the current communication mode of its internal reservoir.
Specifically, central processing unit internal reservoir has the fast clock conversion ratio table of communication pattern-, fast clock signal is indicated
Frequency clock signal corresponding with each communication pattern frequency ratio.In present embodiment, the frequency of fast clock signal
For example, 30.72M, the frequency of the corresponding clock signal of gsm communication system are 4.33M, then the corresponding fast clock of gsm communication system
Conversion ratio is 30.72M/4.33M=7.0947.As shown in table 1, for by taking tri- communication systems of GSM, TD-SCDMA, LTE as an example
The fast clock conversion ratio table of communication pattern-, wherein the frequency of the corresponding clock signal of TD-SCDMA, LTE communication system is distinguished
For 10.24M, 30.72M.
Table 1
| GSM | TD-SCDMA | LTE |
| Fast clock conversion ratio | 7.0947 | 3 | 1 |
Central processing unit according to the fast clock conversion ratio table of communication pattern-that current communication mode inquires its internal reservoir with
Obtain the corresponding fast clock conversion ratio of the current communication mode.
Step S3：Multiple current communication mode waiting times are converted into more by central processing unit according to fast clock conversion ratio
A fast clock waiting time.That is, fast clock waiting time=fast clock conversion ratio * current communication mode waiting time.For example,
The waiting time T of the 6 gsm communication modes enumerated in step S11~T6It is converted into corresponding 6 fast clock waiting time T1'~
T6' be respectively：T1'=220, T2'=490, T3'=411, T4'=724, T5'=709, T6'=2299.
Step S4：Central processing unit judge in multiple fast clock waiting times whether at least one fast clock waiting time
Greater than preset duration, if so, S5 is entered step, if it is not, then entering step S7.
Specifically, timing sequence process module includes multiple serial devices, the counter in each serial device instruction has certain
Bit wide, i.e. counter have preset maximum count value.The preset duration may be set to the maximum count value, however this implementation
Mode is not limited in any way the setting means of preset duration.When fast clock waiting time being more than preset duration, serial device refers to
Counter in order can not will correctly count, to cause the instruction execution mistake of serial device.To avoid above situation, center
Processor needed to judge in multiple fast clock waiting times of present instruction information, if at least one fast clock waiting time
Greater than preset duration；If so, entering step S4.For example, when the maximum count value of the counter in serial device instruction is 899,
I.e. when preset duration is 899, due to T6'=2299>899, then enter step S5.In other situation, i.e., when each fast clock
When waiting time is respectively less than or is equal to preset duration, then step S7 is directly entered.
Step S5：Central processing unit obtains slow clock alignment ratio from common timing module.
Specifically, fast clock signal and slow clock that common timing module is also used to be generated according to clock generation module are believed
It number periodically generates slow clock alignment ratio and the slow clock alignment ratio is stored in inside it.Wherein, slow clock alignment ratio
Value=fast clock signal frequency/slow clock signal frequency.For example, when the frequency of fast clock signal is 30.72M, slow clock
When the frequency of signal is 32.768K, slow clock alignment ratio is 30.72M/32.768K=937.5.Central processing unit is from public
The slow clock alignment ratio is obtained in timing module.
Step S6：The fast clock waiting time is resolved into slow clock according to slow clock alignment ratio and waited by central processing unit
The combination of duration and fast clock waiting time.That is, slow clock waiting time and the group of fast clock waiting time are combined into：Slow clock school
Quasi- ratio * slow clock waiting time+fast clock waiting time.It, can be by fast clock waiting time T according to step S46’
=2299 are decomposed into：T6'=937.5*2+424, that is, be decomposed into 2 slow clock waiting times and 424 fast clock waiting times
Combination.
Step S7：Present instruction information is downloaded to timing sequence process module by central processing unit.Step S7 includes sub-step S71
To sub-step S72.
Sub-step S71：Central processing unit successively inquires whether each serial device is in idle condition, if it is not, then repeating this step
Suddenly, if so, into sub-step S72.
Specifically, each serial device has idle state identifier, and when serial device executes radio-frequency receiving-transmitting event, idle shape
State identifier is, for example, 0 (or 1), indicates that the serial device is in busy state, when serial device has executed a radio-frequency receiving-transmitting thing
When part, which can be revised as the idle state identifier 1 (or 0), indicate that the serial device is in idle condition.Centre
The idle state identifier that reason device successively inquires each serial device is in idle condition with judging whether there is serial device, if each serial device
It is in busy state, then central processing unit repeats sub-step S71；If inquiring at least one of which serial device as sky
Not busy state then enters sub-step S72.
Sub-step S72：Present instruction information is downloaded to a serial device for being currently at idle state by central processing unit.
That is, central processing unit the present instruction information parsed is downloaded to checked out in sub-step S71 be currently at the free time
In the serial device of state.
To which the serial device executes current radio frequency according to the current command information and receives and dispatches event.Specifically, the serial device
The fast clock timing information received is executed into current radio frequency as the timing information of default and receives and dispatches event.When going to some etc.
When a length of slow clock waiting time and fast clock waiting time combination when, then automatically switch to and receive slow clock timing information
Reception is switched to again after having executed the slow clock waiting time as the timing information for executing the slow clock waiting time
Fast clock timing information is as the timing information for continuing operation.
The step of various methods divide above, be intended merely to describe it is clear, when realization can be merged into a step or
Certain steps are split, multiple steps are decomposed into, as long as comprising identical logical relation, all in the protection scope of this patent
It is interior；To adding inessential modification in algorithm or in process or introducing inessential design, but its algorithm is not changed
Core design with process is all in the protection scope of the patent.
It is not difficult to find that present embodiment is embodiment of the method corresponding with the first, second embodiment, present embodiment
Can work in coordination implementation with the first, second embodiment.The relevant technical details mentioned in first, second embodiment are in this reality
It applies in mode still effectively, in order to reduce repetition, which is not described herein again.Correspondingly, the relevant technologies mentioned in present embodiment
Details is also applicable in the first, second embodiment.
It will be understood by those skilled in the art that the respective embodiments described above are to realize specific embodiments of the present invention,
And in practical applications, can to it, various changes can be made in the form and details, without departing from the spirit and scope of the present invention.
Claims (8)
1. a kind of rf control unit is applied to multi-mode communication system, plurality of communication schemes corresponds respectively to multiple clock signal,
It is characterized in that, includes：
Clock generating module includes fast clock generating unit, and the fast clock generating unit is used to generate a kind of fast clock signal,
Clock frequency of the clock frequency of the fast clock signal not less than any one clock signal in the multiple clock signal；
Common timing module, include the first timing unit, first timing unit be connected to the fast clock generating unit with
Fast clock timing information is generated according to the fast clock signal；
Timing sequence process module, is connected to first timing unit, and the timing sequence process module is believed according to the fast clock timing
Breath and the present instruction information of timing sequence process inside modules storage execute current radio frequency and receive and dispatch event,
Wherein, the present instruction information includes multiple fast clock waiting times, and there is each communication pattern corresponding fast clock to change
Ratio is calculated, the current radio frequency transmitting-receiving event corresponds to current communication mode, and the multiple fast clock waiting time is according to
The corresponding fast clock conversion ratio of current communication mode multiple current communication modes corresponding with current radio frequency transmitting-receiving event
Waiting time converts and obtains.
2. rf control unit according to claim 1, which is characterized in that the clock generation module also includes that slow clock produces
Raw unit, for the slow clock generating unit for generating slow clock signal, the common timing module also includes slow clock alignment
Unit, the slow clock calibration unit is connected to the fast clock generating unit and the slow clock generating unit, when described slow
Clock calibration unit is to generate slow clock alignment ratio according to the fast clock signal and the slow clock signal.
3. rf control unit according to claim 2, which is characterized in that the common timing module also includes the second timing
Unit, is connected to the slow clock generating unit and the timing sequence process module, second timing unit according to it is described slow when
Clock signal generates slow clock timing information, and the timing sequence process module is according to the slow clock timing information and the present instruction
Information executes the current radio frequency and receives and dispatches event.
4. rf control unit according to claim 3, which is characterized in that the timing sequence process module includes multiple sequences
Device, is connected to first timing unit and second timing unit, and each serial device is believed according to the fast clock timing
Breath and the present instruction information execute the current radio frequency and receive and dispatch event, or according to the slow clock timing information with it is described
Present instruction information executes the current radio frequency and receives and dispatches event.
5. rf control unit according to claim 1, which is characterized in that the rf control unit also includes Peripheral Interface mould
Block, is connected to the timing sequence process module, and the peripheral interface module is worked as described in the timing sequence process module execution for exporting
The multiple control signal generated in preceding radio-frequency receiving-transmitting event procedure.
6. a kind of radio frequency time control method, applied to the multi-mode communication system comprising rf control unit, the rf control unit
Comprising sequentially connected clock generation module, common timing module and timing sequence process module, the clock generation module is for producing
A kind of raw fast clock signal, the common timing module are used to generate fast clock timing information according to the fast clock signal,
It is characterized in that, comprises the steps of：
The current radio frequency is received and dispatched event solution by central processing unit current communication mode according to belonging to current radio frequency transmitting-receiving event
Present instruction information is analysed into, includes multiple current communication mode waiting times in the present instruction information；
The central processing unit obtains the corresponding fast clock conversion ratio of the current communication mode of its internal reservoir；
The multiple current communication mode waiting time is converted by the central processing unit according to the fast clock conversion ratio
Multiple fast clock waiting times；
The present instruction information is downloaded to the timing sequence process module by the central processing unit,
Wherein, the timing sequence process module executes described current according to the fast clock timing information and the present instruction information
Radio-frequency receiving-transmitting event.
7. radio frequency time control method according to claim 6, which is characterized in that the clock generation module is also used to produce
Raw slow clock signal, the common timing module is also used to generate slow clock timing information according to the slow clock signal, described
Common timing module is also used to generate slow clock alignment ratio according to the fast clock signal and the slow clock signal, in described
When the multiple current communication mode waiting time is converted into multiple fast according to the fast clock conversion ratio by central processing unit
After the step of clock waiting time, also include：
The central processing unit judges whether at least one fast clock waiting time is big in the multiple fast clock waiting time
In preset duration, if it is not, the present instruction information is then downloaded to the timing sequence process module into the central processing unit
The step of；
If so, the central processing unit obtains the slow clock alignment ratio from the common timing module；
The fast clock waiting time is resolved into slow clock according to the slow clock alignment ratio and waited by the central processing unit
The combination of duration and the fast clock waiting time downloads to the present instruction information subsequently into the central processing unit
The step of timing sequence process module,
Wherein, the timing sequence process module executes described current according to the slow clock timing information and the present instruction information
Radio-frequency receiving-transmitting event.
8. radio frequency time control method according to claim 6, which is characterized in that the timing sequence process module includes multiple
The step of serial device, the present instruction information is downloaded to the timing sequence process module by the central processing unit includes：
The central processing unit successively inquires whether each serial device is in idle condition, if it is not, then repeating this step；
If so, the present instruction information is downloaded to a serial device for being currently at idle state by the central processing unit.
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