CN105702579A - Manufacturing method of epitaxial channel on fin and fin field effect transistor - Google Patents
Manufacturing method of epitaxial channel on fin and fin field effect transistor Download PDFInfo
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- CN105702579A CN105702579A CN201410681972.1A CN201410681972A CN105702579A CN 105702579 A CN105702579 A CN 105702579A CN 201410681972 A CN201410681972 A CN 201410681972A CN 105702579 A CN105702579 A CN 105702579A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 35
- 230000005669 field effect Effects 0.000 title claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 238000002156 mixing Methods 0.000 claims description 13
- 230000001590 oxidative effect Effects 0.000 claims description 12
- 150000002500 ions Chemical class 0.000 claims description 8
- 229910052986 germanium hydride Inorganic materials 0.000 claims description 4
- LDDQLRUQCUTJBB-UHFFFAOYSA-N ammonium fluoride Chemical compound [NH4+].[F-] LDDQLRUQCUTJBB-UHFFFAOYSA-N 0.000 claims description 2
- 238000000407 epitaxy Methods 0.000 abstract 1
- 239000000463 material Substances 0.000 description 10
- 230000008569 process Effects 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000002309 gasification Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000010992 reflux Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
- H01L29/7854—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection with rounded corners
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a method for manufacturing a fin of a fin field effect transistor, which comprises the following steps: providing a substrate, wherein fins which are mutually isolated are formed in the substrate; performing pre-baking before fin epitaxy to remove a natural oxide layer on the fin, and reflowing the fin in a pre-baking chamber; an epitaxial layer is grown on the fin. In the invention, after reflow, the height of the fin is reduced, the original doping residue in the channel region can move downwards to the lower part of the fin, and the regrown epitaxial layer is used as a part or a new channel, so that the device has better device characteristics.
Description
Technical field
The invention belongs to field of semiconductor manufacture, particularly relate to the manufacture method of epi channels on a kind of fin formula field effect transistor, fin。
Background technology
Highly integrated along with semiconductor device, the short-channel effect of the MOSFET element of plane is more notable, is degrading the performance of device。
At present, for the problem solving short-channel effect, propose the three-dimensional device architecture of fin formula field effect transistor (Fin-FET), Fin-FET is the transistor with fin channel structure, it utilizes several surfaces of thin fin as raceway groove, such that it is able to prevent the short-channel effect in conventional transistor, operating current can be increased simultaneously。
In Fin-FET device fabrication, owing to PTSL (PunchThoughStopLayer, break-through stop-layer) etc. is in the doping of channel region so that channel region remains unwanted impurity, increases the scattering of channel region, affect the performance of device。
Summary of the invention
It is an object of the invention to overcome deficiency of the prior art, it is provided that the manufacture method of epi channels on a kind of fin formula field effect transistor, fin, improve the stress effect of source-drain area。
For achieving the above object, the technical scheme is that
The manufacture method of epi channels on a kind of fin, including step:
Substrate is provided, substrate is formed mutually isolated fin；
Carry out the front baking before fin extension, to remove the natural oxidizing layer on fin, and in the chamber of front baking, fin is refluxed；
At fin growing epitaxial layers。
Optionally,
Optionally, the mobility mobility more than fin of epitaxial layer is stated。
Optionally, described substrate is body substrate, before the step of the front baking before carrying out fin extension, also includes: carry out ion implanting, to form break-through stop-layer。
Optionally, described substrate is SOI or GOI substrate。
Optionally, the gas of front baking is H2, or H2With HCl, NH4F or GeH4Mixing gas or HF and N2Mixing gas。
Optionally, when removing natural oxidizing layer, the pressure of chamber indoor gas is 20-2000 holder, and the temperature of cavity is 450-1150 DEG C。
Optionally, when source-drain area is refluxed, the pressure of chamber indoor gas is 50 millitorr-200 holders, and the temperature of cavity is 450-1150 DEG C。
Optionally, when removing natural oxidizing layer, the pressure of chamber indoor gas is 250-1000 holder, and the temperature of cavity is 700-850 DEG C。
Optionally, when source-drain area is refluxed, the pressure of chamber indoor gas is 1-100 holder, and the temperature of cavity is 700-850 DEG C。
Optionally, the thickness range of epitaxial layer is 1-100nm。
Optionally, the thickness range of epitaxial layer is 5-40nm。
Additionally, present invention also offers the manufacture method of a kind of fin formula field effect transistor, any of the above-described manufacture method is utilized to form epi channels on fin。
The manufacture method of epi channels on the fin formula field effect transistor of the embodiment of the present invention, fin, whole piece fin is carried out front baking, and in the chamber of front baking, fin is refluxed, then, carrying out the extension of fin, make the height reduction of fin after backflow, the original doping residual of channel region can be displaced downwardly to the bottom of fin, the epitaxial layer regrowed, as part or new raceway groove, has better device property。Meanwhile, the atom of backflow skeg rearranges, and reduces the defect in fin, thus improve the quality of subsequent epitaxial layer。
Further, the fin after backflow is prone to the higher-quality epitaxial layer of extension, the epitaxial layer that extension mobility is bigger, will further improve the carrier mobility of raceway groove, improves the speed of device。
Accompanying drawing explanation
In order to be illustrated more clearly that technical scheme of the invention process, the accompanying drawing used required in embodiment will be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the premise not paying creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings。
Fig. 1 is the flow chart of the manufacture method of the fin formula field effect transistor source-drain area according to the present invention；
Fig. 2 A-Fig. 6 B manufactures the perspective view in each manufacture process of fin formula field effect transistor according to embodiments of the present invention, wherein Fig. 2 A-6A is the schematic cross-section of the transistor of the cross-sectional direction along fin, and Fig. 2 B-6B is the generalized section of the transistor of the length direction along fin；
The epitaxial layer of the fin that respectively conventional for Fig. 7 A and 7B manufacturing process, the manufacturing process of the embodiment of the present invention are formed schematic cross-section under the microscope。
Detailed description of the invention
Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail。
Elaborate a lot of detail in the following description so that fully understanding the present invention, but the present invention can also adopt other to be different from alternate manner described here to be implemented, those skilled in the art can do similar popularization when without prejudice to intension of the present invention, and therefore the present invention is not by the restriction of following public specific embodiment。
Secondly, the present invention is described in detail in conjunction with schematic diagram, when describing the embodiment of the present invention in detail; for ease of explanation; representing that the profile of device architecture can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, it should not limit the scope of protection of the invention at this。Additionally, the three-dimensional space of length, width and the degree of depth should be comprised in actual fabrication。
The present invention proposes the manufacture method of a kind of fin formula field effect transistor fin, including: substrate is provided, substrate is formed mutually isolated fin；Carry out the front baking before fin extension, to remove the natural oxidizing layer on fin, and in the chamber of front baking, fin is refluxed；At fin growing epitaxial layers。
In the present invention, whole piece fin is carried out front baking, and in the chamber of front baking, fin is refluxed, then, carry out the extension of fin, after backflow, make the height reduction of fin, the original doping residual of channel region can be displaced downwardly to the bottom of fin, the epitaxial layer regrowed is as part or new raceway groove, and undoped remains, and has better device property。Meanwhile, the atom of backflow skeg rearranges, and reduces the defect in fin, thus improve the quality of subsequent epitaxial layer。
It should be noted that, in the accompanying drawing of the present invention, the accompanying drawing of same sequence number, such as Fig. 2 A and Fig. 2 B, for the schematic cross-section of the different directions of transistor in same manufacture process, wherein, Fig. 2 A-6A is the schematic cross-section of the transistor of the cross-sectional direction along fin, and namely Fig. 2 B-6B is the cross-sectional view of the transistor along fin bearing of trend。
In order to be better understood from technical scheme and technique effect, below with reference to concrete schematic flow sheet Fig. 1, specific embodiment is described in detail。
First, in step S01, it is provided that substrate 100, substrate 100 is formed with mutually isolated fin 110, with reference to shown in Fig. 4 A and Fig. 4 B。
In the present invention, described substrate 100 can be Si substrate, Ge substrate, SiGe substrate, SOI (silicon-on-insulator, or GOI (germanium on insulator SiliconOnInsulator), GermaniumOnInsulator) etc., described substrate can also be the substrate including other elemental semiconductors or compound semiconductor, such as GaAs, InP or SiC etc., it can also be laminated construction, such as Si/SiGe etc., other epitaxial structures all right, for instance SGOI (silicon germanium on insulator) etc.。In the present embodiment, described substrate is body silicon substrate, with reference to shown in Fig. 2 A。
In a specific embodiment, it is possible to fin 110 and isolation 120 are provided as follows。
First, the substrate 100 of body silicon forms the first hard mask 104, such as silicon nitride；Then, adopting lithographic technique, for instance the method for RIE (reactive ion etching), etched substrate 100 forms fin 102, thus the fin 102 defined on substrate 100, as shown in Figure 2 A and 2B。
Then, as shown in Figure 3 A and Figure 3 B, carrying out the filling of isolated material 106, isolated material can be such as silicon dioxide, then planarize, until exposing the upper surface of fin 102, then, it is possible to use wet etching, such as with the isolated material of the certain thickness silicon dioxide of Fluohydric acid. erosion removal, the isolated material of member-retaining portion is between fin 102, thus defining isolation 110, with reference to shown in Fig. 4 A and Fig. 4 B。
Then, in step S02, carry out the front baking before fin extension, to remove the natural oxidizing layer on fin, and in the chamber of front baking, fin is refluxed, with reference to shown in Fig. 6 A and Fig. 6 B。
In the manufacturing process of body silicon substrate, after forming fin, as shown in Figure 4 A and 4 B shown in FIG., it is typically conducted ion implanting, to form break-through stop-layer (PunchThoughStopLayer, PTSL) 108 under the raceway groove of fin。Normally, the angular range of PTSL ion implanting is 0-45 °, and dosage range is 1E12 to 1E14cm-2, energy range is 10 to 150KEV。In the present embodiment, the angular range of PTSL ion implanting is 0-7 °, and dosage range is 5E12 to 5E13cm-2, energy range is 30 to 80KEV。Normally, PTSL ion implanting adopts and the ion of source and drain injection opposite types, for N-type device, implanting p-type impurity, for instance B etc.；For P-type device, inject N-type impurity, for instance for As or P etc.。After the ion implanting forming PTSL forms break-through stop-layer, uneven doping content can be there is also at channel region, this makes the pattern of the knot between channel region and source-drain area occur, and the duty of device is produced impact, causes the deterioration of device performance。
In the present embodiment, after forming break-through stop-layer, front baking and reflux technique are carried out。In front baking processing step before fin extension, natural oxidizing layer on fin is removed, so that it is follow-up at fin growing epitaxial layers, in front baking technique, it is common that by the gas in chamber and silicon oxide reacting generating compound, the melting point compound of generation is low, easily gasification, separating from fin surface after gasification, thus reaching to remove the purpose of fin oxide on surface, the gas of front baking can be H2、H2With the mixing gas of HCl, H2With NH4The mixing gas of F, H2With GeH4Mixing gas or HF and N2Mixing gas etc.。
Removal and the reflow step of natural oxidizing layer is carried out in removing the chamber of front baking of natural oxidizing layer。Concrete, first, the chamber of front baking carrying out the removal of natural oxidizing layer, the gas of front baking can be H2、H2With the mixing gas of HCl, H2With NH4The mixing gas of F, H2With GeH4Mixing gas or HF and N2Mixing gas, in the process, the pressure of chamber indoor gas be 20-2000 holder (torr), the temperature of cavity is 450-1150 DEG C, in a preferred embodiment, the pressure of chamber indoor gas be 250-1000 holder, the temperature of cavity is 700-850 DEG C；Then, in the chamber, change the pressure in chamber and/or temperature, carrying out the backflow (re-flow) of fin, in the process, the pressure of chamber indoor gas is 50 millitorr-200 holders, the temperature of cavity is 450-1150 DEG C, in preferred embodiment, the pressure of chamber indoor gas is 1-100 holder, and the temperature of cavity is 700-850 DEG C。Upon reflowing, with reference to shown in Fig. 5 A and Fig. 5 B, the height reduction of fin, the original doping residual of channel region can be displaced downwardly to the bottom of fin, and the atom of fin rearranges, and reduces the defect in fin, is conducive to improving the quality of subsequent epitaxial。
In the present embodiment, the chamber of front baking adopts H2Or H2With the mixing gas of HCl, after backflow, with reference to shown in Fig. 7 B, fin defines the polyhedron with (111) face, and this polyhedron is shorter wider。
In step S03, at fin growing epitaxial layers 103, with reference to shown in Fig. 6 A and 6B。
Selective epitaxial process can be adopted, carry out the growth of the epitaxial layer of fin, epitaxial layer thickness can be 1-100nm, the atom of the fin after refluxing has re-started arrangement, is more conducive to improve the quality of epitaxial layer, simultaneously, the original doping residual of channel region can be displaced downwardly to the bottom of fin, the epitaxial layer regrowed is as part or new raceway groove, and undoped remains, and has better device property。
In a preferred embodiment, epitaxial layer selects mobility to be formed higher than the material of fin, and thickness range can be 5-40nm, so, will further improve the carrier mobility of raceway groove, and then improves the speed of device。Such as the fin of silicon, epitaxial layer can be the material that constitutes of the single-element of four races or the compound-material of two or more compositions, for instance germanium silicon, carbon silicon etc.；Can also be the material that constitutes of III-V material single-element or the compound-material of two or more compositions, for instance GaAs, InP etc.。
With reference to shown in Fig. 7 A and 7B, the epitaxial layer of the fin that respectively conventional for Fig. 7 A and 7B manufacturing process, the manufacturing process of the embodiment of the present invention are formed schematic cross-section under the microscope, it can be seen that the epitaxial layer of the embodiment of the present invention has better epitaxial quality and pattern。
So far, the fin with epitaxial layer of the embodiment of the present invention is defined, then, it is possible to complete the subsequent manufacturing procedures of device, for instance on epitaxial layer, continuously form gate dielectric layer, grid and side wall, and source-drain area etc.。
Although the present invention discloses as above with preferred embodiment, but is not limited to the present invention。Any those of ordinary skill in the art, without departing from, under technical solution of the present invention ambit, may utilize the method for the disclosure above and technology contents and technical solution of the present invention is made many possible variations and modification, or be revised as the Equivalent embodiments of equivalent variations。Therefore, every content without departing from technical solution of the present invention, the technical spirit of the foundation present invention, to any simple modification made for any of the above embodiments, equivalent variations and modification, all still falls within the scope of technical solution of the present invention protection。
Claims (12)
1. the manufacture method of epi channels on a fin, it is characterised in that include step:
Substrate is provided, substrate is formed mutually isolated fin；
Carry out the front baking before fin extension, to remove the natural oxidizing layer on fin, and in the chamber of front baking, fin is refluxed；
At fin growing epitaxial layers。
2. manufacture method according to claim 1, it is characterised in that the mobility of described epitaxial layer is more than the mobility of fin。
3. manufacture method according to claim 1, it is characterised in that described substrate is body substrate, before the step of the front baking before carrying out fin extension, also includes: carry out ion implanting, to form break-through stop-layer。
4. manufacture method according to claim 1, it is characterised in that described substrate is SOI or GOI substrate。
5. manufacture method according to claim 1, it is characterised in that the gas of front baking is H2, or H2With HCl, NH4F or GeH4Mixing gas or HF and N2Mixing gas。
6. manufacture method according to claim 1, it is characterised in that when removing natural oxidizing layer, the pressure of chamber indoor gas is 20-2000 holder, and the temperature of cavity is 450-1150 DEG C。
7. manufacture method according to claim 1, it is characterised in that when source-drain area is refluxed, the pressure of chamber indoor gas is 50 millitorr-200 holders, and the temperature of cavity is 450-1150 DEG C。
8. manufacture method according to claim 1, it is characterised in that when removing natural oxidizing layer, the pressure of chamber indoor gas is 250-1000 holder, and the temperature of cavity is 700-850 DEG C。
9. manufacture method according to claim 8, it is characterised in that when source-drain area is refluxed, the pressure of chamber indoor gas is 1-100 holder, and the temperature of cavity is 700-850 DEG C。
10. manufacture method according to claim 1, it is characterised in that the thickness range of epitaxial layer is 1-100nm。
11. manufacture method according to claim 1, it is characterised in that the thickness range of epitaxial layer is 5-40nm。
12. the manufacture method of a fin formula field effect transistor, it is characterised in that include the manufacture method of epi channels on the fin according to any one of claim 1-11。
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| CN201410681972.1A CN105702579B (en) | 2014-11-24 | 2014-11-24 | Manufacturing method of epitaxial channel on fin and fin field effect transistor |
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| CN201410681972.1A CN105702579B (en) | 2014-11-24 | 2014-11-24 | Manufacturing method of epitaxial channel on fin and fin field effect transistor |
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| US8659032B2 (en) * | 2012-01-31 | 2014-02-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET and method of fabricating the same |
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