CN104124166B - The forming method of fin formula field effect transistor - Google Patents
The forming method of fin formula field effect transistor Download PDFInfo
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- CN104124166B CN104124166B CN201310156941.XA CN201310156941A CN104124166B CN 104124166 B CN104124166 B CN 104124166B CN 201310156941 A CN201310156941 A CN 201310156941A CN 104124166 B CN104124166 B CN 104124166B
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- 230000005669 field effect Effects 0.000 title claims abstract description 64
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- 230000009969 flowable effect Effects 0.000 claims description 7
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- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 claims description 5
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- 238000001451 molecular beam epitaxy Methods 0.000 claims description 3
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
Abstract
A kind of forming method of fin formula field effect transistor, including: providing Semiconductor substrate, described semiconductor substrate surface has first medium layer；Etch described first medium layer, form the first opening exposing described Semiconductor substrate；Epitaxial layer is formed in described first opening, described epitaxial layer fills full described first opening, the carrier mobility of described epitaxial layer is more than the carrier mobility of described Semiconductor substrate, described epitaxial layer has two end regions and zone line, and the lattice defect of described epitaxial layer two end regions is more than the lattice defect of zone line；Removing two end regions of described epitaxial layer, form the second opening, the zone line of residue epitaxial layer constitutes semiconductor fin；Forming second dielectric layer in described second opening, described second dielectric layer fills full described second opening.The excellent performance of the fin formula field effect transistor of the present invention.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to the formation side of a kind of fin formula field effect transistor
Method.
Background technology
MOS transistor is by applying voltage at grid, and regulation produces switch by the electric current of channel region
Signal.But when semiconductor technology enters 30 nanometers with lower node, traditional plane formula MOS transistor pair
The control ability of channel current dies down, and causes serious leakage current.Fin formula field effect transistor (FinFET)
Being a kind of emerging multi-gate device, it generally comprises and protrudes from the semiconductor fin of substrate surface, covering
The top of the described semiconductor fin of part and the grid structure of sidewall and be positioned at described grid structure both sides
Source region in semiconductor fin and drain region.Compared with planar MOS transistors, fin formula field effect transistor energy
Enough raising while keeping the lowest cut-off current drives electric current, it is possible to effectively suppress short-channel effect.
It addition, in order to improve the driving electric current of MOS transistor unit grid length in prior art, generally use
The method shortening channel length and reduction gate dielectric layer thickness, but reducing along with MOS transistor size,
Using above-mentioned means to improve drives the technology barrier of electric current to get more and more.In order to relax this situation, make
A kind of effective means are become as the channel material of MOS transistor with the semi-conducting material of high mobility.
Such as, owing to germanium or the electron mobility of SiGe and hole mobility are all than electron mobility and the sky of silicon
Cave mobility is high, so no matter pair nmos transistor or PMOS transistor uses germanium or SiGe conduct
Channel material can promote the driving electric current of MOS transistor.
Therefore, the heterogeneous of above-mentioned fin formula field effect transistor structure and high mobility semiconductor material is combined
Extension fin formula field effect transistor (Hetero epitaxial FinFET) structure has obtained more research recently.
Refer to Fig. 1, Fig. 1 is the cross-section structure signal that prior art forms hetero-epitaxy fin formula field effect transistor
Figure, including: Semiconductor substrate 100, the material of described Semiconductor substrate 100 is silicon；It is positioned at and described partly leads
Dielectric layer 101 on body substrate 100, described dielectric layer 101 has and exposes described Semiconductor substrate 100
Opening (not shown)；Being positioned at the fin 102 of described opening, the material of described fin 102 is germanium, institute
Stating fin 102 uses epitaxy technique to be formed.Dielectric layer 101 described in subsequent etching, make described fin 102 protrude
In the surface of described dielectric layer 101, formed and cover described fin 102 top and the grid structure of sidewall, then
Source region and drain region is formed in the fin 102 of described grid structure both sides.
But the performance of the hetero-epitaxy fin formula field effect transistor that prior art is formed is the best.
Summary of the invention
The problem that the present invention solves is the performance of the hetero-epitaxy fin formula field effect transistor that prior art is formed
The best.
For solving the problems referred to above, the invention provides the forming method of a kind of fin formula field effect transistor, bag
Include: providing Semiconductor substrate, described semiconductor substrate surface has first medium layer；Etch described first
Dielectric layer, forms the first opening exposing described Semiconductor substrate；Outside being formed in described first opening
Prolonging layer, described epitaxial layer fills full described first opening, and the carrier mobility of described epitaxial layer is more than institute
Stating the carrier mobility of Semiconductor substrate, described epitaxial layer has two end regions and zone line, described
The lattice defect of epitaxial layer two end regions is more than the lattice defect of zone line；Remove the two of described epitaxial layer
End regions, forms the second opening, and the zone line of residue epitaxial layer constitutes semiconductor fin；Described
Forming second dielectric layer in two openings, described second dielectric layer fills full described second opening.
Optionally, the material of described Semiconductor substrate is silicon, and the material of described epitaxial layer is germanium or SiGe.
Optionally, in described first opening, form epitaxial layer and use selective epitaxial process.
Optionally, described selective epitaxial process is ultra-high vacuum CVD or molecular beam epitaxy.
Optionally, the carrier mobility of described epitaxial layer is more than the carrier mobility of described Semiconductor substrate
Rate refers to: the electron mobility of described epitaxial layer is more than the electron mobility, described of described Semiconductor substrate
The hole mobility of epitaxial layer is more than the hole mobility of described Semiconductor substrate or described epitaxial layer
Electron mobility and hole mobility are respectively greater than electron mobility and the hole migration of described Semiconductor substrate
Rate.
Optionally, the rectangle being shaped as there is fillet of described first opening.
Optionally, described Semiconductor substrate is (100) crystal face, and the long limit of described rectangle is<100>crystal orientation.
Optionally, described epitaxial layer along the radius area at described first opening long side direction two ends be described outside
Prolong two end regions of layer, described epitaxial layer along the zone line of described first opening long side direction be described outside
Prolong the zone line of layer.
Optionally, the material of described first medium layer is silicon oxide.
Optionally, the material of described second dielectric layer is silicon oxide.
Optionally, in described second opening, form second dielectric layer and use atom layer deposition process.
Optionally, in described second opening, form second dielectric layer and use flowable chemical gaseous phase deposition
Technique.
Optionally, described flowable chemical vapor deposition method uses high-density plasma chemical gas phase
Depositing system, plasma reinforced chemical vapor deposition system or subatmospheric chemical gas-phase deposition system.
Optionally, the technique of two end regions removing described epitaxial layer includes: formed on said epitaxial layer there
Barrier layer, described barrier layer exposes two end regions of described epitaxial layer；With described barrier layer as mask,
Etch two end regions of described epitaxial layer, until exposing described semiconductor substrate surface；Remove described resistance
Barrier.
Optionally, described barrier layer is photoresist layer or hard mask layer.
Optionally, described second dielectric layer covers the top surface of described semiconductor fin.
Optionally, also include, after forming second dielectric layer in described second opening, grind described second
Dielectric layer, makes described second dielectric layer surface smooth.
Optionally, also include, after forming second dielectric layer in described second opening, to described quasiconductor
Fin carries out ion implanting, forms the well region of fin formula field effect transistor.
Optionally, also include, after the well region forming fin formula field effect transistor, etch described first and be situated between
Matter layer and described second dielectric layer, make the top surface of described semiconductor fin higher than described first medium layer and
The top surface of described second dielectric layer.
Optionally, also include, form the grid knot of semiconductor fin sidewall and top surface described in covering part
Structure；Source region and drain region is formed in the semiconductor fin of described grid structure both sides.
Compared with prior art, technical scheme has the advantage that
In the forming method of the fin formula field effect transistor of the embodiment of the present invention, etch semiconductor substrates surface
First medium layer, formed and expose the first opening of described Semiconductor substrate, in described first opening
It is epitaxially formed the epitaxial layer having than described Semiconductor substrate more high carrier mobility.Shape at epitaxial layer
During one-tenth, due to the self limiting of crystal material growth, the growth rate in each crystal orientation is different, follow-up shape
The epitaxial layer become has well-regulated geometry, and described first opening exists due to the restriction of photoetching process
, at the fillet of described first opening, there is multiple crystal orientation in fillet effect (Corner rounding)
(Crystalline orientations), causes in epitaxial process, produces a large amount of lattice defects at described fillet
(Crystalline defect).In the present embodiment, use etching technics to remove and have outside a large amount of lattice defect
Prolong layer two end regions, and retain the zone line of described epitaxial layer, as the fin field effect being subsequently formed
The semiconductor fin of transistor.Owing to the lattice defect of described semiconductor fin is less, follow-up well region,
In the ion implantation process in source region and drain region, there is not the dopant ion caused due to a large amount of lattice defects and expand
Dissipate passage, it is to avoid due to Impurity Distribution (the Non conformal dopant of the non-conformal that lattice defect causes
Distribution), the performance of the fin formula field effect transistor being subsequently formed beneficially is improved.
Further, in the forming method of the fin formula field effect transistor of the embodiment of the present invention, described extension
The electron mobility that material is germanium or SiGe, germanium or SiGe and the hole mobility of layer are respectively greater than silicon
The electron mobility of material and hole mobility so that formed hetero-epitaxy fin formula field effect transistor
Driving electric current increases.
Further, in the forming method of the fin formula field effect transistor of the embodiment of the present invention, described
Form second dielectric layer in two openings and use atom layer deposition process or flowable chemical gaseous phase deposition work
Skill, filling capacity is good, can avoid forming space and crack in the filling process.
Accompanying drawing explanation
Fig. 1 is the cross-section structure signal of the hetero-epitaxy fin formula field effect transistor forming process of prior art
Figure；
Fig. 2 is the top view of the hetero-epitaxy fin formula field effect transistor forming process of prior art；
Fig. 3 to Figure 13 is the structural representation of the fin formula field effect transistor forming process of the embodiment of the present invention
Figure.
Detailed description of the invention
From background technology, the performance of the hetero-epitaxy fin formula field effect transistor that prior art is formed is not
Good.
The present inventor forms the side of hetero-epitaxy fin formula field effect transistor by research prior art
Method, please continue to refer to Fig. 1, finds that prior art is by the dielectric layer 101 on etching semiconductor 100 surface
Form opening (not shown), then extension has the quasiconductor material of more high carrier mobility in described opening
Material forms fin 102.But when prior art is epitaxially formed fin 102 in described opening, do not consider institute
State the impact of the lattice quality of the shape of the opening fin 102 on being formed.It is existing for refer to Fig. 2, Fig. 2
There is the top view of the hetero-epitaxy fin formula field effect transistor forming process of technology, due to opening described in shape
Technique generally uses photoetching and etching technics, there is fillet effect (Corner in photo-etching technological process
Rounding) so that the drift angle of the opening formed is not right angle, but there is the arc of certain curvature,
There is a large amount of lattice defect in the two end regions 102a causing the follow-up fin 102 formed in described opening,
In the follow-up ion implantation process forming well region in described fin, lattice defect is as the expansion of dopant ion
Dissipate passage, deeper at the doping depth of described two end regions 102a, cause dopant ion to have non-conformal
Impurity Distribution (Non conformal dopant distribution), causes formed fin field effect then
The hydraulic performance decline of transistor.
Based on above research, the present inventor proposes the formation side of a kind of fin formula field effect transistor
Method, the first medium layer on etch semiconductor substrates surface, formed and expose the first of described Semiconductor substrate
Opening, is epitaxially formed in described first opening and has than described Semiconductor substrate more high carrier mobility
Epitaxial layer, remove and there is epitaxial layer two end regions of a large amount of lattice defect, and retain described epitaxial layer
Zone line, as the semiconductor fin of the fin formula field effect transistor being subsequently formed.Thus avoid
In follow-up ion implantation process, the dopant profiles of the non-conformal that a large amount of lattice defects cause, be conducive to carrying
The performance of high fin formula field effect transistor.
Understandable, below in conjunction with the accompanying drawings for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from
The specific embodiment of the present invention is described in detail.
It should be noted that provide the purpose of these accompanying drawings to contribute to understand embodiments of the invention, and
Should not be construed as the restriction improperly to the present invention.For the sake of becoming apparent from, shown in figure, size is not pressed
Ratio draw, may make amplify, reduce or other change.
Fig. 3 to Figure 13 is the structural representation of the forming process of the fin formula field effect transistor of the embodiment of the present invention
Figure.
Refer to Fig. 3, it is provided that Semiconductor substrate 200, described Semiconductor substrate 200 surface has first Jie
Matter layer 201.
In the present embodiment, described Semiconductor substrate 200 is silicon substrate or silicon-on-insulator substrate (SOI),
Follow-up formation in described Semiconductor substrate 200 has epitaxial germanium layer or the silicon of more high carrier mobility
Epitaxial germanium layer, as the channel material of fin formula field effect transistor to be formed, brilliant to improve fin field effect
The performance of body pipe.In other embodiments, described Semiconductor substrate 200 can also be germanium substrate, SiGe
Substrate, gallium arsenide substrate or germanium substrate on insulator, follow-up formation in described Semiconductor substrate 200
There is the epitaxial layer of more high carrier mobility.
The material of described first medium layer 201 is silicon oxide, silicon nitride, silicon oxynitride or other low Jie
Electric constant (low K) dielectric layer, for electric isolation, the technique forming described first medium layer 201 is
Chemical gaseous phase deposition or physical vapour deposition (PVD)；When the material of described first medium layer 201 is silicon oxide,
Described first medium layer 201 can also use thermal oxidation technology to be formed.In the present embodiment, described first is situated between
The material of matter layer 201 is silicon oxide.
Refer to the top view that Fig. 4 and Fig. 5, Fig. 5 are Fig. 4, etch described first medium layer 201, shape
Become to expose the first opening 202 of described Semiconductor substrate 200.
Concrete, described first medium layer 201 is formed patterned photoresist layer (not shown), institute
State patterned photoresist layer and expose first medium layer 201 table corresponding with the first aperture position to be formed
Face, with described patterned photoresist layer as mask, uses dry etch process to etch described first medium
Layer 201, until exposing described Semiconductor substrate 200 surface, forms the first opening 202, removes described
Patterned photoresist layer.In the present embodiment, reactive ion etching process is used to etch described first medium
Layer 201, described reactive ion etching process uses CF4And H2Mixed gas or CHF3And O2
Mixed gas.
Described first opening 202 exposes described Semiconductor substrate 200 surface, follow-up opens described first
It is epitaxially formed the epitaxial layer with described Semiconductor substrate 200 with consistent lattice structure in mouth 202.Need
Illustrate, in the forming process of described first opening 202, due to described patterned photoresist layer
Generally use photoetching process to be formed, but the reasons such as the diffraction of light source are easily caused optical lithography processes institute shape
There is fillet effect (Corner rounding), the i.e. drift angle of photoetching offset plate figure in the graphical photoresist layer become
It not right angle, but there is the arc of certain curvature.Then with the described graphical photoresist with fillet
Layer is also the figure with fillet for the first opening 202 that first medium layer 201 described in mask etching is formed.
Please continue to refer to Fig. 5, in the present embodiment, the layout-design of described first opening 202 is rectangle, but through light
The rectangle being shaped as there is fillet 202a of the first opening 202 carved and formed after etching technics.This reality
Executing in example, described Semiconductor substrate is (100) crystal face, the long edge of rectangle<100>of described first opening 202
Crystal orientation, the beneficially formation of subsequent epitaxial layer.But due to the existence of described fillet 202a, at described fillet
Multiple crystal orientation (Crystalline orientations) is there is at 202a, and due to the self limiting of crystal growth,
The epitaxial layer being subsequently formed has well-regulated geometric shape, easily produces a large amount of brilliant at described fillet 202a
Lattice defect (Crystalline defect).
Refer to the top view that Fig. 6 and Fig. 7, Fig. 7 are Fig. 6, at described first opening 202(with reference to figure
4) forming epitaxial layer 203 in, described epitaxial layer 203 fills full described first opening 202, described extension
The carrier mobility of layer 203 is more than the carrier mobility of described Semiconductor substrate 200.
Concrete, use selective epitaxial process to form epitaxial layer 203 in described first opening 202.Institute
Stating selective epitaxial process can be molecular beam epitaxy (MBE) or ultra-high vacuum CVD
(UHVCVD).Described selective epitaxial process, by regulation extension parameter, utilizes epitaxial material at silicon table
Face adsorb more than oxide or nitride to realize epitaxially grown selectivity, at described first opening
In 202, growth has the monocrystal material of same or like lattice arrangement, makes described monocrystal material fill full institute
State the first opening 202, form epitaxial layer 203.The carrier mobility of described epitaxial layer 203 is more than described
The carrier mobility of Semiconductor substrate 200, can be that the electron mobility of described epitaxial layer 203 is more than
The electron mobility of described Semiconductor substrate 200, is conducive to improving the performance of nmos pass transistor；Also may be used
To be the hole mobility hole mobility more than described Semiconductor substrate 200 of described epitaxial layer 203,
Be conducive to improving PMOS transistor performance；Can also is that electron mobility and the sky of described epitaxial layer 203
Cave mobility is respectively greater than electron mobility and the hole mobility of described Semiconductor substrate 200, is conducive to
Improve nmos pass transistor and PMOS transistor performance simultaneously.In the present embodiment, described Semiconductor substrate
The material of 200 is silicon, and the material of described epitaxial layer 203 is germanium or SiGe (SiGe), germanium and germanium silicon
Electron mobility and hole mobility are all higher than silicon, constitute heteroepitaxial structure, are conducive to improving simultaneously
Nmos pass transistor and the performance of PMOS transistor.In the present embodiment, form described epitaxial layer 203 and adopt
Use ultra-high vacuum CVD technique, when the material germanium of described epitaxial layer 203, reacting gas bag
Include GeH4；When the material of described epitaxial layer 203 is SiGe, reacting gas includes SiH4And GeH4；
Reaction temperature is 500 degrees Celsius～800 degrees Celsius.
It should be noted that in the present embodiment, being shaped as of described first opening 202 has fillet 202a
The rectangle of (with reference to Fig. 5), the epitaxial layer 203 therefore formed in described first opening 202 is also for having
The rectangle of fillet.Due to the self limiting of crystal material growth, the growth rate in each crystal orientation is different, such as
The growth rate of germanium and silicon germanium material<100>is the fastest,<110>take second place, and<111>take second place again so that end form
The epitaxial layer become has well-regulated geometric figure surface, in the present embodiment, the square of described first opening 202
The long edge of shape<100>crystal orientation,<010>crystal orientation, rectangle minor face edge, but due to the existence of described fillet 202a,
At described fillet 202a, there is multiple crystal orientation, cause in epitaxial process, produce at described fillet 202a
A large amount of lattice defects.Please continue to refer to Fig. 7, in the present embodiment, described epitaxial layer 203 has two end regions
203a and zone line 203b, described two end regions 203a refer to that described epitaxial layer 203 is opened along described first
The region of the fillet 202a at mouth 202 long side direction two ends, described zone line 203b refers to described extension
Layer 203 is along the zone line of described first opening 202 long side direction, due to the existence of described fillet 202a,
Cause the lattice of the lattice defect unnecessary zone line 203b of two end regions 203a of described epitaxial layer 203
Defect.A large amount of lattice defects that two end regions 203a of described epitaxial layer 203 exist, are being subsequently formed trap
The ion implantation process in district, source region and drain region, lattice defect is as the diffusion admittance of dopant ion, outside
The doping depth of the two end regions 203a prolonging layer 203 is deeper, causes dopant ion to have the impurity of non-conformal
Distribution (Non conformal dopant distribution), can cause formed fin field effect brilliant then
The hydraulic performance decline of body pipe.
Refer to the top view that Fig. 8 and Fig. 9, Fig. 9 are Fig. 8, remove two petiolareas of described epitaxial layer 203
Territory 203a(is with reference to Fig. 7), form the second opening 205, the zone line 203b(ginseng of residue epitaxial layer 203
Examine Fig. 7) constitute semiconductor fin 206.
Concrete, described semiconductor epitaxial layers 203 is formed barrier layer (not shown), described barrier layer
Expose two end regions 203a of described epitaxial layer 203.Described barrier layer can be photoresist layer, described
Photoresist layer uses photoetching process to be formed；Described barrier layer can also be hard mask layer, when described barrier layer
During for hard mask layer, described hard mask layer uses the etching technics after photoetching and photoetching to be formed.Described stop
Layer covers the zone line 203b of described epitaxial layer 203, exposes two end regions of described epitaxial layer 203
203a.Then, with described barrier layer as mask, dry etch process is used, such as reactive ion etching work
Skill, removes two end regions 203a of described epitaxial layer 203, until exposing described Semiconductor substrate 200
Surface, forms the second opening 205, and the zone line 203b of residue epitaxial layer 203 constitutes semiconductor fin
206.Finally, described barrier layer is removed.In the present embodiment, described barrier layer 204 is hard mask layer, can
To reduce during subsequent etching the lateral etching on the top to described epitaxial layer 203 zone line 203b,
Make the sidewall of zone line 203b after etching.The two end regions 203a due to described epitaxial layer 203
The a large amount of defect of middle existence, the performance of the fin formula field effect transistor that impact is subsequently formed, therefore in this step
Employing etching technics is removed, and only retains the zone line 203b of described epitaxial layer 203 as semiconductor fin
206, follow-up formation fin formula field effect transistor on the basis of described semiconductor fin 206.
Refer to Figure 10, in described second opening, 205(is with reference to Fig. 8) in formation second dielectric layer 207,
Described second dielectric layer 207 fills full described second opening 205.
In the present embodiment, in described second opening 205, form the technique of second dielectric layer 207 for flowing
Dynamic property chemical gaseous phase deposition (FCVD), the material of described second dielectric layer 207 is silicon oxide.Flowable
Property chemical gaseous phase deposition by promoting the mobility of deposition material, it is to avoid formed in the filling process lacks
Fall into, it is to avoid in the filling process of high aspect ratio trench quite, form space and crack.Described flowable chemistry
Gas-phase deposition can use high density plasma CVD (HDP-CVD) system, etc.
Gas ions strengthens chemical gaseous phase deposition (PECVD) system or subatmospheric chemical gaseous phase deposition
(SACVD) system.Use flowable chemical vapor deposition method shape in described second opening 205
Becoming after second dielectric layer 207, described second dielectric layer 207 fills full described second opening 205, and described the
Second medium layer 207 also covers the top surface of described semiconductor fin 206.In the present embodiment, described
After forming second dielectric layer 207 in two openings 206, CMP process is also used to grind described the
Second medium layer 207, the surface making described second dielectric layer 207 is smooth.
In other embodiments, in described second opening, form second dielectric layer and can also use atomic layer
Depositing operation (ALD) technique.Atom layer deposition process forms deposition by chemisorbed and monolayer growth
Thin film, it also has preferably filling capacity, it is to avoid formed in the filling process of high aspect ratio trench quite
Space and crack, decrease the impact on the fin formula field effect transistor performance being subsequently formed.
Refer to Figure 11, etch described first medium layer 201 and described second dielectric layer 207, make described
The top surface of semiconductor fin 206 is higher than described first medium layer 201 and described second dielectric layer 207
Top surface.
In the present embodiment, before etching described first medium layer 201 and described second dielectric layer 207,
Described semiconductor fin 206 carries out ion implanting, and the well region forming fin formula field effect transistor (does not shows
Go out).When fin formula field effect transistor to be formed is PMOS transistor, described semiconductor fin is carried out
N-type ion implanting, forms N-type well region, and described N-type ion can be phosphonium ion, arsenic ion or antimony
Ion；When fin formula field effect transistor to be formed is nmos pass transistor, described semiconductor fin is entered
Row p-type ion implanting, formed P type trap zone, described p-type ion can be boron ion, indium ion or
Gallium ion.Owing to the semiconductor fin in the present embodiment is by the zone line 203b of described epitaxial layer 203
Constituting (with reference to Fig. 7), the two end regions 203a with a large amount of lattice defect have been removed by, and there is not crystalline substance
The impurity diffusion admittance that lattice defect causes, the well region formed after ion implanting is conformal Impurity Distribution,
Beneficially improve the performance of the fin formula field effect transistor being subsequently formed.
Described semiconductor fin 206 is being carried out ion implanting, after forming well region, is using dry etching
Technique, such as reactive ion etching process, etches described first medium layer 201 and described second dielectric layer 207,
Make the top surface of described semiconductor fin 206 higher than described first medium layer 201 and described second dielectric layer
The top surface of 207.Described dry etch process has higher selectivity, can be situated between in etching described first
While matter layer 201 and described second dielectric layer 207, the damage to described semiconductor fin 206 is less.
In the present embodiment, the material of described first medium layer 201 and described second dielectric layer 207 is silicon oxide,
After etching technics, the top surface of described first medium layer 201 and described second dielectric layer 207 flushes.
Described semiconductor fin 206 is made to protrude from described first medium layer 201 and described second dielectric layer 207
Top surface, when being conducive to being subsequently formed grid structure, described grid structure partly can be led with described in covering part
The top surface of body fin 206 and sidewall surfaces, form multi-gate structure.
Refer to the perspective view that Figure 12 and Figure 13, Figure 13 are Figure 12, form covering part institute
State the grid structure (not shown) of semiconductor fin 206 sidewall and top surface；In described grid structure both sides
Semiconductor fin 206 in form source region and drain region (not shown).
Described grid structure includes semiconductor fin 206 sidewall described in covering part and the gate medium of top surface
Layer (not shown), the gate electrode 208 being positioned on described gate dielectric layer, it is positioned at described gate dielectric layer and described
The side wall 209 of gate electrode 208 sidewall surfaces.When fin formula field effect transistor to be formed is NMOS,
Source region and the drain region of N-type is formed in the semiconductor fin 206 of described grid structure both sides；When to be formed
When fin formula field effect transistor is PMOS, shape in the semiconductor fin 206 of described grid structure both sides
Become p-type source region and drain region.The technique forming described grid structure, described source region and drain region refer to existing
Technique, does not repeats them here.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, all can make various changes or modifications, therefore the guarantor of the present invention
The scope of protecting should be as the criterion with claim limited range.
Claims (20)
1. the forming method of a fin formula field effect transistor, it is characterised in that including:
Thering is provided Semiconductor substrate, described semiconductor substrate surface has first medium layer；
Etch described first medium layer, form the first opening exposing described Semiconductor substrate；
Forming epitaxial layer in described first opening, described epitaxial layer fills full described first opening, described outside
Prolonging the carrier mobility carrier mobility more than described Semiconductor substrate of layer, described epitaxial layer has
Two end regions and zone line, the lattice defect of described epitaxial layer two end regions is more than the lattice of zone line
Defect；
Removing two end regions of described epitaxial layer, form the second opening, the zone line of residue epitaxial layer is constituted
Semiconductor fin；
Forming second dielectric layer in described second opening, described second dielectric layer fills full described second opening.
2. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that described half
The material of conductor substrate is silicon, and the material of described epitaxial layer is germanium or SiGe.
3. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that described
Form epitaxial layer in first opening and use selective epitaxial process.
4. the forming method of fin formula field effect transistor as claimed in claim 3, it is characterised in that described choosing
Selecting property epitaxy technique is ultra-high vacuum CVD or molecular beam epitaxy.
5. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that outside described
The carrier mobility prolonging layer refers to more than the carrier mobility of described Semiconductor substrate: described extension
The electron mobility of layer is moved more than the electron mobility of described Semiconductor substrate, the hole of described epitaxial layer
Shifting rate more than the hole mobility of described Semiconductor substrate or the electron mobility of described epitaxial layer and
Hole mobility is respectively greater than electron mobility and the hole mobility of described Semiconductor substrate.
6. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that described the
The rectangle being shaped as there is fillet of one opening.
7. the forming method of fin formula field effect transistor as claimed in claim 6, it is characterised in that described half
Conductor substrate is (100) crystal face, and the long limit of described rectangle is<100>crystal orientation.
8. the forming method of fin formula field effect transistor as claimed in claim 6, it is characterised in that outside described
Prolong the layer two end regions that radius area is described epitaxial layer along described first opening long side direction two ends,
Described epitaxial layer is along the mesozone that zone line is described epitaxial layer of described first opening long side direction
Territory.
9. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that described the
The material of one dielectric layer is silicon oxide.
10. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that described the
The material of second medium layer is silicon oxide.
The forming method of 11. fin formula field effect transistors as claimed in claim 1, it is characterised in that described
Form second dielectric layer in second opening and use atom layer deposition process.
The forming method of 12. fin formula field effect transistors as claimed in claim 1, it is characterised in that described
Form second dielectric layer in second opening and use flowable chemical vapor deposition method.
The forming method of 13. fin formula field effect transistors as claimed in claim 12, it is characterised in that described can
Mobility chemical vapor deposition method uses high density plasma CVD system, plasma
Body strengthens chemical gas-phase deposition system or subatmospheric chemical gas-phase deposition system.
The forming method of 14. fin formula field effect transistors as claimed in claim 1, it is characterised in that remove institute
The technique of two end regions stating epitaxial layer includes: form barrier layer, described stop on said epitaxial layer there
Layer exposes two end regions of described epitaxial layer；With described barrier layer as mask, etch described epitaxial layer
Two end regions, until exposing described semiconductor substrate surface；Remove described barrier layer.
The forming method of 15. fin formula field effect transistors as claimed in claim 14, it is characterised in that described resistance
Barrier is photoresist layer or hard mask layer.
The forming method of 16. fin formula field effect transistors as claimed in claim 1, it is characterised in that described
Second medium layer covers the top surface of described semiconductor fin.
The forming method of 17. fin formula field effect transistors as claimed in claim 1, it is characterised in that also include,
After forming second dielectric layer in described second opening, grind described second dielectric layer, make described second
Dielectric layer surface is smooth.
The forming method of 18. fin formula field effect transistors as claimed in claim 1, it is characterised in that also include,
After forming second dielectric layer in described second opening, described semiconductor fin is carried out ion implanting,
Form the well region of fin formula field effect transistor.
The forming method of 19. fin formula field effect transistors as claimed in claim 18, it is characterised in that also include,
After the well region forming fin formula field effect transistor, etch described first medium layer and described second medium
Layer, makes the top surface of described semiconductor fin higher than described first medium layer and described second dielectric layer
Top surface.
The forming method of 20. fin formula field effect transistors as claimed in claim 19, it is characterised in that also include,
Form semiconductor fin sidewall and the grid structure of top surface described in covering part；At described grid structure
Source region and drain region is formed in the semiconductor fin of both sides.
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| US6287904B1 (en) * | 2000-01-27 | 2001-09-11 | Advanced Micro Devices, Inc. | Two step mask process to eliminate gate end cap shortening |
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| US6287904B1 (en) * | 2000-01-27 | 2001-09-11 | Advanced Micro Devices, Inc. | Two step mask process to eliminate gate end cap shortening |
| CN102347350A (en) * | 2010-07-30 | 2012-02-08 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
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