CN105702579B - Manufacturing method of epitaxial channel on fin and fin field effect transistor - Google Patents
Manufacturing method of epitaxial channel on fin and fin field effect transistor Download PDFInfo
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- CN105702579B CN105702579B CN201410681972.1A CN201410681972A CN105702579B CN 105702579 B CN105702579 B CN 105702579B CN 201410681972 A CN201410681972 A CN 201410681972A CN 105702579 B CN105702579 B CN 105702579B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 34
- 230000005669 field effect Effects 0.000 title claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 230000001590 oxidative effect Effects 0.000 claims description 14
- 150000002500 ions Chemical class 0.000 claims description 8
- 238000010992 reflux Methods 0.000 claims description 8
- 150000001875 compounds Chemical class 0.000 claims description 7
- 229910052986 germanium hydride Inorganic materials 0.000 claims description 4
- 238000002309 gasification Methods 0.000 claims description 3
- LDDQLRUQCUTJBB-UHFFFAOYSA-N ammonium fluoride Chemical compound [NH4+].[F-] LDDQLRUQCUTJBB-UHFFFAOYSA-N 0.000 claims description 2
- 238000013508 migration Methods 0.000 claims 1
- 230000005012 migration Effects 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 13
- 238000000407 epitaxy Methods 0.000 abstract 1
- 239000000463 material Substances 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 239000008246 gaseous mixture Substances 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 101100373011 Drosophila melanogaster wapl gene Proteins 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- VDGJOQCBCPGFFD-UHFFFAOYSA-N oxygen(2-) silicon(4+) titanium(4+) Chemical compound [Si+4].[O-2].[O-2].[Ti+4] VDGJOQCBCPGFFD-UHFFFAOYSA-N 0.000 description 1
- 210000004483 pasc Anatomy 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
- H01L29/7854—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection with rounded corners
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a method for manufacturing a fin of a fin field effect transistor, which comprises the following steps: providing a substrate, wherein fins which are mutually isolated are formed in the substrate; performing pre-baking before fin epitaxy to remove a natural oxide layer on the fin, and reflowing the fin in a pre-baking chamber; an epitaxial layer is grown on the fin. In the invention, after reflow, the height of the fin is reduced, the original doping residue in the channel region can move downwards to the lower part of the fin, and the regrown epitaxial layer is used as a part or a new channel, so that the device has better device characteristics.
Description
Technical field
The invention belongs to epi channels in field of semiconductor manufacture more particularly to a kind of fin formula field effect transistor, fin
Manufacturing method.
Background technology
Highly integrated with semiconductor devices, the short-channel effect of the MOSFET element of plane is more notable, is degrading
The performance of device.
Currently, in order to solve the problems, such as short-channel effect, it is proposed that the three-dimensional device of fin formula field effect transistor (Fin-FET)
Part structure, Fin-FET are the transistors for having fin channel structure, it using several surfaces of thin fin as raceway groove, so as to
To prevent the short-channel effect in conventional transistor, while operating current can be increased.
In Fin-FET device fabrications, due to PTSL (Punch Though Stop Layer, break-through stop-layer)
Deng the doping in channel region so that channel region remains unwanted impurity, increases the scattering of channel region, influences the performance of device.
Invention content
It is an object of the invention to overcome deficiency in the prior art, a kind of fin formula field effect transistor, outer on fin is provided
The manufacturing method for prolonging raceway groove improves the stress of source-drain area.
To achieve the above object, the technical scheme is that：
The manufacturing method of epi channels on a kind of fin, including step：
Substrate is provided, mutually isolated fin is formed in substrate；
Ion implanting is carried out, to form break-through stop-layer；
The front baking before fin extension is carried out, to remove the natural oxidizing layer on fin, and fin is returned in the chamber of front baking
Stream, makes the height of fin reduce, and the original doping residual of channel region is displaced downwardly to the lower part of fin；
In fin growing epitaxial layers；
Front baking refers to reacting to generate compound with the natural oxidizing layer on fin by the gas in chamber, and compound is gasifying
It is detached afterwards from fin surface；
Reflux refers to changing gas pressure intensity and/or temperature in chamber, so that the height of fin is reduced, the atom of fin rearranges.
Optionally, the mobility for stating epitaxial layer is more than the mobility of fin.
Optionally, the substrate is SOI or GOI substrates.
Optionally, the gas of front baking is H2Or H2With HCl, NH4F or GeH4Mixed gas or HF and N2Mixing
Gas.
Optionally, when removing removing natural oxidizing layer, the pressure of chamber indoor gas holds in the palm for 20-2000, and the temperature of cavity is 450-
1150℃。
Optionally, when flowing back to fin, the pressure of chamber indoor gas is -200 support of 50 millitorr, and the temperature of cavity is 450-
1150℃。
Optionally, when removing removing natural oxidizing layer, the pressure of chamber indoor gas holds in the palm for 250-1000, and the temperature of cavity is 700-
850℃。
Optionally, when flowing back to fin, the pressure of chamber indoor gas holds in the palm for 1-100, and the temperature of cavity is 700-850
℃。
Optionally, the thickness range of epitaxial layer is 1-100nm.
Optionally, the thickness range of epitaxial layer is 5-40nm.
In addition, the present invention also provides a kind of manufacturing method of fin formula field effect transistor, any of the above-described manufacturer is utilized
Method forms epi channels on fin.
The manufacturing method of epi channels on the fin formula field effect transistor of the embodiment of the present invention, fin, before being carried out to whole fin
It dries, and flows back to fin in the chamber of front baking, then, carry out the extension of fin, so that the height of fin reduces after reflux, raceway groove
The original doping residual in area can be displaced downwardly to the lower part of fin, and the epitaxial layer to regrow has more preferable as part or new raceway groove
Device property.Meanwhile the atom for the skeg that flows back rearranges, and reduces the defects of fin, to improve subsequent epitaxial layer
Quality.
Further, the fin after reflux is easy to the higher-quality epitaxial layer of extension, the epitaxial layer of extension mobility bigger,
The carrier mobility that will further improve raceway groove improves the speed of device.
Description of the drawings
It, below will be to attached drawing needed in the embodiment in order to illustrate more clearly of the technical solution that the present invention is implemented
It is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, general for this field
For logical technical staff, without creative efforts, other drawings may also be obtained based on these drawings.
Fig. 1 is the flow chart according to the manufacturing method of the fin formula field effect transistor source-drain area of the present invention；
Fig. 2A-Fig. 6 B are the solid in each manufacturing process for manufacture fin formula field effect transistor according to the embodiment of the present invention
Structural schematic diagram, wherein Fig. 2A -6A are the schematic cross-section of the transistor of the cross-sectional direction along fin, and Fig. 2 B-6B are along fin
The diagrammatic cross-section of the transistor of length direction；
The epitaxial layer of the fin of Fig. 7 A and 7B respectively conventional manufacturing process, the formation of the manufacturing process of the embodiment of the present invention exists
Schematic cross-section under microscope.
Specific implementation mode
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, below in conjunction with the accompanying drawings to the present invention
Specific implementation mode be described in detail.
Many details are elaborated in the following description to facilitate a thorough understanding of the present invention, still the present invention can be with
Implemented different from other manner described here using other, those skilled in the art can be without prejudice to intension of the present invention
In the case of do similar popularization, therefore the present invention is not limited by following public specific embodiment.
Secondly, combination schematic diagram of the present invention is described in detail, when describing the embodiments of the present invention, for purposes of illustration only, table
Show that the sectional view of device architecture can disobey general proportion and make partial enlargement, and the schematic diagram is example, is not answered herein
Limit the scope of protection of the invention.In addition, three-dimensional space that should be comprising length, width and depth in actual fabrication.
The present invention proposes a kind of manufacturing method of fin formula field effect transistor fin, including：Substrate is provided, is formed in substrate
There is mutually isolated fin；The front baking before fin extension is carried out, to remove the natural oxidizing layer on fin, and to fin in the chamber of front baking
It flows back；In fin growing epitaxial layers.
In the present invention, front baking is carried out to whole fin, and flowed back to fin in the chamber of front baking, then, carry out fin
Extension, so that the height of fin reduces after reflux, the original doping residual of channel region can be displaced downwardly to the lower part of fin, regrow
Epitaxial layer has better device property as part or new raceway groove, undoped residual.Meanwhile the atom for the skeg that flows back
It rearranges, reduces the defects of fin, to improve the quality of subsequent epitaxial layer.
It should be noted that in the attached drawing of the present invention, the attached drawing of same sequence number is same manufacture such as Fig. 2A and Fig. 2 B
The schematic cross-section of the different directions of transistor in the process, wherein Fig. 2A -6A are cutting for the transistor of the cross-sectional direction along fin
Face schematic diagram, i.e. Fig. 2 B-6B are the cross-sectional view of the transistor along fin extending direction.
Technical solution in order to better understand the present invention and technique effect, below with reference to specific flow diagram figure
1 pair of specific embodiment is described in detail.
First, in step S01, provide substrate 100, mutually isolated fin 110 be formed in substrate 100, with reference to figure 4A and
Shown in Fig. 4 B.
In the present invention, the substrate 100 can be Si substrates, Ge substrates, SiGe substrate, SOI (silicon-on-insulator,
Silicon On Insulator) or GOI (germanium on insulator, Germanium On Insulator) etc., the substrate may be used also
Think that the substrate including other elements semiconductor or compound semiconductor, such as GaAs, InP or SiC etc. can also be lamination knot
Structure, such as Si/SiGe etc. can be with other epitaxial structures, such as SGOI (silicon germanium on insulator) etc..In the present embodiment, institute
It is body silicon substrate to state substrate, with reference to shown in figure 2A.
In a specific embodiment, fin 110 and isolation 120 can be provided as follows.
First, the first hard mask 104 is formed on the substrate 100 of body silicon, such as silicon nitride；Then, using lithographic technique, example
Such as the method for RIE (reactive ion etching), etched substrate 100 forms fin 102, so as to form the fin 102 on substrate 100,
As shown in Figure 2 A and 2B.
Then, as shown in Figure 3A and Figure 3B, the filling of isolated material 106 is carried out, isolated material for example can be titanium dioxide
Silicon is then planarized, until exposing the upper surface of fin 102, then, can use wet etching, such as use hydrofluoric acid
The isolated material of the certain thickness silica of erosion removal, the isolated material of member-retaining portion between fin 102, so as to form
Isolation 110, with reference to shown in figure 4A and Fig. 4 B.
Then, in step S02, the front baking before fin extension is carried out, to remove the natural oxidizing layer on fin, and in the chamber of front baking
It flows back to fin in room, with reference to shown in figure 6A and Fig. 6 B.
In the manufacturing process of body silicon substrate, is formed after fin, as shown in Figure 4 A and 4 B shown in FIG., usually to carry out ion note
Enter, to form break-through stop-layer (Punch Though Stop Layer, PTSL) 108 under the raceway groove of fin.Normally, PTSL
The angular range of ion implanting is 0-45 °, and dosage range is 1E12 to 1E14cm-2, energy range is 10 to 150KEV.In this reality
It applies in example, the angular range of PTSL ion implantings is 0-7 °, and dosage range is 5E12 to 5E13cm-2, energy range be 30 to
80KEV.Normally, PTSL ion implantings use the ion that opposite types are injected with source and drain, and for N-type device, implanting p-type is miscellaneous
Matter, such as B etc.；For P-type device, N-type impurity, for example, As or P etc. are injected.Break-through is formed in the ion implanting for forming PTSL
After stop-layer, in channel region, there is also non-uniform doping concentrations for meeting, this makes the knot between channel region and source-drain area
Pattern tilt, the working condition of device is had an impact, the deterioration of device performance is caused.
In the present embodiment, after forming break-through stop-layer, front baking and reflux technique are carried out.Front baking before fin extension
In processing step, the natural oxidizing layer on fin is removed, so as to subsequently in fin growing epitaxial layers, in front baking technique, usually
It is that compound is generated with oxidation pasc reaction by the gas in chamber, the melting point compound of generation is low, is easy gasification, after gasification
It is detached from fin surface, to achieve the purpose that remove fin oxide on surface, the gas of front baking can be H2、H2With the gaseous mixture of HCl
Body, H2With NH4The mixed gas of F, H2With GeH4Mixed gas or HF and N2Mixed gas etc..
Removal and the reflow step of natural oxidizing layer are carried out in the chamber for the front baking for removing removing natural oxidizing layer.Specifically
, first, the removal of natural oxidizing layer is carried out in the chamber of front baking, the gas of front baking can be H2、H2With the gaseous mixture of HCl
Body, H2With NH4The mixed gas of F, H2With GeH4Mixed gas or HF and N2Mixed gas, in the process, in chamber
The pressure of gas is that 20-2000 holds in the palm (torr), and the temperature of cavity is 450-1150 DEG C, in a preferred embodiment, chamber Indoor Air
The pressure of body holds in the palm for 250-1000, and the temperature of cavity is 700-850 DEG C；Then, in the chamber, change the indoor pressure of chamber
And/or temperature, the reflux (re-flow) of fin is carried out, in the process, the pressure of chamber indoor gas is -200 support of 50 millitorr, chamber
The temperature of body is 450-1150 DEG C, and in preferred embodiment, the pressure of chamber indoor gas holds in the palm for 1-100, and the temperature of cavity is
700-850℃.Upon reflowing, with reference to shown in figure 5A and Fig. 5 B, the height of fin reduces, and the original doping residual of channel region can move down
To the lower part of fin, the atom of fin rearranges, and reduces the defects of fin, is conducive to the quality for improving subsequent epitaxial.
In the present embodiment, H is used in the chamber of front baking2Or H2With the mixed gas of HCl, after reflux, with reference to figure 7B institutes
Show, fin forms the polyhedron with (111) face, and the polyhedron is shorter wider.
In step S03, in fin growing epitaxial layers 103, with reference to shown in figure 6A and 6B.
Selective epitaxial process may be used, carry out the growth of the epitaxial layer of fin, the thickness of epitaxial layer can be 1-
The atom of 100nm, the fin after being flowed back have re-started arrangement, more conducively improve the quality of epitaxial layer, meanwhile, channel region is former
Some doping residuals can be displaced downwardly to the lower part of fin, and the epitaxial layer to regrow is as partly or new raceway groove, undoped residual,
With better device property.
In a preferred embodiment, epitaxial layer selection mobility is formed higher than the material of fin, and thickness range can be 5-
40nm in this way, will further improve the carrier mobility of raceway groove, and then improves the speed of device.Such as the fin for silicon, outside
Prolong the material or two or more compound-materials constituted that the single-element that layer can be four races is constituted, such as germanium silicon, carbon silicon
Deng；Can also be three-five material single-element constitute material or two or more constitute compound-materials, such as GaAs,
InP etc..
With reference to shown in figure 7A and 7B, Fig. 7 A and 7B are respectively the manufacturing process of routine, the manufacturing process of the embodiment of the present invention
The schematic cross-section of the epitaxial layer of the fin of formation under the microscope, it can be seen that the epitaxial layer of the embodiment of the present invention has better
Epitaxial quality and pattern.
So far, the fin with epitaxial layer of the embodiment of the present invention is formd, then, the follow-up manufacture work of device can be completed
Skill, such as gate dielectric layer, grid and side wall and source-drain area etc. are continuously formed on epitaxial layer.
Although the present invention has been disclosed in the preferred embodiments as above, however, it is not intended to limit the invention.It is any to be familiar with ability
The technical staff in domain, without departing from the scope of the technical proposal of the invention, all using in the methods and techniques of the disclosure above
Appearance makes many possible changes and modifications to technical solution of the present invention, or is revised as the equivalent embodiment of equivalent variations.Therefore,
Every content without departing from technical solution of the present invention is made to the above embodiment any simple according to the technical essence of the invention
Modification, equivalent variations and modification, in the range of still falling within technical solution of the present invention protection.
Claims (11)
1. the manufacturing method of epi channels on a kind of fin, which is characterized in that including step：
Substrate is provided, mutually isolated fin is formed in substrate；
Ion implanting is carried out, to form break-through stop-layer；
The front baking before fin extension is carried out, to remove the natural oxidizing layer on fin, and flows back, makes to fin in the chamber of front baking
The height of fin reduces, and the original doping residual of channel region is displaced downwardly to the lower part of fin；
In fin growing epitaxial layers；
Front baking refer to reacted with the natural oxidizing layer on fin by the gas in chamber generate compound, compound after gasification from
Fin surface detaches；
Reflux refers to changing gas pressure intensity and/or temperature in chamber, so that the height of fin is reduced, the atom of fin rearranges.
2. manufacturing method according to claim 1, which is characterized in that the mobility of the epitaxial layer is more than the migration of fin
Rate.
3. manufacturing method according to claim 1, which is characterized in that the substrate is SOI or GOI substrates.
4. manufacturing method according to claim 1, which is characterized in that the gas of front baking is H2Or H2With HCl, NH4F or
GeH4Mixed gas or HF and N2Mixed gas.
5. manufacturing method according to claim 1, which is characterized in that when removing removing natural oxidizing layer, the pressure of chamber indoor gas
It is held in the palm for 20-2000 by force, the temperature of cavity is 450-1150 DEG C.
6. manufacturing method according to claim 1, which is characterized in that when flowing back to fin, the pressure of chamber indoor gas
Temperature for -200 support of 50 millitorr, cavity is 450-1150 DEG C.
7. manufacturing method according to claim 1, which is characterized in that when removing removing natural oxidizing layer, the pressure of chamber indoor gas
It is held in the palm for 250-1000 by force, the temperature of cavity is 700-850 DEG C.
8. manufacturing method according to claim 7, which is characterized in that when flowing back to fin, the pressure of chamber indoor gas
It is held in the palm for 1-100, the temperature of cavity is 700-850 DEG C.
9. manufacturing method according to claim 1, which is characterized in that the thickness range of epitaxial layer is 1-100nm.
10. manufacturing method according to claim 1, which is characterized in that the thickness range of epitaxial layer is 5-40nm.
11. a kind of manufacturing method of fin formula field effect transistor, which is characterized in that described in any one of claim 1-10
Fin on epi channels manufacturing method.
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| CN201410681972.1A CN105702579B (en) | 2014-11-24 | 2014-11-24 | Manufacturing method of epitaxial channel on fin and fin field effect transistor |
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| CN201410681972.1A CN105702579B (en) | 2014-11-24 | 2014-11-24 | Manufacturing method of epitaxial channel on fin and fin field effect transistor |
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| CN105702579B true CN105702579B (en) | 2018-09-11 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102496574A (en) * | 2011-11-17 | 2012-06-13 | 上海华力微电子有限公司 | Pretreatment method for SiGe selective epitaxial growth |
| CN103227200A (en) * | 2012-01-31 | 2013-07-31 | 台湾积体电路制造股份有限公司 | Finfet and method of fabricating the same |
| CN104022037A (en) * | 2013-02-28 | 2014-09-03 | 中芯国际集成电路制造(上海)有限公司 | Fin type field effect transistor and forming method thereof |
-
2014
- 2014-11-24 CN CN201410681972.1A patent/CN105702579B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102496574A (en) * | 2011-11-17 | 2012-06-13 | 上海华力微电子有限公司 | Pretreatment method for SiGe selective epitaxial growth |
| CN103227200A (en) * | 2012-01-31 | 2013-07-31 | 台湾积体电路制造股份有限公司 | Finfet and method of fabricating the same |
| CN104022037A (en) * | 2013-02-28 | 2014-09-03 | 中芯国际集成电路制造(上海)有限公司 | Fin type field effect transistor and forming method thereof |
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