CN105700604B - A low voltage source coupled exclusive OR logic circuit structure - Google Patents
A low voltage source coupled exclusive OR logic circuit structure Download PDFInfo
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- CN105700604B CN105700604B CN201410701629.9A CN201410701629A CN105700604B CN 105700604 B CN105700604 B CN 105700604B CN 201410701629 A CN201410701629 A CN 201410701629A CN 105700604 B CN105700604 B CN 105700604B
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Abstract
The invention provides a low voltage source coupled exclusive OR logic circuit structure comprising two differential pairs of NMOS input, which are a differential pair A and a differential pair B, a differential pair C of PMOS input, and a bias current source N1, a bias current source N2 and a bias current source P3 which provide bias current for the differential pair A, the differential pair B, and differential pair C respectively. A path of differential complementary input signals AP, AN is connected with complementary input ends of the differential pair A and the differential pair B; inverted complementary input ends of the differential pair A and the differential pair B are connected and same-phase complementary output ends of the differential pair A and the differential pair B are connected; another path of differential complementary input signals BP, BN is connected with a complementary input end of the differential pair C; a complementary output end of the differential pair C is connected with the bias current input ends of the differential pair A and the differential pair B. By using a folding method, the number of vertically superimposed layers of a traditional circuit is reduced and the problem that the requirement for low voltage cannot be met along with the reduction of technological line width and reduction of required power voltage.
Description
Technical field
The present invention relates to XOR circuit, particularly a kind of low pressure source coupling XOR circuit structure.
Background technology
The circuit structure of conventional source coupling XOR includes：The differential pair of two pairs of NMOS inputs, the PMOS of a pair of laminations are defeated
Differential pair, load and the bias current sources for entering.The laminated circuit structure that it is adopted, it is desirable to which supply voltage could be protected in certain value
Card normal circuit operation.But as the raising of modern technology, technique live width are less and less, result in required supply voltage and get over
Come less, traditional XOR circuit structure cannot meet more low voltage operating requirement.
The content of the invention
It is an object of the invention to overcome the deficiencies in the prior art, there is provided a kind of low pressure source coupling XOR circuit structure,
Method using folding, reduces the conventional source coupling XOR circuit superposition number of plies in vertical direction, so as to reduce required power supply electricity
Pressure, makes in the case of at low pressure, and it can work more more preferable than conventional source coupling XOR circuit.
The purpose of the present invention is achieved through the following technical solutions：It include the differential pair A of two NMOS input and
The differential pair C that differential pair B, a PMOS are input into, and respectively to differential pair A, differential pair B and differential pair C offer bias current
Bias current sources N1, bias current sources N2 and bias current sources P3；All the way differential complement input signal AP, AN respectively with difference
Complementary input end connection to A and differential pair B, the reverse complement input interconnection of differential pair A and differential pair B, differential pair A and difference
The homophase complementary output end to B is divided to interconnect；The complementary input end of another road differential complement input signal BP, BN and differential pair C connects
Connect, the complementary output end of differential pair C is connected respectively with the bias current inputs of differential pair A and differential pair B.
Described bias current sources N1 and bias current sources N2 are mainly made up of NMOS tube.
Described bias current sources P3 are mainly made up of PMOS.
When AP is identical with BP, OUTP is output as ' 0 '；As AP and BP different, OUTP is output as ' 1 '；When AN and BN phases
Meanwhile, OUTN is output as ' 0 '；As AN and BN different, OUTN is output as ' 1 '.
The invention has the beneficial effects as follows：The conventional source coupling XOR circuit superposition number of plies in vertical direction is reduced, so as to
Reduce required supply voltage；Solve the problems, such as that the less and less caused supply voltage of technique live width is more and more lower, lower
The situation of pressure can also normal work.
Description of the drawings
Fig. 1 is schematic structural view of the invention；
Fig. 2 is circuit structure diagram of the present invention；
Fig. 3 is conventional source coupling XOR circuit structure chart.
Specific embodiment
Technical scheme is described in further detail below in conjunction with the accompanying drawings, but protection scope of the present invention is not limited to
Described below.
As shown in Figure 1 and Figure 2, a kind of low pressure source coupling XOR circuit structure, it includes：The difference of two pairs of NMOS tube inputs
Divide to A, B, the differential pair C of a pair of PMOS inputs, load and respectively to differential pair A, differential pair B and differential pair C offer biasing
Bias current sources N1 of electric current, bias current sources N2 and bias current sources P3, the differential pair A of the NMOS tube input includes the 4th
NMOS tube N4, the 5th NMOS tube N5, differential pair B includes the 6th NMOS tube N6 and the 7th NMOS tube N7, the difference of PMOS input
To including the first PMOS P1 and the second PMOS P2, the load includes two resistance R1 and resistance R2；The bias current
The source ground of source N1 and N2；The source electrode of the 4th NMOS tube N4, the 5th NMOS tube N5 and the second PMOS P2 connects, and with
The drain electrode of bias current sources N1 connects, and the source electrode of the 6th NMOS tube N6, the 7th NMOS tube N7 and the first PMOS P1 connects,
And connect with the drain electrode of bias current sources N2；4th NMOS tube N4, the drain electrode of the 6th NMOS tube N6 connect as difference letter
Number output end OUTP, and connect with one end of load resistance R1, the 5th NMOS tube N5, the drain electrode of the 7th NMOS tube N7 connect
As differential signal outputs OUTN, and it is connected with one end of load resistance R2, the grid and the 6th of the 5th NMOS tube N5
The grid connection of NMOS tube N6, the drain electrode of first PMOS P1 and the second PMOS P2 and the source electrode phase of bias current sources P3
Connect, the drain electrode of bias current sources P3 connects respectively with the other end of load R1, R2.
4th NMOS tube N4, input signal AN of the 7th NMOS tube N7 grid and the 5th NMOS tube N5, the 6th NMOS tube N6
Input signal AP of grid is differential complement input signal；Input signal BP and the second PMOS P2 of the first PMOS P1 grid
Input signal BN of grid is differential complement input signal；Output signal OUTP and output signal OUTN are differential complement output letters
Number.
As shown in Fig. 2 when BP is ' 1 ', then BN is ' 0 ' naturally, then now, and the first PMOS P1 of BP connections is just closed
It is disconnected, and the second PMOS P2 of BN connections is turned on.So, the drain voltage of conducting meeting NMOS tube N1 of lifting first of P2,
Allow the 4th NMOS tube N4, the 5th NMOS tube N5 not to turn on, also state is off with regard to N4, N5.The shut-off of P1 is not interfered with
The drain voltage of the sub- N2 of NMOS tube.Now, if AP is ' 0 ', then N6 shut-offs are flow through on R1 without electric current, and natural OUTP points are just
For ' 1 '；And AP is ' 0 ', then mean that AN is ' 1 ', this when, R2 had electric current to pass through, then the voltage of OUTN is not VDD, so
For ' 0 '.So as to obtain result, when it is ' 0 ' that BP is ' 1 ', AP, cause OUTP ' 1 ', realize the function of XOR.
When BP is ' 1 ', then BN is ' 0 ' naturally；Now the 6th NMOS tube N6 is turned on if AP is ' 1 ', this when
R1 has electric current to pass through, and then the voltage of OUTP is not VDD, is ' 0 '.
Other situations can be drawn by similar reasoning, therefore obtain this conclusion：When AP is identical with BP, OUTP is output as
‘0’；As AP and BP different, OUTP is output as ' 1 '；When AN is identical with BN, OUTN is output as ' 0 '；As AN and BN different,
OUTN is output as ' 1 '.
As shown in figure 3, the circuit structure of conventional source coupling XOR includes：The differential pair of two pairs of NMOS inputs, a pair folded
The differential pair of the PMOS inputs of layer, load and bias current sources.Conventional source coupling XOR circuit structure is compared, the present invention is adopted
The method of folding, reduces the conventional source coupling XOR circuit superposition number of plies in vertical direction, so as to reduce required supply voltage, makes
In the case of at low pressure, it can work more more preferable than conventional source coupling XOR circuit.
Claims (3)
1. a kind of low pressure source coupling XOR circuit structure, it is characterised in that：It includes the differential pair A and difference of two pairs of NMOS inputs
Divide the differential pair C to B, a pair of PMOS inputs, and respectively to differential pair A, differential pair B and differential pair C offer bias current
Bias current sources N1, bias current sources N2 and bias current sources P3；The reverse complement input interconnection of differential pair A and differential pair B,
The homophase complementary output end interconnection of differential pair A and differential pair B；All the way differential complement input signal AP, AN respectively with differential pair A and
The complementary input end connection of the complementary input end connection of differential pair B, another road differential complement input signal BP, BN and differential pair C,
The complementary output end of differential pair C is connected respectively with the bias current inputs of differential pair A and differential pair B.
2. a kind of low pressure source coupling XOR circuit structure according to claim 1, it is characterised in that：Described biased electrical
Stream source N1 and bias current sources N2 are mainly made up of NMOS tube.
3. a kind of low pressure source coupling XOR circuit structure according to claim 1, it is characterised in that：Described biased electrical
Stream source P3 is mainly made up of PMOS.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410701629.9A CN105700604B (en) | 2014-11-28 | 2014-11-28 | A low voltage source coupled exclusive OR logic circuit structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410701629.9A CN105700604B (en) | 2014-11-28 | 2014-11-28 | A low voltage source coupled exclusive OR logic circuit structure |
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| CN105700604A CN105700604A (en) | 2016-06-22 |
| CN105700604B true CN105700604B (en) | 2017-05-10 |
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Citations (9)
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| US5334888A (en) * | 1993-04-19 | 1994-08-02 | Intel Corporation | Fast exclusive-or and exclusive-nor gates |
| CN1856935A (en) * | 2003-09-22 | 2006-11-01 | 皇家飞利浦电子股份有限公司 | Circuit for providing a logic gate function and a latch function |
| CN101262213A (en) * | 2007-03-07 | 2008-09-10 | 恩益禧电子股份有限公司 | Input signal detecting circuit |
| CN101404500A (en) * | 2007-11-19 | 2009-04-08 | 杨曙辉 | Analog probability NOR gate circuit designed by CMOS transistor |
| CN101841318A (en) * | 2009-01-16 | 2010-09-22 | 特克特朗尼克公司 | Multifunction word recognizer element |
| CN201854266U (en) * | 2010-10-15 | 2011-06-01 | 北京工业大学 | Domino exclusive-or gate of PN mixed pull-down network used for VLSI (Very Large Scale Integrated Circuits) with low power consumption |
| CN102857217A (en) * | 2012-09-11 | 2013-01-02 | 宁波大学 | Low-power-consumption xor/xnor gate circuit |
| CN103297036A (en) * | 2013-06-26 | 2013-09-11 | 北京大学 | Low-power-consumption current mode logic circuit |
| CN204256578U (en) * | 2014-11-28 | 2015-04-08 | 成都振芯科技股份有限公司 | A kind of low pressure source coupling XOR circuit structure |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20060092408A (en) * | 2005-02-17 | 2006-08-23 | 삼성전자주식회사 | Circuits and methods for high performance exclusive or and exclusive nor |
| KR20130113085A (en) * | 2012-04-05 | 2013-10-15 | 에스케이하이닉스 주식회사 | Exclusive or circuit |
-
2014
- 2014-11-28 CN CN201410701629.9A patent/CN105700604B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5334888A (en) * | 1993-04-19 | 1994-08-02 | Intel Corporation | Fast exclusive-or and exclusive-nor gates |
| CN1856935A (en) * | 2003-09-22 | 2006-11-01 | 皇家飞利浦电子股份有限公司 | Circuit for providing a logic gate function and a latch function |
| CN101262213A (en) * | 2007-03-07 | 2008-09-10 | 恩益禧电子股份有限公司 | Input signal detecting circuit |
| CN101404500A (en) * | 2007-11-19 | 2009-04-08 | 杨曙辉 | Analog probability NOR gate circuit designed by CMOS transistor |
| CN101841318A (en) * | 2009-01-16 | 2010-09-22 | 特克特朗尼克公司 | Multifunction word recognizer element |
| CN201854266U (en) * | 2010-10-15 | 2011-06-01 | 北京工业大学 | Domino exclusive-or gate of PN mixed pull-down network used for VLSI (Very Large Scale Integrated Circuits) with low power consumption |
| CN102857217A (en) * | 2012-09-11 | 2013-01-02 | 宁波大学 | Low-power-consumption xor/xnor gate circuit |
| CN103297036A (en) * | 2013-06-26 | 2013-09-11 | 北京大学 | Low-power-consumption current mode logic circuit |
| CN204256578U (en) * | 2014-11-28 | 2015-04-08 | 成都振芯科技股份有限公司 | A kind of low pressure source coupling XOR circuit structure |
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| CN105700604A (en) | 2016-06-22 |
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