CN105655343A - Flash memory and manufacturing method thereof - Google Patents
Flash memory and manufacturing method thereof Download PDFInfo
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- CN105655343A CN105655343A CN201610119566.5A CN201610119566A CN105655343A CN 105655343 A CN105655343 A CN 105655343A CN 201610119566 A CN201610119566 A CN 201610119566A CN 105655343 A CN105655343 A CN 105655343A
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- polysilicon layer
- grid
- silicon substrate
- layer
- flash memories
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- 230000015654 memory Effects 0.000 title claims abstract description 56
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 239000010410 layer Substances 0.000 claims abstract description 145
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 91
- 150000004767 nitrides Chemical class 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 41
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 40
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 40
- 239000010703 silicon Substances 0.000 claims abstract description 40
- 239000011229 interlayer Substances 0.000 claims abstract description 30
- 229920005591 polysilicon Polymers 0.000 claims description 88
- 238000000034 method Methods 0.000 claims description 34
- 238000005516 engineering process Methods 0.000 claims description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
Abstract
The embodiment of the invention discloses a flash memory and a manufacturing method thereof. The manufacturing method of the flash memory includes the steps that at least one grid electrode is formed on a silicon substrate, and the outer side of each grid electrode is wrapped with a nitride layer; first polycrystalline silicon layers are formed in a source electrode region and a drain electrode region on the two sides of each grid electrode on the silicon substrate; an interlayer dielectric layer is formed on the first polycrystalline silicon layers and the nitride layers; the interlayer dielectric layer is etched to form leading-out holes above the first polycrystalline silicon layers. By means of the manufacturing method of the flash memory, the problem that short-circuiting between leading-out holes and grid electrodes is likely to occur can be solved under the condition that the distance between the leading-out holes and the memory cell grid electrodes is made as small as possible.
Description
Technical field
The present embodiments relate to semiconductor fabrication techniques, particularly relate to a kind of flash memories and preparation method thereof.
Background technology
Flash memories has and not easily runs off and the characteristic of repeatable erasing read-write, additionally has that transmission speed is fast and the characteristic of low power consumption so that flash memories application in portable product, information, communication and consumption electronic products is widely.
At present, in flash memories processing technology, especially or in non-flash memorizer processing technology, each memory element includes the fairlead of source and drain end. Fairlead is more little to the distance of memory element grid, and the area shared by single memory element is more little, the flash memories that can be formed on the silicon substrate of same size can memory space more big. In order to realize increasing unit sizes flash memories can the purpose of memory space, in concrete manufacturing process, generally adopt self aligned hole technology to form the fairlead of source and drain end, particularly as follows: first it, form grid on a silicon substrate; Secondly, square one-tenth nitride and form nitride side wall around grid on the gate, described nitride and nitride side wall are connected in one and are wrapped on described grid; Again, nitride layer and underlay substrate form interlayer dielectric layer; Finally, utilize dry carving technology, the etching selection ratio according to the interlayer dielectric layer set and nitride, the interlayer dielectric layer between adjacent two grids is etched, thus forming fairlead.
Utilize existing method in making flash memories process, even if the etching selection ratio of interlayer dielectric layer and nitride is determined errorless, owing to the nitride above grid and nitride side wall junction about are weaker, in dry etching process, easily cause fairlead and gate short, and then cause storage-unit-failure.
Summary of the invention
The present invention provides a kind of flash memories and preparation method thereof, to realize when the distance of fairlead to memory element grid is tried one's best little, and the problem solving fairlead and grid easily short circuit.
First aspect, embodiments provides a kind of flash memories manufacture method, including:
Form at least one grid on a silicon substrate, and be enclosed with nitride layer outside every described grid;
On described silicon substrate, the source region of every described grid both sides and drain region are respectively formed the first polysilicon layer;
Described first polysilicon layer and described nitride layer are formed interlayer dielectric layer;
Described interlayer dielectric layer is etched, is formed over fairlead at described first polysilicon layer.
Further, form at least one grid on a silicon substrate, and be enclosed with nitride layer outside every described grid and include:
Form at least one grid on a silicon substrate;
Every described, grid is formed over nitride;
The nitride of the top of formation nitride side wall around grid every described, described nitride side wall and described grid is connected in one and forms the nitride layer being wrapped in outside every described grid.
Further, on described silicon substrate, the source region of every described grid both sides and drain region are respectively formed the first polysilicon layer and include:
Forming polysilicon layer on described silicon substrate, described polysilicon layer covers the region that whole silicon substrate is corresponding;
The described polysilicon layer formed is etched, retains each source region of every described grid both sides or the polysilicon layer of drain region, to form described first polysilicon layer.
Further, forming polysilicon layer on described silicon substrate, described polysilicon layer is adulterated after covering the region that whole silicon substrate is corresponding by described polysilicon layer including the method utilizing diffusing, doping or ion implantation doping.
Further, described polysilicon layer is p-shaped doping or the doping of N shape.
Further, the described polysilicon layer formed is etched, retains each source region of every described grid both sides or the polysilicon layer of drain region, include forming described first polysilicon layer;
The described polysilicon layer formed is etched, only retain each source region of every described grid both sides or the polysilicon layer of drain region, or retain each source region of every described grid both sides or the polysilicon layer of drain region and connect the polysilicon layer of adjacent two source electrodes, to form described first polysilicon layer.
Further, described interlayer dielectric layer is etched, is formed over fairlead at described first polysilicon layer and includes:
Utilize dry carving technology, according to the etching selection ratio set, described interlayer dielectric layer is etched, is formed over fairlead at described first polysilicon layer.
Further, described interlayer dielectric layer is etched, includes after described first polysilicon layer is formed over fairlead:
The fairlead of described source region is formed source electrode, the fairlead of described drain region is formed drain electrode.
Second aspect, the embodiment of the present invention additionally provides a kind of flash memories, and this flash memories includes:
Silicon substrate;
Form the grid on described silicon substrate, and be enclosed with nitride layer outside every described grid
Form the first polysilicon layer of every described source region, grid both sides or drain region on described silicon substrate;
Form the interlayer dielectric layer on described first polysilicon layer and described nitride layer;
And penetrate described interlayer dielectric layer and the fairlead being connected with described first polysilicon layer.
Further, this flash memories also includes forming the source electrode on the fairlead of described source region and the drain electrode on the fairlead of drain region.
The embodiment of the present invention by forming the first polysilicon layer on nitride layer, first polysilicon layer is formed interlayer dielectric layer, and described interlayer dielectric layer is etched, it is formed over fairlead at described first polysilicon layer, solve and utilize existing manufacture method easily to make fairlead and gate short in dry etching process in the process making flash memories, and then the problem causing storage-unit-failure, it is possible to improve the yield of flash memories.
Accompanying drawing explanation
Fig. 1 is the flow chart of the flash memories manufacture method that the embodiment of the present invention one provides;
In the process that Fig. 2 a to Fig. 2 c is carried out in Fig. 1 S110, the structural representation of each state of flash memories;
Planning chart when Fig. 3 is to make flash memories;
In the process that Fig. 4 a and Fig. 4 b is carried out in Fig. 1 S120, the structural representation of each state of flash memories;
Fig. 5 a and Fig. 5 b has been in Fig. 1 after S120, two kinds of structural representations of flash memories;
Fig. 6 has been in Fig. 1 after S130, the structural representation of flash memories;
Fig. 7 has been in Fig. 1 after S140, the structural representation of flash memories;
Fig. 8 is the structural representation of a kind of flash memories that the embodiment of the present invention two provides.
Detailed description of the invention
Below in conjunction with drawings and Examples, the present invention is described in further detail. It is understood that specific embodiment described herein is used only for explaining the present invention, but not limitation of the invention. It also should be noted that, for the ease of describing, accompanying drawing illustrate only part related to the present invention but not entire infrastructure.
Embodiment one
The flow chart of the manufacture method of a kind of flash memories that Fig. 1 provides for the embodiment of the present invention one. The manufacture method of this flash memories specifically includes following steps:
S110, form at least one grid on a silicon substrate, and be enclosed with nitride layer outside every described grid;
The concrete methods of realizing of this step is: first, such as Fig. 2 a, forms at least one grid 2 (in fig. 2 a two grids 2 of exemplary formation) on silicon substrate 1; Secondly, such as Fig. 2 b, it is formed over nitride 31 at every grid 2; Finally, such as Fig. 2 c, formation nitride side wall 32 around every grid 2, the nitride 31 of the top of nitride side wall 32 and grid 2 is connected in one and forms the nitride layer 3 being wrapped in outside every grid 2.
Need explanation, in this step, in order to relax the high potential difference near source-drain electrode, extend the life-span of flash memories, optionally, after silicon substrate 1 is formed at least one grid 2, first complete lightly-doped source leakage injection technology, it is enclosed with after nitride layer 3 outside every grid 3 again, completes heavy doping source and drain injection technology.
S120, on described silicon substrate, the source region of every described grid both sides and drain region are respectively formed the first polysilicon layer;
Source region refers to and planned in advance on a silicon substrate for making the region of source electrode before making. Similarly, drain region refers to and planned in advance on a silicon substrate for making the region of drain electrode before making. Exemplarily, as it is shown on figure 3, this source region 21 and drain region 22 are positioned at the both sides of grid 2, and being positioned on bit line 11, same grid 2 the same side can arrange territory, plurality of source regions 21 (or drain region 22).
The concrete methods of realizing of this step is: first, and such as Fig. 4 a, formation polysilicon layer 41 on silicon substrate 1, polysilicon layer 41 covers the region of whole silicon substrate 1 correspondence; Secondly, such as Fig. 4 b, the polysilicon layer 41 formed is etched, retains each source region of every grid 2 both sides or the polysilicon layer 41 of drain region, to form the first polysilicon layer 4.
It should be noted that after forming this polysilicon layer 41, and when this polysilicon layer 41 not being etched, it is possible to this polysilicon layer 41 is adulterated, it is also possible to this polysilicon layer 41 is not adulterated. If this polysilicon layer 41 being adulterated, it is possible to use polysilicon layer 41 is adulterated by the method for diffusing, doping or ion implantation doping, and polysilicon layer 41 is p-shaped doping or the doping of N shape.When polysilicon layer 41 is etched, it is possible to adopt wet-etching technique that polysilicon layer 41 is etched.
It addition, when the polysilicon layer 41 formed is etched, it is possible to the demand according to product, select only to retain each source region of every grid 2 both sides or the polysilicon layer 41 of drain region, to form the first polysilicon layer 4 (such as Fig. 5 a); Can also select retain each source region of every grid 2 both sides or the polysilicon layer 41 of drain region and connect the polysilicon layer 41 of adjacent two source electrodes, to form the first polysilicon layer 4 (such as Fig. 5 b).
S130, on described first polysilicon layer and described nitride layer formed interlayer dielectric layer.
It should be noted that such as Fig. 6, the interlayer dielectric layer 5 formed covers whole silicon substrate 1.
S140, described interlayer dielectric layer is etched, is formed over fairlead 6 at described first polysilicon layer.
Specifically, utilize dry carving technology, according to the etching selection ratio set, interlayer dielectric layer 5 is etched, is formed over fairlead 6 (such as Fig. 7) at the first polysilicon layer 4.
It addition, after S140, be additionally included on the fairlead of described source region and form source electrode, the fairlead of described drain region forms drain electrode.
The embodiment of the present invention by forming the first polysilicon layer on nitride layer, first polysilicon layer is formed interlayer dielectric layer, and described interlayer dielectric layer is etched, it is formed over fairlead at described first polysilicon layer, solve and utilize existing manufacture method easily to make fairlead and gate short in dry etching process in the process making flash memories, and then the problem causing storage-unit-failure, it is possible to improve the yield of flash memories.
Embodiment two
The present invention also provides for a kind of flash memories. The structural representation of the flash memories that Fig. 8 provides for the embodiment of the present invention two. This flash memories, including: silicon substrate 1; Form the grid 2 on described silicon substrate, and be enclosed with nitride layer 3 outside every described grid 2; Form first polysilicon layer 4 of every described source region, grid 2 both sides or drain region on described silicon substrate 1; Form the interlayer dielectric layer 5 on described first polysilicon layer 4 and described nitride layer 3; And penetrate described interlayer dielectric layer and the fairlead 6 being connected with described first polysilicon layer.
On this basis, this flash memories also includes forming the source electrode on the fairlead of described source region and the drain electrode on the fairlead of drain region.
The flash memories that the embodiment of the present invention provides, by setting up the first polysilicon layer between nitride layer and fairlead, solve and utilize existing manufacture method easily to make fairlead and gate short in dry etching process in the process making flash memories, and then the problem causing storage-unit-failure, it is possible to improve the yield of flash memories.
Note, above are only presently preferred embodiments of the present invention and institute's application technology principle. It will be appreciated by those skilled in the art that and the invention is not restricted to specific embodiment described here, various obvious change can be carried out for a person skilled in the art, readjust and substitute without departing from protection scope of the present invention. Therefore, although the present invention being described in further detail by above example, but the present invention is not limited only to above example, when without departing from present inventive concept, other Equivalent embodiments more can also be included, and the scope of the present invention is determined by appended right.
Claims (10)
1. a flash memories manufacture method, it is characterised in that including:
Form at least one grid on a silicon substrate, and be enclosed with nitride layer outside every described grid;
On described silicon substrate, the source region of every described grid both sides and drain region are respectively formed the first polysilicon layer;
Described first polysilicon layer and described nitride layer are formed interlayer dielectric layer;
Described interlayer dielectric layer is etched, is formed over fairlead at described first polysilicon layer.
2. according to the flash memories manufacture method described in claim 1, it is characterised in that form at least one grid on a silicon substrate, and it is enclosed with nitride layer outside every described grid and includes:
Form at least one grid on a silicon substrate;
Every described, grid is formed over nitride;
The nitride of the top of formation nitride side wall around grid every described, described nitride side wall and described grid is connected in one and forms the nitride layer being wrapped in outside every described grid.
3. according to the flash memories manufacture method described in claim 1, it is characterised in that on described silicon substrate, the source region of every described grid both sides and drain region are respectively formed the first polysilicon layer and include:
Forming polysilicon layer on described silicon substrate, described polysilicon layer covers the region that whole silicon substrate is corresponding;
The described polysilicon layer formed is etched, retains each source region of every described grid both sides or the polysilicon layer of drain region, to form described first polysilicon layer.
4. according to the flash memories manufacture method described in claim 3, it is characterised in that form polysilicon layer on described silicon substrate, after described polysilicon layer covers the region that whole silicon substrate is corresponding, including
Described polysilicon layer is adulterated by the method utilizing diffusing, doping or ion implantation doping.
5. according to the flash memories manufacture method described in claim 4, it is characterised in that described polysilicon layer is p-shaped doping or the doping of N shape.
6. according to the flash memories manufacture method described in claim 3, it is characterized in that, the described polysilicon layer formed is etched, retains each source region of every described grid both sides or the polysilicon layer of drain region, include forming described first polysilicon layer;
The described polysilicon layer formed is etched, only retain each source region of every described grid both sides or the polysilicon layer of drain region, or retain each source region of every described grid both sides or the polysilicon layer of drain region and connect the polysilicon layer of adjacent two source electrodes, to form described first polysilicon layer.
7. according to the flash memories manufacture method described in claim 1, it is characterised in that described interlayer dielectric layer is etched, is formed over fairlead at described first polysilicon layer and includes:
Utilize dry carving technology, according to the etching selection ratio set, described interlayer dielectric layer is etched, is formed over fairlead at described first polysilicon layer.
8. according to the flash memories manufacture method described in claim 1, it is characterised in that described interlayer dielectric layer is etched, includes after described first polysilicon layer is formed over fairlead:
The fairlead of described source region is formed source electrode, the fairlead of described drain region is formed drain electrode.
9. the flash memories that the method described in claim 1-8 makes, it is characterised in that including:
Silicon substrate;
Form the grid on described silicon substrate, and be enclosed with nitride layer outside every described grid
Form the first polysilicon layer of every described source region, grid both sides or drain region on described silicon substrate;
Form the interlayer dielectric layer on described first polysilicon layer and described nitride layer;
And penetrate described interlayer dielectric layer and the fairlead being connected with described first polysilicon layer.
10. according to the flash memories described in claim 9, it is characterised in that also include forming the source electrode on the fairlead of described source region and the drain electrode on the fairlead of drain region.
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| CN201610119566.5A CN105655343A (en) | 2016-03-03 | 2016-03-03 | Flash memory and manufacturing method thereof |
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| CN201610119566.5A CN105655343A (en) | 2016-03-03 | 2016-03-03 | Flash memory and manufacturing method thereof |
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2016
- 2016-03-03 CN CN201610119566.5A patent/CN105655343A/en active Pending
Patent Citations (9)
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| US20020060332A1 (en) * | 2000-11-20 | 2002-05-23 | Hitachi, Ltd. | Semiconductor integrated circuit device and manufacturing method thereof |
| US20040209427A1 (en) * | 2003-04-15 | 2004-10-21 | Nanya Technology Corporation | Method of filling bit line contact via |
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Application publication date: 20160608 |