TWI578538B - Semiconductor structure - Google Patents

Description

Semiconductor structure

The present invention relates to a semiconductor structure, and more particularly to an improved dynamic random access memory having a three-dimensional junction (3D junction) node contact structure, which can effectively reduce the contact resistance of the storage node.

With the continuous advancement of process technology, the critical dimensions of components of semiconductor memory components, such as dynamic random access memory (DRAM), are becoming smaller and smaller, which enables more wafers to be fabricated per unit area. Memory unit.

However, since the contact area on the active area is also shrinking, the current challenge in the industry is that the contact resistance of the storage node cannot be effectively reduced, especially when defining node contact holes. When there is a rnisalignment on the lithography process.

It can be seen that there is still a need in the art for an improved semiconductor structure to address the above-described deficiencies and shortcomings of the prior art.

In order to achieve the above object, the present invention further provides a semiconductor structure including a semiconductor substrate having a main surface; at least one active region disposed on the main surface of the semiconductor substrate; and a shallow trench isolation region separating the active region, wherein The upper surface of the shallow trench isolation region is lower than the predetermined surface of the main surface to expose a sidewall of the active region; a vertical junction doping region is disposed on the sidewall of the exposed active region; a source/drain region disposed on the main surface of the semiconductor substrate, wherein the vertical junction doping region and the source/drain region are coupled together to form a Three-dimensional junction.

According to an embodiment of the invention, the three-dimensional interface mask has an inverted L-shaped junction profile.

According to an embodiment of the invention, the vertical junction doping region and the source/drain region have the same conductivity type.

According to an embodiment of the invention, the vertical junction doping region and the source/drain region are both N-type.

According to an embodiment of the invention, the semiconductor structure of the present invention further includes a contact plug while contacting the vertical junction doping region and the source/drain region.

In accordance with an embodiment of the invention, the inventive semiconductor structure further includes at least one buried word line disposed within the semiconductor substrate below the major surface and through the active region.

The above described objects, features and advantages of the present invention will become more apparent from the description of the appended claims. However, the following preferred embodiments and drawings are for illustrative purposes only and are not intended to limit the invention.

10‧‧‧Semiconductor substrate

10a‧‧‧Main surface

10b‧‧‧ sidewall

12‧‧‧Oxygen lining

14‧‧‧Nitride layer

20‧‧‧Insulation trench

22‧‧‧Insulation materials

22a‧‧‧Upper surface

22b‧‧‧ upper surface

22c‧‧‧ upper surface

30‧‧‧ oblique angle ion implantation process

32‧‧‧Vertical junction doping

40‧‧‧ buried word line

402‧‧‧word line trench

404‧‧‧gate dielectric layer

406‧‧‧ conductor layer

408‧‧‧ dielectric layer

50‧‧‧Source/bungee area

52‧‧‧Source/bungee area

60‧‧‧Three-dimensional junction

70‧‧‧Dielectric layer

72‧‧‧ bit line

80‧‧‧ openings

88‧‧‧Contact plug

90‧‧‧ cover

H1‧‧‧depth

H2‧‧‧Predetermined depth

AA‧‧‧active area

STI‧‧‧Shallow trench insulation area

1 to 5 illustrate a semiconductor structure of the present invention and a method of fabricating the same.

In the following, the details of the embodiments of the present invention will be described with reference to the accompanying drawings, which form a part of the specification and the description of the specific examples in which the embodiments can be practiced. The following examples are set forth with sufficient detail to enable those of ordinary skill in the art to practice. Of course, other embodiments may be utilized in the present invention, or any structural, logical, or electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description is not to be considered as a limitation, and the embodiments included herein are defined by the scope of the accompanying claims.

For the manufacture of a transistor and an integrated circuit, as in the case of a planar process, the term "main surface" refers to the surface of a semiconductor layer having a plurality of transistors formed therein or in close proximity. As used herein, the term "vertical" means substantially at right angles to the major surface. In general, the major surface extends along one of the <100> planes of the single crystal germanium layer on the fabricated field effect transistor.

The semiconductor structure of the present invention and a method of fabricating the same will be described below by the cross-sections of Figs. 1 to 5. First, as shown in Fig. 1, a semiconductor substrate 10 having a main surface 10a is provided. An oxide liner 12 and a pad nitride 14 may be disposed on the main surface 10a of the semiconductor substrate 10. Next, a shallow trench isolation (STI) process is performed, including forming a photoresist pattern (not shown) on the tantalum nitride pad layer 14, followed by dry etching, and forming an insulating trench 20 on the semiconductor substrate 10 to define Active area (AA) and shallow trench insulation (STI) area. Then, the insulating material 22 is filled in the insulating trench 20, and planarized by a chemical mechanical polishing process so that the upper surface 22a of the insulating material 22 is flush with the surface of the tantalum nitride pad layer 14.

As shown in FIG. 2, after the above STI process is completed, an etching process, such as a wet etching process, is performed, but is not limited thereto. The etching process selectively etches a portion of the insulating material 22 such that the upper surface 22b of the insulating material 22 is lower than the major surface 10a of the semiconductor substrate 10 by a predetermined depth h1 and the sidewall 10b of the active region (AA) is exposed. According to an embodiment of the invention, the predetermined depth h1 may be between 50 angstroms and 500 angstroms. At this point, the active area (AA) in the memory array exhibits a bulge because the surface of the surrounding shallow trench isolation (STI) region has subsided.

As shown in FIG. 3, an oblique angle ion implantation process 30 is then performed to implant a dopant, such as an N-type dopant, into the sidewall 10b of the exposed active region (AA) to form a vertical junction doping. District 32. According to an embodiment of the present invention, the above N-type dopant may be arsenic or phosphorus, but is not limited thereto.

As shown in FIG. 4, after the active region (AA), the shallow trench isolation (STI) region, and the vertical junction doping region 32 are completed, the fabrication of the buried word line is performed, and a plurality of stripes are formed in the semiconductor substrate 10. The buried word line 40 passes through the active area (AA). For example, the method of forming the buried word line 40 may first form a plurality of word line trenches 402 in the semiconductor substrate 10 by a lithography and etching process, and form a gate dielectric layer 404 in the word line trenches 402. A conductor layer 406 is then formed at the bottom of the word line trench 402 as a gate, and finally the conductor layer 406 is covered with a dielectric layer 408 and the word line trenches 402 are filled. Dielectric layer 408 also fills the shallow trench isolation (STI) region.

After the fabrication of the buried word line is completed, a source/drain ion implantation process can be continued to form the source/drain region 50 and the source in the semiconductor substrate 10 on both sides of the word line trench 402. / drain region 52, wherein the source/drain region 52 and the vertical junction doping region 32 together form an inverted L-shaped three-dimensional junction (60). According to an embodiment of the invention, the source/drain region 52 and the vertical junction doping region 32 are of the same conductivity type, that is, both are N-type.

As shown in FIG. 4-1, at least one dielectric layer 70 and one bit line 72 are formed on the semiconductor substrate 10, wherein the bit line 72 is disposed in the dielectric layer 70 and is connected to the source/drain region. 50 electrical connections. An opening 80 is then formed in the dielectric layer 70 by lithography and etching processes to expose the source/drain regions 52 and portions of shallow trench isolation (STI) regions. When the opening 80 is formed, the shallow trench isolation (STI) region is again etched such that the upper surface 22c of the shallow trench isolation (STI) region is again lower than the main surface 10a of the semiconductor substrate 10 by a predetermined depth h2, thereby passing through the opening 80. A sidewall 10b of the active region (AA) and a vertical junction doping region 32 are exposed.

Finally, as shown in FIG. 5, a contact plug 88 of the storage node is formed in the opening 80. According to an embodiment of the invention, the method for forming the contact plug 88 may be preceded by filling a metal layer in the lower half of the opening 80, forming a cap layer 90 on the metal layer, and then opening the opening 80 by lithography and etching. The cover layer 90 and the underlying metal layer are cut and split into two, thus forming a contact plug 88. Since the bottom of the contact plug 88 is in contact with the inverted L-shaped three-dimensional junction 60 formed by the source/drain region 52 and the vertical junction doping region 32, the contact resistance of the storage node can be reduced.

The fabrication methods of Figs. 1 to 5 are merely illustrative, and the present invention is not limited to the embodiments described in the above drawings. For example, the step of exposing the sidewall 10b of the active region (AA) may be performed after the formation of the buried word line 40. In other words, in other embodiments, the buried word line 40 may be formed first, and then the three-dimensional interface 60 may be formed.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10‧‧‧Semiconductor substrate

20‧‧‧Insulation trench

22‧‧‧Insulation materials

22c‧‧‧ upper surface

40‧‧‧ buried word line

402‧‧‧word line trench

404‧‧‧gate dielectric layer

406‧‧‧ conductor layer

408‧‧‧ dielectric layer

50‧‧‧Source/bungee area

60‧‧‧Three-dimensional junction

70‧‧‧Dielectric layer

72‧‧‧ bit line

80‧‧‧ openings

88‧‧‧Contact plug

90‧‧‧ cover

H2‧‧‧Predetermined depth

AA‧‧‧active area

STI‧‧‧Shallow trench insulation area

Claims (6)

A semiconductor structure comprising: a semiconductor substrate having a major surface; at least one active region disposed on the major surface of the semiconductor substrate; a shallow trench isolation region separating the active region, wherein the shallow trench isolation region The surface is lower than the predetermined surface of the main surface to expose a sidewall of the active region; a vertical junction doped region is disposed on the sidewall of the exposed active region; and a source/drain region The main surface of the semiconductor substrate is disposed, wherein the vertical junction doping region and the source/drain region are coupled to each other to form a three-dimensional junction. The semiconductor structure of claim 1, wherein the three-dimensional contact mask has an inverted L-junction profile. The semiconductor structure of claim 1, wherein the vertical junction doping region and the source/drain region have the same conductivity type. The semiconductor structure of claim 1, wherein the vertical junction doping region and the source/drain region are both N-type. The semiconductor structure of claim 1, further comprising a contact plug while contacting the vertical junction doping region and the source/drain region. The semiconductor structure of claim 1, further comprising at least one buried word line disposed in the semiconductor substrate below the main surface and passing through the active region.