CN105826319B

CN105826319B - Semiconductor structure

Info

Publication number: CN105826319B
Application number: CN201510004989.8A
Authority: CN
Inventors: 李宗翰; 施能泰; 胡耀文
Original assignee: Micron Technology Inc
Current assignee: Micron Technology Inc
Priority date: 2014-11-28
Filing date: 2015-01-06
Publication date: 2020-04-21
Anticipated expiration: 2035-01-06
Also published as: TWI578538B; TW201620137A; CN105826319A

Abstract

The invention discloses a semiconductor structure, comprising a semiconductor substrate with a main surface; at least one active region disposed on the main surface of the semiconductor substrate; a shallow trench isolation for isolating the active region, wherein the upper surface of the shallow trench isolation is lower than the main surface by a predetermined depth and a sidewall of the active region is exposed; a vertical junction doped well formed on the exposed sidewall of the active region; and a source/drain region disposed on the main surface of the semiconductor substrate, wherein the vertical junction doped well is connected with the source/drain region to form a three-dimensional junction.

Description

Semiconductor structure

Technical Field

The present invention relates to a semiconductor structure, and more particularly, to an improved dram having a node contact structure with a three-dimensional (3D) junction, which can effectively reduce the contact resistance of a storage node.

Background

As process technology continues to advance, the critical dimensions of semiconductor memory devices, such as Dynamic Random Access Memory (DRAM) devices, are becoming smaller, which allows more memory cells to be fabricated per unit area of the chip.

However, since the contact area on the active area is also getting smaller and smaller, the storage node (storage node) contact resistance cannot be effectively reduced, especially when misalignment occurs in the photolithography process for defining the node contact (node contact).

Accordingly, there is a need in the art for an improved semiconductor structure that overcomes the above-mentioned deficiencies and drawbacks of the prior art.

Disclosure of Invention

To achieve the above objective, the present invention provides a semiconductor structure, which includes a semiconductor substrate having a main surface; at least one active region disposed on the main surface of the semiconductor substrate; a shallow trench isolation isolating the active region, wherein the upper surface of the shallow trench isolation is lower than the main surface by a predetermined depth, and a side wall of the active region is exposed; a vertical junction doped well disposed on the exposed sidewall of the active region; and a source/drain region disposed on the main surface of the semiconductor substrate, wherein the vertical junction doped well is connected with the source/drain region to form a three-dimensional junction.

According to an embodiment of the present invention, the three-dimensional solid junction has an inverted L-shaped junction profile.

According to an embodiment of the present invention, the vertical junction doped well and the source/drain region have the same conductivity type.

According to an embodiment of the present invention, the vertical junction doped well and the source/drain regions are both N-type.

According to an embodiment of the present invention, the semiconductor structure further comprises a contact plug simultaneously contacting the vertical junction doped well and the source/drain region.

According to an embodiment of the present invention, the semiconductor structure further includes at least one buried word line disposed in the semiconductor substrate, below the main surface, and passing through the active region.

In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below. However, the following preferred embodiments and the accompanying drawings are only for reference and illustration purposes and are not intended to limit the present invention.

Drawings

FIG. 1 illustrates a semiconductor structure and method of fabricating the same according to the present invention.

Fig. 2 depicts a semiconductor structure and method of making the same of the present invention.

Fig. 3 depicts a semiconductor structure and method of making the same of the present invention.

Fig. 4 depicts a semiconductor structure and method of making the same of the present invention.

Fig. 5 depicts a semiconductor structure and method of making the same of the present invention.

Wherein the reference numerals are as follows:

10 semiconductor substrate

10a main surface

10b side wall

12 silicon oxygen liner

14 silicon nitride pad layer

20 insulated trench

22 insulating material

22a upper surface

22b upper surface

22c upper surface

30-oblique-angle ion implantation process

32 vertical junction doped well

40 buried word line

402 word line trench

404 Gate dielectric layer

406 conductive layer

408 dielectric layer

50 source/drain regions

52 source/drain regions

60 three-dimensional stereo junction surface

70 dielectric layer

72 bit line

80 opening

88 contact plug

90 cover layer

h1 predetermined depth

h2 predetermined depth

AA active region

STI shallow trench isolation

Detailed Description

Reference will now be made in detail to the present embodiments of the invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. The following examples are set forth in sufficient detail to enable those skilled in the art to practice the invention. Of course, other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the embodiments described herein. The following detailed description is, therefore, not to be taken in a limiting sense, and the embodiments included therein are defined by the appended claims.

For the fabrication of transistors and integrated circuits, the term "major surfaces" as in the case of a planar process refers to those surfaces of a semiconductor layer in which or near which a plurality of transistors are formed. As used herein, the term "perpendicular" means substantially at right angles to the major surface. Typically, the main surface extends along a <100> plane of the monocrystalline silicon layer on the fabricated field effect transistor.

The semiconductor structure and the method of fabricating the same of the present invention will be described below by means of cross-sectional views of fig. 1 to 5. First, as shown in fig. 1, a semiconductor substrate 10 having a main surface 10a is provided. A silicon oxide liner (oxide liner)12 and a silicon nitride pad (pad nitride)14 may be disposed on the main surface 10a of the semiconductor substrate 10. Next, a Shallow Trench Isolation (STI) process is performed, including forming a photoresist pattern (not shown) on the silicon nitride pad 14, followed by dry etching to form an isolation trench 20 in the semiconductor substrate 10 to define an Active Area (AA) and a Shallow Trench Isolation (STI). Then, the insulating trench 20 is filled with an insulating material 22, and planarization is performed by a chemical mechanical polishing process, so that the upper surface 22a of the insulating material 22 is flush with the surface of the silicon nitride pad layer 14.

As shown in fig. 2, after the STI process is completed, an etching process, such as a wet etching process, is performed. The etching process selectively removes a portion of the insulating material 22 such that the upper surface 22b of the insulating material 22 is lower than the main surface 10a of the semiconductor substrate 10 by a predetermined depth h1 and the sidewalls 10b of the Active Area (AA) are exposed. According to an embodiment of the present invention, the predetermined depth h1 may be between 50 a and 500 a. At this time, the Active Area (AA) in the memory array exhibits a bump because the surface of the surrounding Shallow Trench Isolation (STI) has sunk.

As shown in fig. 3, an angled ion implantation process 30 is performed to implant dopants, such as N-type dopants, into the exposed sidewalls 10b of the Active Area (AA) to form a vertical junction dopant well 32. According to the embodiment of the present invention, the N-type dopant may be arsenic or phosphorus, but is not limited thereto.

After completing the Active Area (AA), Shallow Trench Isolation (STI) and vertical junction dopant well 32, a plurality of buried word lines 40 are formed in the semiconductor substrate 10 through the Active Area (AA), as shown in fig. 4. For example, the method of forming the buried word line 40 may include forming a plurality of word line trenches 402 in the semiconductor substrate 10 by photolithography and etching processes, forming a gate dielectric layer 404 in the word line trenches 402, forming a conductive layer 406 at the bottom of the word line trenches 402 as a gate, and covering the conductive layer 406 with a dielectric layer 408 and filling the word line trenches 402. The dielectric layer 408 also fills the Shallow Trench Isolation (STI).

After the fabrication of the embedded word line is completed, a source/drain ion implantation process may be performed to form a source/drain region 50 and a source/drain region 52 in the semiconductor substrate 10 on both sides of the word line trench 402, wherein the source/drain region 52 and the vertical junction doped well 32 together form an inverted L-shaped three-dimensional junction (3D junction) 60. According to the present embodiment, the source/drain regions 52 and the vertical junction dopant well 32 are of the same conductivity type, i.e., both N-type.

As shown in fig. 5, at least one dielectric layer 70 and a bit line 72 are formed on the semiconductor substrate 10, wherein the bit line 72 is disposed in the dielectric layer 70 and electrically connected to the source/drain regions 50. An opening 80 is then formed in the dielectric layer 70 by photolithography and etching processes, exposing the source/drain regions 52 and portions of the Shallow Trench Isolation (STI). The opening 80 is formed by etching the Shallow Trench Isolation (STI) again such that the upper surface 22c of the Shallow Trench Isolation (STI) is again lower than the main surface 10a of the semiconductor substrate 10 by a predetermined depth h2, thereby exposing the sidewall 10b of the Active Area (AA) and the vertical junction doping well 32 through the opening 80. Finally, a contact plug 88 for a storage node is formed in the opening 80.

According to the embodiment of the invention, the method for forming the contact plug 88 can be performed by filling a metal layer in the lower half of the opening 80, forming a cap layer 90 on the metal layer, and then cutting the cap layer 90 in the opening 80 and the metal layer below into two parts by photolithography and etching, thereby forming the contact plug 88. Since the bottom of the contact plug 88 contacts the inverted-L-shaped three-dimensional junction (3D junction)60 formed by the source/drain region 52 and the vertical junction doping well 32, the contact resistance of the storage node can be reduced.

The manufacturing methods of fig. 1 to 5 are merely exemplary, and the present invention is not limited to the embodiments described in the above drawings. For example, the step of exposing the sidewalls 10b of the Active Area (AA) may be performed after the formation of the buried word line 40. In other words, in other embodiments, the buried word line 40 may be formed first, and then the three-dimensional body junction 60 may be formed.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor structure, comprising:

a semiconductor substrate having a main surface;

at least one active region disposed on the main surface of the semiconductor substrate;

the opposite shallow trench isolation regions isolate the at least one active region, wherein the upper surfaces of the opposite shallow trench isolation regions are lower than the main surface by a preset depth and the side walls of the at least one active region are exposed;

a vertical junction doping well disposed on the exposed sidewall along the at least one active region;

at least one buried word line disposed in the word line trench below the main surface of the semiconductor substrate and passing through the at least one active region;

source/drain regions extending along the major surface of the semiconductor substrate from both sides of the word line trench to respective exposed sidewalls of the opposing shallow trench isolation regions, wherein each vertical junction doping well is positioned along the exposed sidewalls of the at least one active region and engages with each other to form an inverted-L-shaped three-dimensional solid junction between one side of the word line trench and the adjacent shallow trench isolation region, wherein the vertical junction doping wells and the source/drain regions have the same conductivity type; and

a contact plug of a storage node in direct contact with the respective vertical junction doping well and the respective source/drain region, the contact plug extending over an upper surface of the major surface of the semiconductor substrate adjacent the respective source/drain region and extending within one of the opposing shallow trench isolation regions along exposed sidewalls of the at least one active region adjacent the vertical junction doping well, wherein opposing portions of the contact plug are laterally spaced apart from each other within each of the shallow trench isolation regions.

2. The semiconductor structure of claim 1, wherein the vertical junction doped well and the source/drain regions each comprise an N-type dopant.