CN105652176A - Method and device for testing number of guard rings - Google Patents
Method and device for testing number of guard rings Download PDFInfo
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- CN105652176A CN105652176A CN201610130581.XA CN201610130581A CN105652176A CN 105652176 A CN105652176 A CN 105652176A CN 201610130581 A CN201610130581 A CN 201610130581A CN 105652176 A CN105652176 A CN 105652176A
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- active area
- type active
- protection ring
- region
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2607—Circuits therefor
- G01R31/2608—Circuits therefor for testing bipolar transistors
Abstract
Provided are a method and device for testing the number of guard rings. The guard rings are arranged between a PMOS and an NMOS, and each guard ring comprises X P-type active regions and Y N-type active regions, wherein the X and the Y are both natural numbers. The method comprises the steps that the range of an intermediate region located between the PMOS and the NMOS is determined; virtual layers corresponding to regions located between the P-type active regions and the N-type active regions are obtained within the range of the intermediate region; the number of the virtual layers is calculated and serves as the number of the guard rings. By means of the method and device for testing the number of the guard rings, the complexity and testing time for testing the number of the guard rings can be reduced.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to method of testing and the device of a kind of protection ring quantity.
Background technology
Latch-up (latch-up) is the one of the main reasons of semiconductor device failure, latch-up be by the active area of NMOS, substrate P, N trap, PMOS the n-p-n-p structure that constitutes of active area produce, when wherein any one audion positively biased in n-p-n-p structure, positive feedback will be constituted and form breech lock. Under latched condition, device forms short circuit between power supply and ground, causes the damage of big electric current, electricity overload (ElectricalOverStress, EOS) and electronic devices and components. In order to avoid latch-up; it is typically between PMOS and NMOS and places protection ring (Guardring); specifically by P type active area (P+) in protection ring around NMOS ground connection, N-type active area (N+) around PMOS and is connect high level.
Test Qualify Phase before device manufactures, consistent with the quantity of design phase determined protection ring in order to determine the device that target manufacture completes, it is necessary to detect the quantity of protection ring in described semiconductor device.
At present; can make to detect with the following method the quantity of protection ring: first determine the zone line between PMOS and NMOS; and then from described zone line, detect the region of non-P type active area and non-N-type active area; and obtain the virtual level corresponding with the region of described non-P type active area and non-N-type active area; then judge that described virtual level is whether between described P type active area and N-type active area; finally calculate the quantity of described virtual level between described P type active area and N-type active area, as the quantity of described protection ring.
But, use above-mentioned method of testing to determine the quantity of protection ring, computation complexity is high, and operation time is long.
Summary of the invention
The problem that this invention address that is how to reduce complexity and the operation time of the test of protection ring quantity.
For solving the problems referred to above, the present invention provides the method for testing of a kind of protection ring quantity, described protection ring is placed between PMOS and NMOS, described protection ring includes X P type active area and Y N-type active area, X, Y are natural number, and described method comprises determining that the zone line scope between described PMOS and described NMOS; Within the scope of described zone line, obtain the virtual level corresponding with the region between described P type active area and described N-type active area;Calculate the quantity of described virtual level, as the quantity of described protection ring.
Alternatively, described within the scope of described zone line, obtain the virtual level corresponding with the region between described P type active area and described N-type active area, including: obtain the region between described P type active area and described N-type active area; Generate the virtual level corresponding with the region between described P type active area and described N-type active area.
Alternatively, the described zone line scope determined between described PMOS and described NMOS, comprise determining that the device channel region of described PMOS and four apex coordinates of correspondence thereof; Determine the device channel region of described NMOS and four apex coordinates of correspondence thereof; By the device channel region of the device channel region of described PMOS and described NMOS just to and four determined regions of apex coordinate on both sides that distance is the shortest, as the zone line scope between described PMOS and described NMOS.
Alternatively, the device channel region of the device channel region of described PMOS and described NMOS just to and distance��50 micron on both sides that distance is the shortest.
Alternatively, described acquisition region between described P type active area and described N-type active area, comprise determining that described P type active area; Determine described N-type active area; Within the scope of described zone line, by the rectangular area between described P type active area and the described N-type active area of arbitrary neighborhood, as described region between described P type active area and described N-type active area.
Alternatively, spacing��50 micron of described adjacent P type active area and described N-type active area.
Alternatively, continuous n same kind of active area is calculated as a described protection ring, n > 1.
One embodiment of the invention provides the test device of a kind of protection ring quantity, described protection ring is placed between PMOS and NMOS, described protection ring includes X P type active area and Y N-type active area, X, Y are natural number, described device includes: zone line determines unit, is adapted to determine that the zone line scope between described PMOS and described NMOS; Virtual level acquiring unit, is suitable within the scope of described zone line, obtains the virtual level corresponding with the region between described P type active area and described N-type active area; Computing unit, is suitable to calculate the quantity of described virtual level, as the quantity of described protection ring.
Alternatively, described virtual level acquiring unit, including: region obtains subelement, is suitable to obtain the region between described P type active area and described N-type active area; Virtual level generates subelement, is suitable to generate the virtual level corresponding with the region between described P type active area and described N-type active area.
Alternatively, described zone line determines unit, including: subelement is determined in first area, is adapted to determine that the device channel region of described PMOS and four apex coordinates of correspondence thereof; Second area determines subelement, is adapted to determine that the device channel region of described NMOS and four apex coordinates of correspondence thereof; Zone line determines subelement, be suitable to by the device channel region of the device channel region of described PMOS and described NMOS just to and four determined regions of apex coordinate on both sides that distance is the shortest, as the zone line scope between described PMOS and described NMOS.
Alternatively, the device channel region of the device channel region of described PMOS and described NMOS just to and distance��50 micron on both sides that distance is the shortest.
Alternatively, described region obtains subelement, including: module is determined in first area, is adapted to determine that described P type active area; Second area determines module, is adapted to determine that described N-type active area; 3rd area determination module, is suitable within the scope of described zone line, by the rectangular area between described P type active area and the described N-type active area of arbitrary neighborhood, as described region between described P type active area and described N-type active area.
Alternatively, spacing��50 micron of described adjacent P type active area and described N-type active area.
Alternatively, continuous n same kind of active area is calculated as a described protection ring, n > 1.
Compared with prior art, technical scheme has the advantage that
By directly determining the zone line between described P type active area and described N-type active area; in described zone line; obtain the virtual level corresponding with the region between described P type active area and described N-type active area; determine the quantity of described virtual level; quantity as described protection ring; the region of all non-P type active areas and non-N-type active area need not be determined; also need not judge that described region is whether between P type active area and N-type active area; thus testing procedure can be reduced, therefore complexity and the testing time of protection ring test can be reduced.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the method for testing of a kind of protection ring quantity of the prior art;
Fig. 2 is the schematic flow sheet of the method for testing of the another kind of protection ring quantity in the embodiment of the present invention;
Fig. 3 is the schematic diagram of the method for testing of a kind of protection ring quantity in the embodiment of the present invention;
Fig. 4 is the structural representation of the test device of the another kind of protection ring quantity in the embodiment of the present invention.
Detailed description of the invention
In order to avoid latch-up; it is typically between PMOS and NMOS and places protection ring (Guardring); specifically by P type active area (P+) in protection ring around NMOS ground connection, N-type active area (N+) around PMOS and is connect high level.
Test Qualify Phase before semiconductor device manufactures, consistent with the quantity of design phase determined protection ring in order to determine the device that target manufacture completes, it is necessary to detect the quantity of protection ring in described semiconductor device.
At present; can make to detect with the following method the quantity of protection ring: first determine the zone line between PMOS and NMOS; and then from described zone line, detect the region of non-P type active area and non-N-type active area; and obtain the virtual level corresponding with the region of described non-P type active area and non-N-type active area; then judge that described virtual level is whether between described P type active area and N-type active area; finally calculate the quantity of described virtual level between described P type active area and N-type active area, as the quantity of described protection ring.
Specifically it is referred to Fig. 1; if detecting the quantity of effective protection ring of structure in Fig. 1; first may determine that the zone line A between described PMOS and NMOS; then from described zone line A, detect the region of non-P type active area and non-N-type active area; i.e. respectively region 1-9; and obtain the virtual level corresponding with the region of described non-P type active area and non-N-type active area; i.e. respectively virtual level 1*-9*, then judges that described virtual level 1*-9* is whether between described P type active area and N-type active area. As it is shown in figure 1, virtual level 2*, 3*, 4* and 5* are between described P+ and N+, namely the quantity of the virtual level between described P+ and N+ is 4, it is hereby achieved that the quantity of described protection ring is 4.
It should be noted that, actual in detecting protection ring quantity by this existing method, structure within PMOS and NMOS it cannot be directly viewed, the internal structure of PMOS and NMOS is directly shown herein in FIG, only to facilitate explanation, and from Fig. 1 directly it can be seen that, 6 P+ and 2 N+ are included between PMOS shown in Fig. 1 and NMOS tube, it is effectively protected ring owing to continuous multiple same kind of active areas are done one by meter, therefore the structure shown in Fig. 1 includes 4 really and is effectively protected ring, the quantity result of effective protection ring in described structure is obtained consistent with test.
But, use above-mentioned method of testing to determine the quantity of protection ring, computation complexity is high, and operation time is long.
For solving the problems referred to above, one embodiment of the invention provides the method for testing of protection ring quantity, by directly determining the zone line between described P type active area and described N-type active area, in described zone line, obtain the virtual level corresponding with the region between described P type active area and described N-type active area, determine the quantity of described virtual level, quantity as described protection ring, can avoid determining the region of all non-P type active areas and non-N-type active area and carry out the whether judgement between P type active area and N-type active area of described region, therefore complexity and the testing time of protection ring test can be reduced
Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail.
Shown below the flow chart of the method for testing of a kind of protection ring quantity in the embodiment of the present invention; described protection ring is placed between PMOS and NMOS; described protection ring includes X P type active area and Y N-type active area; X, Y are natural number; and X >=0; Y >=0, describes in detail to described method step by step below in conjunction with Fig. 2, and described method may include that
S21: determine the zone line scope between described PMOS and described NMOS.
Protection ring owing to being placed between PMOS and NMOS just can be conducive to avoiding generation latch-up between described PMOS and NMOS, therefore in being embodied as, it is possible to first determine the zone line scope between described PMOS and described NMOS.
The device channel region of PMOS includes overlapped N trap (LayerNW), P type injection region (LayerPPLUS), active area (LayerACT), polysilicon layer (LayerGATE) this which floor, generally rectangular region, in like manner, the device channel region of NMOS includes overlapped p-well (LayerPW), N-type injection region (LayerNPLUS), active area (LayerACT), polysilicon layer (LayerGATE) this which floor, is generally also rectangle. in being embodied as, determine that the method for described zone line scope can be such that four apex coordinates of device channel region and the correspondence thereof first determining described PMOS, and then determine the device channel region of described NMOS and four apex coordinates of correspondence thereof, then can by the device channel region of the device channel region of described PMOS and described NMOS just to, and four determined regions of apex coordinate on the shortest both sides, namely the device channel region of the device channel region of described PMOS and described NMOS just to, and distance is less than four determined regions of apex coordinate on the two of default distance threshold limits, it is used as the zone line scope between described PMOS and described NMOS.
According to different technique, described distance threshold can be different. The existence of described distance threshold can so that between PMOS and NMOS of I/O port even without protection ring time, as long as distance reaches described distance threshold, it is also possible to effectively avoid latch-up. In an embodiment of the present invention, described distance threshold can be 50 microns.
S22: within the scope of described zone line, obtains the virtual level corresponding with the region between described P type active area and described N-type active area.
Described P type active area includes multiple ingredient, N-type active area also includes multiple ingredient, namely P type and N-type active area itself also have certain size, therefore described zone line is actual in P type active area, the region composition of N-type active area and non-P type active area and non-N-type active area, in an embodiment of the present invention, can within the scope of described zone line, acquisition and the region between described P type active area and described N-type active area, from the region of described non-P type active area and non-N-type active area, namely search the region between described P type active area and described N-type active area, then the virtual level corresponding to regeneration and the region between described P type active area and described N-type active area.
Specifically can first determine each described P type active area, it is then determined that each described N-type active area, then within the scope of described zone line, find adjacent P type active area and N-type active area, and then by the rectangular area between described P type active area and the described N-type active area of arbitrary neighborhood, namely in described P type active area and described N-type active area, just to and rectangle that spacing distance is formed less than the limit of described distance threshold, be used as described region between described P type active area and described N-type active area. It is understood that the present invention is not constituted any restriction by the quantity in described region between described P type active area and described N-type active area, described region can be 0, it is possible to is 1, it is also possible to for multiple.
S23: calculate the quantity of described virtual level, as the quantity of described protection ring.
In an embodiment of the present invention, continuous n same kind of active area is calculated as a described protection ring, n > 1. Ratio is put together if any 3 P type active area continuous adjacent, then 3 described P type active area meters are effectively protected ring as 1.
Owing to continuous multiple same kind of active areas are done 1 protection ring by meter; therefore in being embodied as; the quantity of virtual level corresponding to described region between described P type active area and described N-type active area, the quantity of described virtual level can be calculated, be the quantity of described protection ring.
For making those skilled in the art be more fully understood that and realizing the present invention, carry out introducing in more detail to the method for testing of the protection ring quantity in above-mentioned one embodiment of the invention illustrated in fig. 2 below in conjunction with Fig. 3:
There are how many to be effectively protected ring between PMOS and NMOS illustrated in fig. 3 for testing actually; can first determine the zone line B between described PMOS and NMOS; then within the scope of described zone line; determine between the region of P+ and N+ respectively region b, c, d and e; obtain virtual level b*, c*, d* and e* corresponding with described region b, c, d and e; the quantity 4 of last virtual level is the quantity of protection ring, namely has 4 between PMOS and NMOS and is effectively protected ring. And as seen from Figure 3; described zone line B includes 6 P type active areas, 2 N-type active areas and region a-i; namely X=6; Y=2; owing to continuous multiple same kind of active areas are done 1 protection ring by meter; therefore the quantity that can also directly obtain described protection ring is 4, consistent with the result obtained by the method for testing in the embodiment of the present invention.
It is understandable that; in being embodied as; when using the method to test the quantity being effectively protected ring in PMOS and NMOS; the concrete structure of described PMOS and NMOS; namely inside specifically includes how many P+, the order of specifically putting of how many N+ and P+ and N+ is all unknown; its structure is directly shown herein in figure 3, is intended merely to and the method is better described, so that those skilled in the art are more fully understood that and realize the present invention.
For making those skilled in the art be more fully understood that and realizing the present invention; the device of the method for testing of a kind of protection ring quantity that can realize Fig. 2 shown in has been also provided below; described protection ring is placed between PMOS and NMOS; described protection ring includes X P type active area and Y N-type active area, and X, Y are natural number.
With reference to Fig. 4, described device may include that zone line determines unit 41, virtual level acquiring unit 42 and computing unit 43, wherein:
Described zone line determines unit 41, is adapted to determine that the zone line scope between described PMOS and described NMOS;
Described virtual level acquiring unit 42, is suitable within the scope of described zone line, obtains the virtual level corresponding with the region between described P type active area and described N-type active area;
Described computing unit 43, is suitable to calculate the quantity of described virtual level, as the quantity of described protection ring.
In being embodied as, described virtual level acquiring unit 42, it is possible to including: region obtains subelement 421, be suitable to obtain the region between described P type active area and described N-type active area; Virtual level generates subelement 422, is suitable to generate the virtual level corresponding with the region between described P type active area and described N-type active area.
In being embodied as, described zone line determines unit 41, it is possible to including: subelement 411 is determined in first area, is adapted to determine that the device channel region of described PMOS and four apex coordinates of correspondence thereof; Second area determines subelement 412, is adapted to determine that the device channel region of described NMOS and four apex coordinates of correspondence thereof; Zone line determines subelement 413, be suitable to by the device channel region of the device channel region of described PMOS and described NMOS just to and four determined regions of apex coordinate on both sides that distance is the shortest, as the zone line scope between described PMOS and described NMOS.
In being embodied as, the device channel region of the device channel region of described PMOS and described NMOS just to and distance��50 micron on both sides that distance is the shortest.
In being embodied as, described region obtains subelement 413, it is possible to including: module (not shown) is determined in first area, is adapted to determine that described P type active area; Second area determines module (not shown), is adapted to determine that described N-type active area; 3rd area determination module (not shown), be suitable within the scope of described zone line, by the rectangular area between described P type active area and the described N-type active area of arbitrary neighborhood, as described region between described P type active area and described N-type active area.
In being embodied as, spacing��50 micron of described adjacent P type active area and described N-type active area. In being embodied as, continuous n same kind of active area meter is as a described protection ring, n > 1.
One of ordinary skill in the art will appreciate that all or part of step in the various methods of above-described embodiment can be by the hardware that program carrys out instruction relevant and completes, this program can be stored in in computer-readable recording medium, and storage medium may include that ROM, RAM, disk or CD etc.
Although present disclosure is as above, but the present invention is not limited to this. Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (14)
1. the method for testing of a protection ring quantity, it is characterised in that described protection ring is placed between PMOS and NMOS, described protection ring includes X P type active area and Y N-type active area, and X, Y are natural number, and described method includes:
Determine the zone line scope between described PMOS and described NMOS;
Within the scope of described zone line, obtain the virtual level corresponding with the region between described P type active area and described N-type active area;
Calculate the quantity of described virtual level, as the quantity of described protection ring.
2. the method for testing of protection ring quantity according to claim 1, it is characterised in that described within the scope of described zone line, obtains the virtual level corresponding with the region between described P type active area and described N-type active area, including:
Obtain the region between described P type active area and described N-type active area;
Generate the virtual level corresponding with the region between described P type active area and described N-type active area.
3. the method for testing of protection ring quantity according to claim 2, it is characterised in that the described zone line scope determined between described PMOS and described NMOS, including:
Determine the device channel region of described PMOS and four apex coordinates of correspondence thereof;
Determine the device channel region of described NMOS and four apex coordinates of correspondence thereof;
By the device channel region of the device channel region of described PMOS and described NMOS just to and four determined regions of apex coordinate on both sides that distance is the shortest, as the zone line scope between described PMOS and described NMOS.
4. the method for testing of protection ring quantity according to claim 3, it is characterised in that the device channel region of the device channel region of described PMOS and described NMOS just to and distance��50 micron on both sides that distance is the shortest.
5. the method for testing of protection ring quantity according to claim 2, it is characterised in that described acquisition region between described P type active area and described N-type active area, including:
Determine described P type active area;
Determine described N-type active area;
Within the scope of described zone line, by the rectangular area between described P type active area and the described N-type active area of arbitrary neighborhood, as described region between described P type active area and described N-type active area.
6. the method for testing of protection ring quantity according to claim 5, it is characterised in that spacing��50 micron of described adjacent P type active area and described N-type active area.
7. the method for testing of protection ring quantity according to claim 1, it is characterised in that n same kind of active area meter is a described protection ring, n > 1 continuously.
8. the test device of a protection ring quantity, it is characterised in that described protection ring is placed between PMOS and NMOS, described protection ring includes X P type active area and Y N-type active area, and X, Y are natural number, and described device includes:
Zone line determines unit, is adapted to determine that the zone line scope between described PMOS and described NMOS;
Virtual level acquiring unit, is suitable within the scope of described zone line, obtains the virtual level corresponding with the region between described P type active area and described N-type active area;
Computing unit, is suitable to calculate the quantity of described virtual level, as the quantity of described protection ring.
9. the test device of protection ring quantity according to claim 8, it is characterised in that described virtual level acquiring unit, including:
Region obtains subelement, is suitable to obtain the region between described P type active area and described N-type active area;
Virtual level generates subelement, is suitable to generate the virtual level corresponding with the region between described P type active area and described N-type active area.
10. the test device of protection ring quantity according to claim 9, it is characterised in that described zone line determines unit, including:
Subelement is determined in first area, is adapted to determine that the device channel region of described PMOS and four apex coordinates of correspondence thereof;
Second area determines subelement, is adapted to determine that the device channel region of described NMOS and four apex coordinates of correspondence thereof;
Zone line determines subelement, be suitable to by the device channel region of the device channel region of described PMOS and described NMOS just to and four determined regions of apex coordinate on both sides that distance is the shortest, as the zone line scope between described PMOS and described NMOS.
11. the test device of protection ring quantity according to claim 10, it is characterised in that the device channel region of the device channel region of described PMOS and described NMOS just to and distance��50 micron on both sides that distance is the shortest.
12. the test device of protection ring quantity according to claim 9, it is characterised in that described region obtains subelement, including:
Module is determined in first area, is adapted to determine that described P type active area;
Second area determines module, is adapted to determine that described N-type active area;
3rd area determination module, is suitable within the scope of described zone line, by the rectangular area between described P type active area and the described N-type active area of arbitrary neighborhood, as described region between described P type active area and described N-type active area.
13. the test device of protection ring quantity according to claim 12, it is characterised in that spacing��50 micron of described adjacent P type active area and described N-type active area.
14. the test device of protection ring quantity according to claim 8, it is characterised in that n same kind of active area is calculated as a described protection ring, n > 1 continuously.
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