CN102386185A - High-voltage and low-voltage integrated process device and preparation method thereof - Google Patents

High-voltage and low-voltage integrated process device and preparation method thereof Download PDF

Info

Publication number
CN102386185A
CN102386185A CN2010102657999A CN201010265799A CN102386185A CN 102386185 A CN102386185 A CN 102386185A CN 2010102657999 A CN2010102657999 A CN 2010102657999A CN 201010265799 A CN201010265799 A CN 201010265799A CN 102386185 A CN102386185 A CN 102386185A
Authority
CN
China
Prior art keywords
type
well
heavily doped
oxide semiconductor
effect transistor
Prior art date
Application number
CN2010102657999A
Other languages
Chinese (zh)
Inventor
刘侠
易扬波
李海松
王钦
陶平
Original Assignee
苏州博创集成电路设计有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 苏州博创集成电路设计有限公司 filed Critical 苏州博创集成电路设计有限公司
Priority to CN2010102657999A priority Critical patent/CN102386185A/en
Publication of CN102386185A publication Critical patent/CN102386185A/en

Links

Abstract

The invention discloses a high-voltage and low-voltage integrated process device and a preparation method thereof. The process device comprises low-voltage enhancement and depletion N-type metal oxide semiconductor field effect transistors, a high-voltage longitudinal double-diffusion metal oxide semiconductor field effect transistor, and medium-voltage and high-voltage enhancement and depletion N-type transverse double-diffusion metal oxide semiconductor field effect transistors. The preparation method comprises the following steps of: making an N-type epitaxial layer on an N-type heavy doped substrate, making different P-type doped wells on the N-type epitaxial layer, simultaneously making N-type voltage tolerance regions of the medium-voltage and the high-voltage enhancement and depletion N-type transverse double-diffusion metal oxide semiconductor field effect transistors on the P-type doped wells, and performing source and drain implantation on the P-type doped wells and the N-type voltage tolerance regions. The process device is an integrated longitudinal power device based on an epitaxial material, and has high process integration and reliability.

Description

一种高低压集成的工艺器件及其制备方法 A highly integrated low voltage process device and method of preparation

技术领域 FIELD

[0001] 本发明涉及半导体器件的技术领域,具体涉及一种高低压集成的工艺器件结构及其制备方法,适用于电源管理,汽车电子等领域的智能功率集成电路设计。 [0001] The present invention relates to the field of semiconductor devices, device structures and particularly relates to a process method for preparing high-low pressure integrated, smart power integrated circuit design for power management, automotive electronics and other fields.

背景技术 Background technique

[0002] 功率集成电路将高压功率器件与信号处理系统及外围结构电路,保护电路,检测电路等集成在同一芯片上,减少了系统中的元件数,互联数和焊点数,不仅可以提高系统的可靠性,稳定性,而且减了系统的功耗,体积重量和成本。 [0002] The power integrated circuit devices and high voltage power signal processing system and a peripheral structure of the circuit, the protection circuit, a detection circuit integrated on the same chip, reduces the number of components in the system, the number of interconnection and weld points, can not only improve the system reliability, stability, and reduce system power consumption, volume and weight costs. 功率集成电路最早出现在70年代后期,但直至90年代后才进入实用阶段,主要需要解决两个技术上的难题:第一个,需要有输入阻抗高,低驱动功耗的金属氧化物半导体场效应晶体管(MOS)型功率器件;第二,需要解决高低压器件集成在结构设计和工艺上的问题,既需保证低压和高压器件都能正常工作又不相互影响,要有较高的可靠性,同时须能兼容现有的低压互补型金属氧化物半导体场效应晶体管(CM0Q工艺,易产业化。 Power integrated circuits first appeared in the late 1970s, but until the 1990s before entering the practical stage, need to address two main technical problems: first, the need for high input impedance, low metal-oxide-semiconductor field-power drive effect transistors (MOS) power devices; second, high and low voltage devices need to be addressed in the design and integration of process issues, the need to ensure both low and high pressure devices can work without affecting each other, have a high reliability , while a low pressure to be compatible with existing complementary metal oxide semiconductor field effect transistor (CM0Q process easy industrialization.

[0003] 本发明提出了一种高低压集成的工艺器件及其制备方法,具有设计简单、可靠性高、能避免CMOS器件存在Latch-Up (闩锁效应)的风险等优点,适用于电源管理,汽车电子等领域里面的智能功率集成电路设计。 [0003] The present invention provides a process for preparing device and a method of high and low voltage integrated, simple design, high reliability, there is an advantage to avoid the risk of Latch-Up (latch) of a CMOS device for power management , automotive electronics and other fields inside the smart power integrated circuit design. .

发明内容 SUMMARY

[0004] 为克服现有技术的不同,本发明的目的在于提供一种高低压集成的工艺器件及其制备方法。 [0004] In order to overcome various prior art, an object of the present invention to provide a device and a process of a method for preparing high-low pressure integrated. 适用于电源管理,汽车电子等领域里面的智能功率集成电路设计。 For power management, automotive electronics and other fields inside the smart power integrated circuit design.

[0005] 本发明所述高低压集成的工艺器件结构采用如下技术方案: [0005] The present invention is an integrated high and low pressure process of the device structure using the following technical solutions:

[0006] 一种高低压集成的工艺器件,包括:N型重掺杂衬底,所述N型衬底上设有N型外延层,所述N型外延层上设有低压增强型N型金属氧化物半导体场效应晶体管、低压耗尽型N型金属氧化物半导体场效应晶体管、高压纵向双扩散金属氧化物半导体场效应晶体管和中高压增强型N型横向双扩散金属氧化物半导体场效应晶体管、中高压耗尽型N型横向双扩散金属氧化物半导体场效应晶体管,其特征在于,所述低压增强型N型金属氧化物半导体场效应晶体管、所述低压耗尽型N型金属氧化物半导体场效应晶体管和所述中高压增强型N型横向双扩散金属氧化物半导体场效应晶体管、所述中高压耗尽型N型横向双扩散金属氧化物半导体场效应晶体管均位于第一P型掺杂阱,所述低压增强型N型金属氧化物半导体场效应晶体管、所述低压耗尽型N型金属氧化物半导体场效应晶体 [0006] A high and low pressure process of the integrated device, comprising: N type heavily doped substrate, the N type epitaxial layer is provided on the N-type substrate, with low-voltage enhancement type N-type epitaxial layer on said N-type metal oxide semiconductor field effect transistor, low-voltage depletion type N-type metal oxide semiconductor field effect transistor, the high-pressure vertical double diffused metal oxide semiconductor field effect transistor and an N-type enhancement mode high voltage lateral double diffused metal oxide semiconductor field effect transistor , high pressure depletion type N-type lateral double diffused metal oxide semiconductor field effect transistor, wherein said low-voltage enhancement mode N-type metal oxide semiconductor field effect transistor, the low depletion type N-type metal oxide semiconductor field effect transistor and said enhancement type N-type high voltage lateral double diffused metal oxide semiconductor field effect transistor, the depletion-type N-type high voltage lateral double diffused metal oxide semiconductor field effect transistor are located on the first P-type doped well, the low-voltage enhancement mode N-type metal oxide semiconductor field effect transistor, the low depletion type N-type metal oxide semiconductor field effect transistor 管、所述中高压增强型N型横向双扩散金属氧化物半导体场效应晶体管、所述中高压耗尽型N型横向双扩散金属氧化物半导体场效应晶体管和所述高压纵向双扩散金属氧化物半导体场效应晶体管之间采用自隔离结构。 Tube, the high pressure enhancement N-type lateral double diffused metal oxide semiconductor field effect transistor, the depletion-type N-type high voltage lateral double diffused metal oxide semiconductor field effect transistor and the high vertical double diffused metal oxide self isolation structure between the semiconductor field effect transistor.

[0007] 优选的,所述低压增强型N型金属氧化物半导体场效应晶体管包括所述第一P型掺杂阱,所述第一P型掺杂阱上设有第一P型重掺杂体接触阱、第一源端N型重掺杂阱和第一漏端N型重掺杂阱,所述第一P型重掺杂体接触阱和所述第一源端N型重掺杂阱之间设有第一场氧化层,所述第一源端N型重掺杂阱和所述第一漏端N型重掺杂阱之间的沟道区上方设有第一栅氧化层,所述第一栅氧化层上方设有第一多晶硅栅极。 [0007] Preferably, the low-voltage enhancement mode N-type metal oxide semiconductor field effect transistor comprising a first P-type doped well, a first P-type heavily doped well of the first P-type doped contacting the well, a first N type heavily doped source well and the drain terminal of the first N-type heavily doped well of the first P-type heavily doped well body contact and said first heavily doped N-type source a first field oxide layer is provided between the well, of the first heavily doped N-type source well and the drain terminal of the first N-type heavily doped well over the channel region between the first gate oxide layer provided , over the first gate oxide layer is provided with a first polysilicon gate. 所述第一P型重掺杂体接触阱、所述第一源端N型重掺杂阱及所述第一漏端N型重掺杂阱上分别连接有金属引线,所述第一P型重掺杂体接触阱、所述第一源端N型重掺杂阱、所述第一漏端N型重掺杂阱、所述第一场氧化层、所述第一栅氧化层、所述第一多晶硅栅极以及金属引线以外的区域设有介质氧化层。 The first P-type heavily doped well body contact, the first heavily doped N-type source and well drain terminal of said first heavily doped N-type well are respectively connected to the metal lead, the first P type heavily doped well body contact, the first heavily doped N-type source well, the first drain terminal of the N-type heavily doped well of the first field oxide layer, said first gate oxide layer, the first polysilicon gate and a region other than the dielectric oxide layer is provided with metal leads.

[0008] 优选的,所述低压耗尽型N型金属氧化物半导体场效应晶体管包括所述第一P型掺杂阱,在所述第一P型掺杂阱上设有所述第一P型重掺杂体接触阱、第二源端N型重掺杂阱和第二漏端N型重掺杂阱,所述低压增强型N型金属氧化物半导体场效应晶体管的所述第一漏端N型重掺杂阱和所述低压耗尽型N型金属氧化物半导体场效应晶体管的所述第二源端N型重掺杂阱之间设有所述第一场氧化层,所述第二源端N型重掺杂阱和所述第二漏端N型重掺杂阱之间的沟道区设有第一耗尽注入层,所述第二源端N型重掺杂阱和所述第二漏端N型重掺杂阱之间的沟道区上方设有第二栅氧化层,所述第二栅氧化层上方设有第二多晶硅栅极,所述第一P型重掺杂体接触阱、所述第二源端N型重掺杂阱及所述第二漏端N型重掺杂阱上分别连接有金属引线,所述第一P型重掺杂体接触阱、所述 [0008] Preferably, the low-pressure depletion type N-type metal oxide semiconductor field effect transistor comprising a first P-type doped well of the first P provided on the first P-type doped well body contact type heavily doped well, a second N + source well and the drain terminal of the second N-type heavily doped well, the low-voltage enhancement mode N-type metal-oxide semiconductor field-effect transistor of the first drain the end of the heavily doped N-type well and said low pressure depletion type N-type metal oxide semiconductor field effect transistor, a second source is provided with a heavily doped N-type first well between the field oxide layer, said a second heavily doped N-type source well and the drain terminal of the second heavily doped N-type channel region between the injection well is provided with a first depletion layer, the second N type heavily doped source well and the second heavily doped N-type drain terminal over the channel region between the second well has a gate oxide layer, the second gate oxide layer is provided over a second polysilicon gate, said first P + body contact wells, said second heavily doped N-type source and well drain terminal of said second heavily doped N-type wells are connected to metal leads, said first heavily doped P-type contacting the well, the 第二源端N型重掺杂阱、所述第二漏端N型重掺杂阱、所述第一场氧化层、所述第二栅氧化层、所述第二多晶硅栅极以及金属引线以外的区域设有介质氧化层。 A second heavily doped source N type well, the drain terminal of the second N-type heavily doped well of the first field oxide layer, the second gate oxide layer, the second polysilicon gate, and region other than the dielectric oxide layer is provided with metal leads.

[0009] 优选的,所述高压纵向双扩散金属氧化物半导体场效应晶体管包括所述N型重掺杂衬底,所述N型重掺杂衬底上设有N型外延层,所述N型外延层上设有第二P型掺杂阱, 所述第二P型掺杂阱上设有第二P型重掺杂体接触阱和第三源端N型重掺杂阱,所述第二P 型掺杂阱包括所述第三源端N型重掺杂阱的沟道区上方设有第三栅氧化层,所述第二P型掺杂阱和所述第二P型重掺杂体接触阱之间的区域设有第二场氧化层,所述第三栅氧化层和所述第二场氧化层上方设有第三多晶硅栅极,所述第二P型重掺杂体接触阱、所述第三源端N型重掺杂阱上连接有金属引线,所述第二P型重掺杂体接触阱、所述第三源端N型重掺杂阱、所述第二场氧化层、所述第三栅氧化层、所述第三多晶硅栅极以及金属引线以外的区域设有所述介质氧化层,所述N型重掺杂衬底底部设有金属引线 [0009] Preferably, the high-pressure vertical double diffused metal oxide semiconductor field effect transistor comprising a heavily doped N-type substrate, the N type heavily doped N-type epitaxial layer provided on a substrate, the N type epitaxial layer provided with a second P-doped well of the second P-type doped with P type heavily doped second well and a third body contact source N type heavily doped well the well, the the second P-type doped well comprises a heavily doped well over the channel region of the third N-type source provided with a third gate oxide layer, the second P-type doped second well and the P type heavily doped well body contact region between the second field oxide layer is provided, the third gate oxide layer over said second and third field oxide layer is provided with a polysilicon gate, said second P type heavily doped well body contact, said third heavily doped N-type source connected to the well with a metal wire, said second heavily doped P-type well body contact, said third heavily doped source N type well, the second field oxide layer, the third gate oxide layer region other than the gate polysilicon and a metal wire provided with the said third dielectric oxide layer, said N type heavily doped substrate provided at the bottom metal lead 为漏端电极。 It is the drain terminal electrode.

[0010] 优选的,所述中高压增强型N型横向双扩散金属氧化物半导体场效应晶体管包括第一P型掺杂阱,所述第一P型掺杂阱上设有第一N型掺杂阱、第四源端N型重掺杂区和第三P型重掺杂体接触阱,所述第一N型掺杂阱上设有第三漏端N型重掺杂阱,所述第一N 型掺杂阱和所述源端N型重掺杂区之间的沟道区上方设有第四栅氧化层,所述第三P型重掺杂体接触阱和所述第四源端N型重掺杂阱、所述第三漏端N型重掺杂阱及沟道区以外的区域均设有场氧化层,栅氧化层上方及所述第一N型掺杂阱和所述第三漏端N型重掺杂阱之间的所述第三场氧化层近源一端上方设有第四多晶硅栅极,所述第三P型重掺杂体接触阱、所述第四源端N型重掺杂阱及所述第三漏端N型重掺杂阱上分别连接有金属引线,所述第三P型重掺杂体接触阱、所述第四源端N型重掺杂阱、所述第三漏端N型重 [0010] Preferably, the high-voltage N-type enhancement mode lateral double diffused metal oxide semiconductor field effect transistor comprising a first P-type doped well of the first P-type doped well is provided on the first N-type doping heteroaryl well, a fourth heavily doped N-type source region and a third P-type heavily doped well body contact with the drain terminal of the third N-type heavily doped N-type well doping said first well, said over the channel region between the first N-type doped well and the heavily doped N-type source region is provided with a fourth gate oxide layer, said third heavily doped P-type well and said fourth body contact heavily doped source N type well, the drain terminal of the third N-type heavily doped than the well region and the channel region of the field oxide layer are provided, and a gate oxide layer over said first N-type doped well and the drain terminal of the third N-type heavily doped oxide layer over the proximal end of the third well is provided between the fourth polysilicon gates of the third P-type heavily doped well body contact, the said fourth N type heavily doped source well and the drain terminal of the third heavily doped N-type wells are connected to metal leads, contacting a well of said third heavily doped P-type, the fourth source heavily doped N-type well, the drain terminal of the third N-type heavy 杂阱、所述第三场氧化层、所述第四栅氧化层、所述第四多晶硅栅极以及所述金属引线以外的区域设有介质氧化层。 Heteroaryl well, a field oxide layer and the third, the fourth gate oxide layer, polysilicon gates, and the fourth area other than the dielectric oxide layer is provided with metal leads.

[0011] 优选的,所述中高压耗尽型N型横向双扩散金属氧化物半导体场效应晶体管包括第一P型掺杂阱,所述第一P型掺杂阱上设有第二N型掺杂阱、第五源端N型重掺杂区和第三P型重掺杂体接触阱,所述第二N型掺杂阱上设有第四漏端N型重掺杂区,所述第二N 型掺杂阱和所述第五源端N型重掺杂区之间的沟道区设有第二耗尽注入层,所述第二N型掺杂阱和所述第五源端N型重掺杂区之间的沟道区上方设有第五栅氧化层,所述第三P型重掺杂体接触阱和所述第五源端N型重掺杂阱、所述第四漏端N型重掺杂阱及沟道区以外的区域均设有场氧化层,第五栅氧化层上方及所述第二N型掺杂阱和所述第四漏端N型重掺杂阱之间的所述第三场氧化层近源一端上方设有第五多晶硅栅极,所述第三P型重掺杂体接触阱、所述第五源端N型重掺杂阱及所述第四漏端N型重掺杂阱上分别连接 [0011] Preferably, the high-voltage depletion type N-type lateral double diffused metal oxide semiconductor field effect transistor comprising a first P-type doped well, a second N-type provided on the first P-type doped well doped well, the well body contact fifth heavily doped N-type source region, and a third heavily doped P-type, with the drain terminal of the fourth N-type heavily doped region of the second N-type doped well, the a second channel region between said N-type doped well and said fifth heavily doped N-type source region implanted with the second depletion layer, the second N-type doped well and the fifth over the channel region between N + source region is provided with a fifth gate oxide layer, the third P-type well and contacting the heavy body fifth source doped heavily doped N-type well, the the drain terminal of said fourth N-type heavily doped than the well region and the channel region of the field oxide layer are provided, and a fifth gate oxide layer over said second N-type doped well and the drain terminal of the fourth N-type the heavily doped source near the top end of the third well between the field oxide layer is provided with a fifth polysilicon gate, said third P-well body contact type heavily doped, said fifth N-type source weight fourth doped well and the heavily doped N-type drain terminals respectively connected to the well 有金属引线,所述第三P型重掺杂体接触阱、所述第五源端N型重掺杂阱、所述第四漏端N型重掺杂阱、所述第三场氧化层、所述第五栅氧化层、所述第五多晶硅栅极以及所述金属引线以外的区域设有介质氧化层。 A metal wire, a third P-type heavily doped well body contact, the source terminal of the fifth N-type heavily doped well, the drain terminal of said fourth heavily doped N-type well, said third field oxide layer , the fifth region other than the gate oxide layer, polysilicon gates of the fifth and the dielectric oxide layer is provided with metal leads.

[0012] 优选的,所述低压增强型N型金属氧化物半导体场效应晶体管、所述低压耗尽型N 型金属氧化物半导体场效应晶体管、所述中高压增强型N型横向双扩散金属氧化物半导体场效应晶体管、所述中高压耗尽型N型横向双扩散金属氧化物半导体场效应晶体管和所述高压纵向双扩散金属氧化物半导体场效应晶体管之间是通过所述N型外延层与所述第一P 型掺杂阱形成的PN结反向作用来实现自隔离。 [0012] Preferably, the low-voltage enhancement mode N-type metal oxide semiconductor field effect transistor, the low depletion type N-type metal oxide semiconductor field effect transistor, the enhancement N-type high voltage lateral double diffused metal oxide semiconductor field effect transistor, through the N-type epitaxial layer between the N-type depletion mode high voltage lateral double diffused metal oxide semiconductor field effect transistor and the high vertical double diffused metal oxide semiconductor field effect transistor the first P-type doped PN junction reverse effect is achieved from the well formation isolation.

[0013] 优选的,所述高压纵向双扩散金属氧化物半导体场效应晶体管的沟道区第三栅氧化层采用与所述低压增强型N型金属氧化物半导体场效应晶体管、耗尽型N型金属氧化物半导体场效应晶体相同的栅氧工艺;所述高压纵向双扩散金属氧化物半导体场效应晶体管的两个所述第二P型掺杂阱之间采用第二场氧化层。 [0013] Preferably, the channel region of the high voltage vertical double diffused metal oxide semiconductor field effect transistor using a third gate oxide layer and the low-voltage enhancement mode N-type metal-oxide semiconductor field effect transistor, a depletion type N-type same MOSFET gate oxide crystal technology; the two P-type high-pressure and the second vertical double diffused metal oxide semiconductor field effect transistor of the second field oxide layer using doped between the well.

[0014] 本发明的一种高低压集成的工艺器件的制备步骤如下: [0014] Procedure for preparation of the present invention a high-low pressure integrated process of the device is as follows:

[0015] 首先,取所述重掺杂的N型衬底,所述N型衬底上生长所述N型外延层,接着在所述N型外延层上进行P型杂质的光刻注入,经高温退火形成所述低压增强型N型金属氧化物半导体场效应晶体管、所述低压耗尽型N型金属氧化物半导体场效应晶体管和所述中高压增强型N型横向双扩散金属氧化物半导体场效应晶体管、所述中高压耗尽型N型横向双扩散金属氧化物半导体场效应晶体管所需的所述第一P型掺杂阱;接着在所述第一P型掺杂阱上进行N型杂质的光刻注入,用以制作所述中高压增强型N型横向双扩散金属氧化物半导体场效应晶体管和所述中高压耗尽型N型横向双扩散金属氧化物半导体场效应晶体管的第一N型掺杂阱、第二N型掺杂阱,所述N型外延层上进行P型杂质的光刻注入,用以制作所述高压纵向双扩散金属氧化物半导体场效应晶体管的第二P型掺杂阱, [0015] Firstly, taking the heavily doped N-type substrate, the N-type epitaxial layer grown on the N-type substrate, followed by photolithography implanted P-type impurities in the N-type epitaxial layer, the low temperature annealing after forming an N-type enhancement mode metal oxide semiconductor field effect transistor, said low voltage N-type depletion mode metal oxide semiconductor field effect transistors and said enhancement mode N-type high voltage lateral double diffused metal oxide semiconductor a field effect transistor, the high pressure required for the depletion type N-type lateral double diffused metal oxide semiconductor field effect transistors of the first P-type doped well; followed by N on the first P-type doped well photolithography type impurity, used to make the first high-voltage N-type enhancement mode lateral double diffused metal oxide semiconductor field effect transistor and said depletion-mode N-type high voltage lateral double diffused metal oxide semiconductor field effect transistor an N-type doped well, a second N-type doped well, a photolithography implanted P-type impurities on said N-type epitaxial layer, for fabricating the high voltage vertical double diffused metal oxide semiconductor field effect transistor of the second P-type doped well, 后进行高温退火工艺;接着进行有源区光刻,采用湿氧化工艺生长所述第一场氧化层、所述第二场氧化层、所述第三场氧化层,接着进行N型杂质的光刻注入,形成所述低压耗尽型N型金属氧化物半导体场效应晶体管和所述中高压耗尽型N型横向双扩散金属氧化物半导体场效应晶体管的所述第一耗尽注入层和第二耗尽注入层,清洗后再采用干氧化工艺生长所述第一栅氧化层、所述第二栅氧化层、所述第三栅氧化层、所述第四栅氧化层和所述第五栅氧化层, 然后进行多晶硅的淀积和刻蚀,以形成所述低压增强型N型金属氧化物半导体场效应晶体管、所述低压耗尽型N型金属氧化物半导体场效应晶体管、所述高压纵向双扩散金属氧化物半导体场效应晶体管和所述中高压增强型N型横向双扩散金属氧化物半导体场效应晶体管、所述中高压耗尽型N型横向双扩散金 After a high temperature annealing process; active region followed by photolithography using a wet oxidation process first growing the field oxide layer, said second field oxide layer, said third oxide layer, followed by N-type impurity light injection moment, the forming of the semiconductor field-effect transistor low-voltage lateral double diffused metal oxide depletion type N-type metal oxide semiconductor field effect transistor and said depletion type N-type high-pressure injection layer and a first depletion two injection layer depletion, and then washed using a dry oxidation process first growing the gate oxide layer, the second gate oxide layer, the third gate oxide layer, the fourth layer and the fifth gate oxide a gate oxide layer, polysilicon is deposited and then etched to form the low-voltage enhancement mode N-type metal oxide semiconductor field effect transistor, the low depletion type N-type metal oxide semiconductor field effect transistor, the high-pressure vertical double diffused metal oxide semiconductor field effect transistors and said enhancement mode N-type high voltage lateral double diffused metal oxide semiconductor field effect transistor, the depletion-type N-type high voltage lateral double diffused metal 氧化物半导体场效应晶体管的所述第一多晶硅栅极、所述第二多晶硅栅极、所述第三多晶硅栅极、所述第四多晶硅栅极和所述第五多晶硅栅极; The oxide semiconductor field effect transistor of a first polysilicon gate, said second polysilicon gate, said third polysilicon gate, said fourth and said first polysilicon gate five polysilicon gate;

[0016] 然后,进行高浓度N型杂质的光刻注入,用以制作所述低压增强型N型金属氧化物半导体场效应晶体管的所述第一源端N型重掺杂阱和所述第一漏端N型重掺杂阱、所述低压耗尽型N型金属氧化物半导体场效应晶体管的所述第二源端N型重掺杂阱和所述第二漏端N型重掺杂阱、所述高压纵向双扩散金属氧化物半导体场效应晶体管的所述第三源端N型重掺杂阱以及所述中高压增强型N型横向双扩散金属氧化物半导体场效应晶体管的所述第四源端N型重掺杂阱和第三所述漏端N型重掺杂阱、所述中高压耗尽型N型横向双扩散金属氧化物半导体场效应晶体管的所述第五源端N型重掺杂阱和所述第四漏端N型重掺杂阱;接着进行高浓度P型杂质的光刻注入,用以制作所述低压增强型N型金属氧化物半导体场效应晶体管和所述低压耗尽型N型金属氧化物半导体场效应晶体管的所 [0016] Then, photolithography implantation of high-concentration N-type impurity, for the production of the semiconductor field-effect transistor of N-type metal oxide source a first low-voltage enhancement type N type heavily doped well and said second a drain terminal of N-type heavily doped well, the low-voltage depletion type N-type metal oxide semiconductor field effect transistor of the second N + source well and the drain terminal of the second N + the well, the high-voltage semiconductor field-effect transistor of the vertical double diffused metal oxide source of the third N-type heavily doped well and the N-type enhancement mode high voltage lateral double diffused metal oxide semiconductor field effect transistor a fourth heavily doped N-type source well and the drain terminal of said third heavily doped N-type well, said N-type depletion mode high voltage lateral double diffused metal oxide semiconductor field effect transistor, a fifth source heavily doped N-type well and the drain terminal of the fourth N-type heavily doped well; followed by photolithography implantation of high-concentration P-type impurity, used to make the low-voltage enhancement mode N-type metal oxide semiconductor field effect transistor and the low-voltage depletion type N-type metal oxide semiconductor field effect transistor being 第一P型重掺杂体接触阱、所述高压纵向双扩散金属氧化物半导体场效应晶体管的所述第二P型重掺杂体接触阱以及所述中高压增强型N型横向双扩散金属氧化物半导体场效应晶体管和所述中高压耗尽型N型横向双扩散金属氧化物半导体场效应晶体管的所述第三P型重掺杂体接触阱;然后进行退火工艺,接着淀积介质氧化层,刻蚀接触孔,蒸铝,反刻铝,形成电极后进行钝化处理; A first heavily doped body contact P-type well, the well and contacting said lateral double diffused metal-type high-voltage N-type enhancement of the high-pressure vertical double diffused metal oxide semiconductor field effect transistor of the second type heavily doped P the oxide semiconductor field effect transistor and said depletion-mode N-type high voltage lateral double diffused metal oxide semiconductor field effect transistor, a third P-type heavily doped body contact well; followed by annealing process, and then depositing a dielectric oxide layer, etching the contact hole, aluminum evaporation, the anti-engraved aluminum, to form an electrode passivation;

[0017] 最后,对圆片背面减薄,进行背面金属化处理后,作为所述高压纵向双扩散金属氧化物半导体场效应晶体管的漏端电极。 [0017] Finally, the back surface of the wafer after thinning process for the back side metallization, which is the drain electrode of the high-pressure side vertical double diffused metal oxide semiconductor field effect transistor.

[0018] 与现有技术相比,本发明具有如下优点: [0018] Compared with the prior art, the present invention has the following advantages:

[0019] (1)本发明结构及制备方法,基于外延材料集成纵向功率器件,与通常的横向功率器件集成相比,集成度高,节约版图成本,同时更容易实现不同耐压和导通电阻的功率器件设计。 [0019] (1) the structure and preparation method of the present invention, based on the longitudinal epitaxial material integrated power device, compared to integration, high integration, cost saving layout generally lateral power devices, while easier to implement different breakdown voltage and on-resistance the power device design.

[0020] (¾本发明将低压增强型N型金属氧化物半导体场效应晶体管、低压耗尽型N型金属氧化物半导体场效应晶体管、增强型N型横向双扩散金属氧化物半导体场效应晶体管、 耗尽型N型横向双扩散金属氧化物半导体场效应晶体管和高压纵向双扩散金属氧化物半导体场效应晶体管结构集成在一起,可以兼容低压CMOS工艺方法制作,并且先制备高压部分所特有结构,然后再制备低压部分以及低压与高压部分共有的结构,最后加入背面工艺。 鉴于低压器件部分制备在后,高压器件部分的制备在先,故不会对低压金属氧化物半导体场效应晶体管产生影响,所以,本发明的高压器件结构的制备方法能够兼容标准外延CMOS 的制造工艺并且具有可靠性高的优点。 [0020] (¾ of the present invention, low-voltage enhancement mode N-type metal oxide semiconductor field effect transistor, low-voltage depletion type N-type metal oxide semiconductor field effect transistors, enhancement mode N-type lateral double diffused metal oxide semiconductor field effect transistor, N-type depletion mode lateral double diffused metal oxide semiconductor field effect transistor and a high voltage vertical double diffused metal oxide semiconductor field effect transistor structure integrated, low voltage CMOS compatible process for making and preparing the high pressure portion to the unique structure, and and then preparing the low pressure portion and the low and the high pressure part of a total structure, finally adding the technical back. in view of the low pressure preparation device portion after preparation, the previous high-voltage portion of the device, it will not affect the low-voltage metal oxide semiconductor field effect transistors, process for preparing high-voltage device structure of the present invention is compatible with CMOS fabrication processes and epitaxial standard has the advantage of high reliability.

[0021] (3)本发明采用增强型/耗尽型N型金属氧化物半导体场效应晶体管(E/DM0S)低压器件结构,避免了CMOS器件存在Latch-Up (闩锁效应)的风险。 [0021] (3) the present invention uses an enhanced / depletion type N-type metal oxide semiconductor field effect transistor device structure of the low-pressure (E / DM0S), avoiding the risk of the presence of Latch-Up (latch) CMOS device.

附图说明 BRIEF DESCRIPTION

[0022] 图1是本发明的高低压集成的工艺器件结构示意图。 [0022] FIG. 1 is a high and low of the present invention is an integrated process schematic device structure.

[0023] 图2是本发明的高低压集成的工艺器件结构的制备工艺步骤一的示意图。 [0023] FIG. 2 is a schematic view showing the process steps of high and low pressure process of the present invention is an integrated device structure.

[0024] 图3是本发明的高低压集成的工艺器件结构的制备工艺步骤二的示意图。 [0024] FIG. 3 is a schematic view showing a two step process of the present invention, the high and low pressure process of the device integrated structure.

[0025] 图4是本发明的高低压集成的工艺器件结构的制备工艺步骤三的示意图。 [0025] FIG. 4 is a schematic view showing the process steps of high and low pressure process of the present invention is an integrated device structure III.

[0026] 图5是本发明的高低压集成的工艺器件结构的制备工艺步骤四的示意图。 [0026] FIG. 5 is a schematic view showing a fourth step of the process of the present invention, the high and low pressure process of the integrated device structure.

[0027] 图6是本发明的高低压集成的工艺器件结构的制备工艺步骤五的示意图。 [0027] FIG. 6 is a schematic view showing the process steps of high and low pressure process of the present invention is an integrated device structure of five. [0028] 图7是本发明的高低压集成的工艺器件结构的制备工艺步骤六的示意图。 [0028] FIG. 7 is a schematic view showing the process steps of high and low pressure process of the present invention is an integrated device structure VI.

[0029] 图8是本发明的高低压集成的工艺器件结构的制备工艺步骤七的示意图。 [0029] FIG. 8 is a schematic view showing the process steps of high and low pressure process of the present invention is an integrated device structure VII.

[0030] 图中标号说明:1. N型重掺杂衬底,2. N型外延层,3.第一P型掺杂阱,4.第一P型重掺杂体接触阱,5.第一源端N型重掺杂阱,6.第一漏端N型重掺杂阱,7.第二源端N型重掺杂阱,8.第二漏端N型重掺杂阱,9.第一栅氧化层,10.第一多晶硅栅极,11.第二栅氧化层,12.第二多晶硅栅极,13.第一耗尽注入层14.第一场氧化层,15.第二P型掺杂阱, 16.第二P型重掺杂体接触阱,17.第三源端N型重掺杂阱,18.第三栅氧化层,19.第二场氧化层,20.第三多晶硅栅极,21.第一N型掺杂阱,22.第二N型掺杂阱,23.漏端N型重掺杂区,24.源端N型重掺杂区,25.第三P型重掺杂体接触阱,26.第四栅氧化层,27.第四多晶硅栅极,28.第三漏端N型重掺杂阱,29.第四源端N型重掺杂阱,30.第五栅氧化层,31.第五多晶硅栅极和场板,32.第二耗尽注入层,33.第三场氧化层,34.介质氧化层,35.低压增强型N [0030] FIG described in reference:. 1 N type heavily doped substrate, 2 N-type epitaxial layer, a first P-type doped well 3, 4 a first heavily doped body contact P-type well, 5.... a first heavily doped N-type source well, 6. The first end of the N + drain well, 7. The second N-type heavily doped source well, 8. The second drain terminal heavily doped N-type well, 9. The first gate oxide layer 10. first polysilicon gate 11. The second gate oxide layer 12. The second polysilicon gate, 13. The first injection depletion field oxide layer 14. The first layer 15. The second P-type doped well, the well body contact 16. A second P type heavily doped, 17. The third source N type heavily doped well 18. The third gate oxide layer 19. The second field oxide layer 20. The third polysilicon gates 21. The first N-type doped well 22. The second N-type doped well 23. The drain terminal of the N-type heavily doped region 24. N source type heavily doped region 25. The heavily doped P-type third body contact wells, 26 fourth gate oxide layer 27. The fourth polysilicon gates 28. The third drain terminal of N-type heavily doped well, 29. The source of the fourth N-type heavily doped well 30. The fifth gate oxide layer 31 and the fifth polysilicon gate field plate 32. The second injection depletion layer, 33 third field oxide layer , 34. The dielectric oxide layer 35 of low-voltage enhancement mode N 金属氧化物半导体场效应晶体管、36.低压耗尽型N型金属氧化物半导体场效应晶体管、37.高压纵向双扩散金属氧化物半导体场效应晶体管,38.中高压增强型N型横向双扩散金属氧化物半导体场效应晶体管、39.中高压耗尽型N型横向双扩散金属氧化物半导体场效应晶体管。 Metal oxide semiconductor field effect transistor 36 low pressure depletion type N-type metal oxide semiconductor field effect transistor 37 high voltage vertical double diffused metal oxide semiconductor field effect transistor 38. N-type enhancement mode high voltage lateral double diffused metal an oxide semiconductor field effect transistor 39 a depletion type N-type high voltage lateral double diffused metal oxide semiconductor field effect transistor.

具体实施方式 Detailed ways

[0031] 实施例1 [0031] Example 1

[0032] 下面结合附图,对本发明一种高低压集成的工艺器件的结构作详细说明。 [0032] DRAWINGS The present invention is an integrated structure of a high and low pressure process of the device described in detail.

[0033] 如图1所示,一种高低压集成的工艺器件,包括:N型重掺杂衬底1,所述N型重掺杂衬底1上设有N型外延层2,N型外延层2上设有低压增强型N型金属氧化物半导体场效应晶体管35、低压耗尽型N型金属氧化物半导体场效应晶体管36、高压纵向双扩散金属氧化物半导体场效应晶体管37和中高压增强型N型横向双扩散金属氧化物半导体场效应晶体管38、中高压耗尽型N型横向双扩散金属氧化物半导体场效应晶体管39,其特征在于,低压增强型N型金属氧化物半导体场效应晶体管35、低压耗尽型N型金属氧化物半导体场效应晶体管36和中高压增强型N型横向双扩散金属氧化物半导体场效应晶体管38、中高压耗尽型N型横向双扩散金属氧化物半导体场效应晶体管39均位于第一P型掺杂阱3低压增强型N型金属氧化物半导体场效应晶体管35、低压耗尽型N型金属氧化物半导体场效应 [0033] As shown in FIG. 1, a highly integrated low voltage technology devices, comprising: N type heavily doped substrate 1, the N type heavily doped N-type epitaxial layer 2 is provided on the substrate 1, the N-type with low-voltage enhancement mode N-type metal oxide 35, low-voltage depletion type N-type metal oxide semiconductor field effect transistor 36, high voltage vertical double diffused metal oxide semiconductor field effect transistors 37 and high-voltage field-effect transistor on a semiconductor epitaxial layer 2 N-type enhancement mode lateral double diffused metal oxide semiconductor field effect transistor 38, a depletion type N-type high voltage lateral double diffused metal oxide semiconductor field effect transistor 39, characterized in that the low-voltage enhancement mode N-type metal oxide semiconductor field effect transistor 35, N-type low-voltage depletion mode metal oxide semiconductor field effect transistor 36 and N-type enhancement mode high voltage lateral double diffused metal oxide semiconductor field effect transistor 38, a depletion type N-type high voltage lateral double diffused metal oxide semiconductor a first field effect transistor 39 are located in the P-type well 3 doped N-type low-voltage enhancement mode metal oxide semiconductor field effect transistor 35, low-voltage N-type depletion mode MOSFET 体管36、中高压增强型N型横向双扩散金属氧化物半导体场效应晶体管38、中高压耗尽型N型横向双扩散金属氧化物半导体场效应晶体管39和高压纵向双扩散金属氧化物半导体场效应晶体管37之间采用自隔离结构。 Transistors 36, 38, the high-voltage depletion type N-type lateral double diffused metal oxide semiconductor field effect transistor 39 and a high voltage vertical double diffused metal oxide semiconductor field enhancement N-type high voltage lateral double diffused metal oxide semiconductor field effect transistor The isolation structure between the self-effect transistor 37.

[0034] 上述低压增强型N型金属氧化物半导体场效应晶体管35包括第一P型掺杂阱3, 第一P型掺杂阱3上设有第一P型重掺杂体接触阱4、第一源端N型重掺杂阱5和第一漏端N型重掺杂阱6,第一P型重掺杂体接触阱4和第一源端N型重掺杂阱5之间设有第一场氧化层14,第一源端N型重掺杂阱5和第一漏端N型重掺杂阱6之间的沟道区上方设有第一栅氧化层9,第一栅氧化层9上方设有第一多晶硅栅极10,第一P型重掺杂体接触阱4、第一源端N型重掺杂阱5及第一漏端N型重掺杂阱6上分别连接有金属引线,第一P型重掺杂体接触阱4、第一源端N型重掺杂阱5、第一漏端N型重掺杂阱6、第一场氧化层14、第一栅氧化层9、第一多晶硅栅极10以及金属引线以外的区域设有介质氧化层34,[0035] 上述低压耗尽型N型金属氧化物半导体场效应晶体管36包括所述第一P型掺杂阱3,第一P型掺杂阱3上设有 [0034] The low-voltage enhancement mode N-type metal oxide semiconductor field effect transistor 35 comprises a first P-type doped well 3, a first P-type well 3 is provided with a first doped P-type heavily doped well body contact 4, a first heavily doped N-type source and a first drain terminal well 5 heavily doped N-type well 6, the well 4 and the first body contact source of the first N-type heavily doped P-type heavily doped well 5 provided between a first field oxide layer 14, a first N-type source and a first heavily doped well 5 heavily doped N-type drain terminal over the channel region between the well 6 is provided with a first gate oxide layer 9, the first gate 9 is provided with a first oxide layer over the polysilicon gate 10, a first P-type heavily doped well body contact 4, a first heavily doped N-type source and a first drain terminal well 5 heavily doped N-type well 6 are connected to the metal lead, the first heavily doped body contact P-type well 4, a first heavily doped N-type source well 5, the drain terminal of a first heavily doped N-type well 6, the first field oxide layer 14, 9, a gate and a region other than the lead of the first metal oxide layer a first polysilicon gate dielectric 10 is provided with an oxide layer 34, [0035] the low-voltage depletion type N-type metal oxide semiconductor field effect transistor 36 comprises a first doping a P-type well 3, a first P-type doped well 3 is provided 述第一P型重掺杂体接触阱4、第二源端N型重掺杂阱7 和第二漏端N型重掺杂阱8,低压增强型N型金属氧化物半导体场效应晶体管35的第一漏端N型重掺杂阱6和低压耗尽型N型金属氧化物半导体场效应晶体管36的第二源端N型重掺杂阱7之间设有第一场氧化层14,第二源端N型重掺杂阱7和第二漏端N型重掺杂阱8之间的沟道区设有第一耗尽注入层13,第二源端N型重掺杂阱7和第二漏端N型重掺杂阱8之间的沟道区上方设有第二栅氧化层11,第二栅氧化层11上方设有第二多晶硅栅极12,第一P型重掺杂体接触阱4、第二源端N型重掺杂阱7及第二漏端N型重掺杂阱8上分别连接有金属引线,第一P型重掺杂体接触阱4、第二源端N型重掺杂阱7、第二漏端N型重掺杂阱8、第一场氧化层14、第二栅氧化层11、第二多晶硅栅极12以及金属引线以外的区域设有介质氧化层;34。 Said first P-type heavily doped well body contact 4, a second source terminal of the N-type heavily doped well and the second drain terminal 7 heavily doped N-type well 8, low-voltage enhancement mode N-type metal oxide semiconductor field effect transistor 35 a first drain terminal of the N type heavily doped well 6 and the low pressure depletion type N-type metal oxide semiconductor field effect transistor of the second N-type source 36 heavily doped with a first field oxide layer 14 between the well 7, a second heavily doped source N type well and the second drain terminal 7 heavily doped N-type channel region between the well 8 is provided with a first depletion injection layer 13, a second N + source well 7 and the drain terminal of the second N-type heavily doped well over the channel region 8 is provided between the second gate oxide layer 11, over the second gate oxide layer 11 is provided with a second polysilicon gate 12, a first P-type the heavily doped well body contact 4, a second source terminal of the N-type heavily doped well and the second drain terminal 7 heavily doped N-type wells are connected to a metal wire 8, a first P-type heavily doped well body contact 4, a second heavily doped source N type well 7, the drain terminal of the second heavily doped N-type well 8, a first field oxide layer 14, a second gate oxide layer 11, polysilicon gate 12 and outside the second metal leads the dielectric oxide layer is provided with regions; 34.

[0036] 上述高压纵向双扩散金属氧化物半导体场效应晶体管37包括N型重掺杂衬底1, N型重掺杂衬底1上设有N型外延层2,N型外延层2上设有第二P型掺杂阱15,第二P型掺杂阱15上设有第二P型重掺杂体接触阱16和第三源端N型重掺杂阱17,第二P型掺杂阱15包括第三源端N型重掺杂阱17的沟道区上方设有第三栅氧化层18,第二P型掺杂阱15和第二P型重掺杂体接触阱16之间的区域设有第二场氧化层19,第三栅氧化层18和第二场氧化层19上方设有第三多晶硅栅极20,第二P型重掺杂体接触阱16、第三源端N型重掺杂阱17上连接有金属引线,第二P型重掺杂体接触阱16、第三源端N型重掺杂阱17、第二场氧化层19、第三栅氧化层18、第三多晶硅栅极20以及金属引线以外的区域设有所述介质氧化层34,N型重掺杂衬底1底部设有金属引线作为漏端电极。 [0036] The high voltage vertical double diffused metal oxide semiconductor field effect transistor 37 comprises heavily doped N-type substrate 1, the N type heavily doped N-type epitaxial layer provided on the substrate 12, provided the 2 N-type epitaxial layer a second P-doped well 15, a P-type doped second well 15 is provided with a second heavily doped P-type well 16 and the third body contact N + source well 17, a second P-type dopant heteroaryl well 15 includes a third N type heavily doped source well above the channel region 17 is provided with a third gate oxide layer 18, a second P-type doped second well 15 and P + body contact 16 of the well the second region is provided between the field oxide layer 19, over the third gate oxide layer 18 and a second field oxide layer 19 is provided with a third polysilicon gate 20, a second P-type heavily doped well body contact 16, a first three N-type heavily doped source connected to the well with a metal wire 17, the second P type well 16 is heavily doped body contact, the source terminal of the third N-type heavily doped well 17, a second field oxide layer 19, the third gate oxide layer 18, 20 and the region other than the metal wires provided with said third polysilicon gate dielectric oxide layer 34, N type heavily doped base substrate 1 is provided with a metal lead as a drain terminal electrode.

[0037] 上述中高压增强型N型横向双扩散金属氧化物半导体场效应晶体管38包括第一P型掺杂阱3,第一P型掺杂阱3上设有第一N型掺杂阱21、第四源端N型重掺杂区M和第三P型重掺杂体接触阱25,第一N型掺杂阱21设有第三漏端N型重掺杂阱23,第一N型掺杂阱21和所述源端N型重掺杂区M之间的沟道区上方设有第四栅氧化层沈,第三P型重掺杂体接触阱25和第四源端N型重掺杂阱M、第三漏端N型重掺杂阱23及沟道区以外的区域均设有场氧化层33,栅氧化层沈上方及所述第一N型掺杂阱21和第三漏端N型重掺杂阱23之间的第三场氧化层33近源一端上方设有第四多晶硅栅极27,第三P型重掺杂体接触阱25、第四源端N型重掺杂阱M及第三漏端N型重掺杂阱23上分别连接有金属引线,第三P型重掺杂体接触阱25、第四源端N型重掺杂阱对、第三漏端N型重掺杂阱23、第三场氧化层33、第四栅氧化层 [0037] The N-type high-voltage enhancement mode lateral double diffused metal oxide semiconductor field effect transistor 38 comprises a first P-type doped well 3, a first P-type doped well is provided with a first N-type doped well 21 3 a fourth heavily doped N-type source region M and a third P-type heavily doped well body contact 25, a first N-type doped well 21 is provided with a drain terminal of a third heavily doped N-type well 23, a first N type doped well over the channel region between the source 21 and the N type heavily doped region M is provided with a fourth gate oxide layer sink, the third P-type heavily doped well body contact 25 and the source of the fourth N M-type heavily doped well, the drain terminal of the third heavily doped N-type well region 23 and the channel regions are provided outside the field oxide layer 33, a gate oxide layer over the sink and the first N-type doped well 21 and the drain terminal of the third heavily doped N-type well 23 between the top of the third oxide layer 33 is provided with a fourth proximal end of the polysilicon gate 27, a third P-type heavily doped well body contact 25, a fourth source end of the N + M, and a third well-type heavily doped N drain terminal are connected to the well with a metal wire 23, third P-type heavily doped well body contact 25, the source terminal of the fourth N-type heavily doped well of , the drain terminal of the third heavily doped N-type well 23, the third oxide layer 33, a fourth gate oxide layer 沈、第四多晶硅栅极27以及所述金属引线以外的区域设有介质氧化层34。 Shen, other than the gate region 27 and the metal lead is provided with a fourth dielectric oxide layer 34 is polysilicon.

[0038] 上述中高压耗尽型N型横向双扩散金属氧化物半导体场效应晶体管39包括第一P 型掺杂阱3,第一P型掺杂阱3上设有第二N型掺杂阱22、第五源端N型重掺杂区四和第三P型重掺杂体接触阱25,第二N型掺杂阱22上设有第四漏端N型重掺杂区观第二N型掺杂阱22和第五源端N型重掺杂区四之间的沟道区设有第二耗尽注入层32,第二N型掺杂阱22和第五源端N型重掺杂区四之间的沟道区上方设有第五栅氧化层30,第三P型重掺杂体接触阱25和第五源端N型重掺杂阱四、第四漏端N型重掺杂阱观及沟道区以外的区域均设有场氧化层33,第五栅氧化层30上方及所述第二N型掺杂阱22和第四漏端N型重掺杂阱观之间的第三场氧化层33近源一端上方设有第五多晶硅栅极31,第三P型重掺 [0038] In the above-described high-voltage depletion type N-type lateral double diffused metal oxide semiconductor field effect transistor 39 comprises a first P-type doped well 3, a first P-type well doped with a second N-type doped well 3 22, a fifth heavily doped N-type source region, and a third four P-type heavily doped well body contact 25, a second N-type doping N-type drain end is provided with a fourth heavily doped region of the second concept of the well 22 N-type doped well 22 and a fifth heavily doped N-type source region a channel region provided between the four second depletion injection layer 32, second N-type doped well 22 and the fifth N-type source weight over the channel region between the doped region with four fifth gate oxide layer 30, the well body contact 25 and the fifth N-type source of the third P-type heavily doped heavily doped wells four, the drain terminal of the fourth N-type View heavily doped than the well region and the channel region of the field oxide layer 33 are provided above the fifth gate oxide layer 30 and the second N-type doped well 22 and the drain terminal of the fourth N-type heavily doped well View near the upper end of the source between the field oxide layer 33 is provided with a third polysilicon gate 31 the fifth, third P-type heavily doped

11杂体接触阱25、第五源端N型重掺杂阱四及第四漏端N型重掺杂阱观上分别连接有金属引线,第三P型重掺杂体接触阱25、第五源端N型重掺杂阱四、第四漏端N型重掺杂阱28、 第三场氧化层33、第五栅氧化层30、所第五多晶硅栅极31以及金属引线以外的区域设有介 11 hetero well body contact 25, the fifth N-type heavily doped source and a fourth drain terminal wells four N-type heavily doped metallic leads are connected to the well concept, a third P-type heavily doped well body contact 25, a first five N type heavily doped source four wells, the drain terminal of the fourth heavily doped N-type well 28, the third oxide layer 33, a fifth gate oxide layer 30, polysilicon gate 31 than the fifth and metal leads the region has a dielectric

质氧化层。 Anodized layer.

[0039] 上述低压增强型N型金属氧化物半导体场效应晶体管35、低压耗尽型N型金属氧化物半导体场效应晶体管36、中高压增强型N型横向双扩散金属氧化物半导体场效应晶体管38、中高压耗尽型N型横向双扩散金属氧化物半导体场效应晶体管39和高压纵向双扩散金属氧化物半导体场效应晶体管37之间是通过N型外延层2与第一P型掺杂阱3形成来PN结反向作用来实现自隔离。 [0039] The low-voltage enhancement mode N-type metal-oxide semiconductor field-effect transistor 35, the low pressure depletion type N-type metal oxide semiconductor field effect transistor 36, the N-type enhancement mode high voltage lateral double diffused metal oxide semiconductor field effect transistor 38 , the high-voltage depletion type N-type lateral double diffused metal oxide semiconductor field effect transistors 39 and 37 between the high voltage vertical double diffused metal oxide semiconductor field effect transistor is an N-type epitaxial layer 2 by the first P-type doped well 3 to form a PN junction isolation from the reverse effect is achieved.

[0040] 上述高压纵向双扩散金属氧化物半导体场效应晶体管37的沟道区第三栅氧化层18采用与低压增强型N型金属氧化物半导体场效应晶体管35、耗尽型N型金属氧化物半导体场效应晶体36相同的栅氧工艺;高压纵向双扩散金属氧化物半导体场效应晶体管37的两个所述第二P型掺杂阱15之间采用第二场氧化层19。 [0040] The high voltage vertical double diffused metal oxide semiconductor field effect transistor channel region 37 of the third oxide layer 18 using the gate 35, a depletion mode N-type metal oxide and the low-voltage enhancement mode N-type metal-oxide semiconductor field effect transistor the semiconductor field effect transistor gate oxide 36 in the same process; high-voltage vertical double diffused metal oxide semiconductor field effect transistor 37 of the two second P-type doped second well between the field oxide layer 19 using 15.

[0041] 实施例2 [0041] Example 2

[0042] 本发明的一种高低压集成的工艺器件的制备步骤如下: [0042] The preparation step of the present invention a high-low pressure integrated process of the device is as follows:

[0043] 首先,如图2所示,取重掺杂的N型衬底1,N型衬底1上生长所述N型外延层2。 [0043] First, taking a heavily doped N-type substrate 1, growing the N-type epitaxial layer on an N-type substrate 2 as shown in FIG. 2.

[0044] 接着,如图3所示,在N型外延层2上进行P型杂质的光刻注入,经高温退火形成低压增强型N型金属氧化物半导体场效应晶体管35、低压耗尽型N型金属氧化物半导体场效应晶体管36和中高压增强型N型横向双扩散金属氧化物半导体场效应晶体管38、中高压耗尽型N型横向双扩散金属氧化物半导体场效应晶体管39所需的第一P型掺杂阱3。 [0044] Next, as shown in FIG photolithography implanted P-type impurities in the N-type epitaxial layer 23, a low pressure enhancement mode N-type metal oxide semiconductor field effect transistor 35, a low pressure high temperature annealing depletion type N type metal-oxide semiconductor field-effect transistor 36 and N-type enhancement mode high voltage lateral double diffused metal oxide semiconductor field effect transistor 38, a depletion type N-type high voltage lateral double diffused metal oxide semiconductor field effect transistor 39 of the desired 3 a P type doped well.

[0045] 接着,如图4所示,在第一P型掺杂阱3上进行N型杂质的光刻注入,用以制作中高压增强型N型横向双扩散金属氧化物半导体场效应晶体管38和中高压耗尽型N型横向双扩散金属氧化物半导体场效应晶体管39的第一N型掺杂阱21、第二N型掺杂阱22,N型外延层2上进行P型杂质的光刻注入,用以制作所述高压纵向双扩散金属氧化物半导体场效应晶体管37的第二P型掺杂阱15,然后进行高温退火工艺。 [0045] Next, as shown in FIG. 4, the first P-type doped well photolithography implanted N-type impurities 3, used to make the high-voltage N-type enhancement mode lateral double diffused metal oxide semiconductor field effect transistor 38 and high voltage depletion type N-type lateral double diffused metal oxide semiconductor field effect transistor 39 of the first N-type doped well 21, second N-type doped well 22, a P-type impurity on the light 2 N-type epitaxial layer injection moment, the high pressure used to make vertical double diffused metal oxide semiconductor field effect transistor 37 of the second P-type doped well 15 and then subjected to high temperature annealing process.

[0046] 接着,如图5所示,进行有源区光刻,采用湿氧化工艺生长所述第一场氧化层14、 所第二场氧化层19、第三场氧化层33。 [0046] Next, as shown in FIG 5, the active region photolithography, wet oxidation process first growing the field oxide layer 14, the second field oxide layer 19, the third oxide layer 33.

[0047] 接着,如图6所示,进行N型杂质的光刻注入,形成低压耗尽型N型金属氧化物半导体场效应晶体管36和中高压耗尽型N型横向双扩散金属氧化物半导体场效应晶体管39 的第一耗尽注入层13和第二耗尽注入层32,清洗后再采用干氧化工艺生长所述第一栅氧化层9、第二栅氧化层11、第三栅氧化层18、第四栅氧化层沈和第五栅氧化层30,然后进行多晶硅的淀积和刻蚀,以形成低压增强型N型金属氧化物半导体场效应晶体管35、低压耗尽型N型金属氧化物半导体场效应晶体管36、高压纵向双扩散金属氧化物半导体场效应晶体管37和中高压增强型N型横向双扩散金属氧化物半导体场效应晶体管38、中高压耗尽型N型横向双扩散金属氧化物半导体场效应晶体管39的第一多晶硅栅极10、第二多晶硅栅极12、第三多晶硅栅极20、第四多晶硅栅极27和第五多晶硅栅极31。 [0047] Next, as shown in FIG 6, a photolithography implanted N-type impurities, a low pressure depletion type N-type metal-oxide semiconductor field-effect transistor 36 and N-type depletion mode high voltage lateral double diffused metal oxide semiconductor a first field effect transistor 39 of the depletion layer 13 and a second depletion injection injection layer 32, after cleaning by dry oxidation process growing the first gate oxide layer 9, a second gate oxide layer 11, the third gate oxide layer, 18, a fourth and a fifth gate oxide Shen gate oxide 30, polysilicon is deposited and then etched to form low-voltage enhancement mode N-type metal oxide semiconductor field effect transistor 35, a depletion-type low-voltage N-type metal oxide semiconductor field-effect transistor 36, high voltage vertical double diffused metal oxide semiconductor field effect transistor 37 and N-type enhancement mode high voltage lateral double diffused metal oxide semiconductor field effect transistor 38, a depletion type N-type high voltage lateral double diffused metal oxide semiconductor field-effect transistor 39 of the first polysilicon gate electrode 10, a second polysilicon gate electrode 12, polysilicon gate 20 of the third, fourth and fifth polysilicon gate polysilicon gate 27 31.

[0048] 然后,如图7所示,进行高浓度N型杂质的光刻注入,用以制作所述低压增强型N 型金属氧化物半导体场效应晶体管35的第一源端N型重掺杂阱5和第一漏端N型重掺杂阱6、低压耗尽型N型金属氧化物半导体场效应晶体管36的第二源端N型重掺杂阱7和第二漏端N型重掺杂阱8、高压纵向双扩散金属氧化物半导体场效应晶体管37的第三源端N 型重掺杂阱17以及中高压增强型N型横向双扩散金属氧化物半导体场效应晶体管38的第四源端N型重掺杂阱M和第三漏端N型重掺杂阱23、中高压耗尽型N型横向双扩散金属氧化物半导体场效应晶体管39的第五源端N型重掺杂阱四和第四漏端N型重掺杂阱观; 接着进行高浓度P型杂质的光刻注入,用以制作所述低压增强型N型金属氧化物半导体场效应晶体管35和低压耗尽型N型金属氧化物半导体场效应晶体管36的第一P型重掺杂体接触阱4、高 [0048] Then, as shown in FIG. 7, a photolithography implantation of high-concentration N-type impurity, used to make the low-voltage enhancement mode N-type metal-oxide semiconductor field-effect transistors of the first N-type source 35 heavily doped well 5 and a first heavily doped N-type drain terminal 6 well, low-voltage depletion type N-type metal oxide semiconductor field effect transistor source terminal of a second N-type well 36 is heavily doped drain terminal 7 and the second heavily doped N-type heteroaryl well 8, a high-pressure vertical double diffused metal oxide semiconductor field effect transistor of the third source 37 heavily doped N-type well 17 and the source of fourth enhancement type N-type high voltage lateral double diffused metal oxide semiconductor field effect transistor 38 end of the N type heavily doped well drain terminal M and a third heavily doped N-type well 23, the high-voltage depletion type N-type lateral double diffused metal oxide semiconductor field effect transistor source fifth heavily doped N-type well 39 four drain terminal and a fourth N type heavily doped well concept; followed by photolithography implantation of high-concentration P-type impurity, used to make the low-voltage enhancement mode N-type metal-oxide semiconductor field-effect transistor 35 and the low-voltage depletion type N type metal-oxide semiconductor field-effect transistor 36 of the first P-type well 4 heavily doped body contact, high 纵向双扩散金属氧化物半导体场效应晶体管37的第二P型重掺杂体接触阱16以及中高压增强型N型横向双扩散金属氧化物半导体场效应晶体管38和中高压耗尽型N型横向双扩散金属氧化物半导体场效应晶体管39的第三P型重掺杂体接触阱25 ;然后进行退火工艺,接着淀积介质氧化层34,刻蚀接触孔,蒸铝,反刻铝,形成电极后进行钝化处理。 Vertical double diffused metal oxide semiconductor field effect transistor 37 of the second P-type well 16 is heavily doped body contact and high-voltage N-type enhancement mode lateral double diffused metal oxide semiconductor field effect transistor 38 and high voltage depletion type N-type lateral double diffused metal oxide semiconductor field effect transistor 39 of the third P-type heavily doped well body contact 25; annealing process is then performed, followed by depositing a dielectric oxide layer 34, etching the contact hole, aluminum evaporation, anti-engraved aluminum, to form an electrode after passivation treatment.

[0049] 最后,如图8所示,对圆片背面减薄,进行背面金属化处理后,作为高压纵向双扩散金属氧化物半导体场效应晶体管37的漏端电极。 [0049] Finally, as shown in FIG, after thinning the back surface of the wafer, a rear surface metallization process, a high-pressure vertical double diffused metal oxide semiconductor field effect transistor 8 end of the drain electrode 37.

Claims (9)

1. 一种高低压集成的工艺器件,包括:N型重掺杂衬底(1),所述N型重掺杂衬底(1) 上设有N型外延层O),所述N型外延层(¾上设有低压增强型N型金属氧化物半导体场效应晶体管(35)、低压耗尽型N型金属氧化物半导体场效应晶体管(36)、高压纵向双扩散金属氧化物半导体场效应晶体管(37)和中高压增强型N型横向双扩散金属氧化物半导体场效应晶体管(38)、中高压耗尽型N型横向双扩散金属氧化物半导体场效应晶体管(39), 其特征在于,所述低压增强型N型金属氧化物半导体场效应晶体管(3¾、所述低压耗尽型N 型金属氧化物半导体场效应晶体管(36)和所述中高压增强型N型横向双扩散金属氧化物半导体场效应晶体管(38)、所述中高压耗尽型N型横向双扩散金属氧化物半导体场效应晶体管(39)均位于第一P型掺杂阱(3),所述低压增强型N型金属氧化物半导体 An integrated high and low pressure process of the device, comprising: N type heavily doped substrate (1), the N-type heavily doped N type epitaxial layer O is provided on the substrate (1)), the N-type an epitaxial layer (with low-voltage enhancement mode N-type metal oxide semiconductor field effect transistor (35) on ¾, low-voltage depletion type N-type metal oxide semiconductor field effect transistor (36), a high-pressure vertical double diffused metal oxide semiconductor field effect a transistor (37) and the N-type enhancement mode high voltage lateral double diffused metal oxide semiconductor field effect transistor (38), the high-voltage depletion mode N-type lateral double diffused metal oxide semiconductor field effect transistor (39), characterized in that, the low-voltage enhancement mode N-type metal oxide semiconductor field effect transistor (3¾, the low depletion type N-type metal oxide semiconductor field effect transistor (36) and the N-type enhancement mode high voltage lateral double diffused metal oxide semiconductor field effect transistor (38), said depletion type N-type high voltage lateral double diffused metal oxide semiconductor field effect transistor (39) are located on the first P-type doped well (3), the low-voltage enhancement mode N-type metal oxide semiconductor 效应晶体管(35)、所述低压耗尽型N型金属氧化物半导体场效应晶体管(36)、所述中高压增强型N 型横向双扩散金属氧化物半导体场效应晶体管(38)、所述中高压耗尽型N型横向双扩散金属氧化物半导体场效应晶体管(39)和所述高压纵向双扩散金属氧化物半导体场效应晶体管(37)之间采用自隔离结构。 Effect transistor (35), said low pressure depletion type N-type metal oxide semiconductor field effect transistor (36), the N-type enhancement mode high voltage lateral double diffused metal oxide semiconductor field effect transistor (38), in the self isolation structure between the (37) high-voltage depletion mode N-type lateral double diffused metal oxide semiconductor field effect transistor (39) and the high vertical double diffused metal oxide semiconductor field effect transistor.
2.根据权利要求1所述的高低压集成的工艺器件,其特征在于,所述低压增强型N型金属氧化物半导体场效应晶体管(3¾包括所述第一P型掺杂阱(3),所述第一P型掺杂阱(3)上设有第一P型重掺杂体接触阱G)、第一源端N型重掺杂阱(¾和第一漏端N型重掺杂阱(6),所述第一P型重掺杂体接触阱(4)和所述第一源端N型重掺杂阱(5)之间设有第一场氧化层(14),所述第一源端N型重掺杂阱(¾和所述第一漏端N型重掺杂阱(6)之间的沟道区上方设有第一栅氧化层(9),所述第一栅氧化层(9)上方设有第一多晶硅栅极(10),所述第一P型重掺杂体接触阱G)、所述第一源端N型重掺杂阱(¾及所述第一漏端N型重掺杂阱(6)上分别连接有金属引线,所述第一P型重掺杂体接触阱G)、所述第一源端N型重掺杂阱(¾、所述第一漏端N型重掺杂阱(6)、所述第一场氧化层(14)、所述第一栅氧 1 2. The integrated high and low pressure process of the device according to claim, wherein said low-voltage enhancement mode N-type metal-oxide semiconductor field effect transistor (3¾ comprising the first P-type doped well (3), the first P-type doped well has a first heavily doped P-type well body contact G) (3), a first heavily doped N-type source well (¾ drain terminal and a first heavily doped N-type well (6), the first P-type heavily doped well body contact (4) and said first N-type heavily doped source provided with a first field oxide layer (14) between the well (5), the over the channel region of said first N-type heavily doped source well (¾ drain terminal and said first heavily doped N-type well (6) provided between the first gate oxide layer (9), said first (9) above a gate oxide layer is provided with a first polysilicon gate (10), the first P-type heavily doped well body contact G), the source terminal of a first N-type heavily doped well (¾ and the drain terminal of the first N-type heavily doped well (6) are connected to the metal lead, the first P-type heavily doped well body contact G), the source terminal of a first N-type heavily doped well (¾, the drain terminal of the first N-type heavily doped well (6), the first field oxide layer (14), said first gate oxide 化层(9)、所述第一多晶硅栅极(10)以及金属引线以外的区域设有介质氧化层(34)。 Layer (9), (10) and a region other than the metal lead is provided with the first polysilicon gate dielectric oxide layer (34).
3.根据权利要求1所述的高低压集成的工艺器件,其特征在于,所述低压耗尽型N型金属氧化物半导体场效应晶体管(36)包括所述第一P型掺杂阱(3),在所述第一P型掺杂阱(3)上设有所述第一P型重掺杂体接触阱G)、第二源端N型重掺杂阱(7)和第二漏端N 型重掺杂阱(8),所述低压增强型N型金属氧化物半导体场效应晶体管(3¾的所述第一漏端N型重掺杂阱(6)和所述低压耗尽型N型金属氧化物半导体场效应晶体管(36)的所述第二源端N型重掺杂阱(7)之间设有所述第一场氧化层(14),所述第二源端N型重掺杂阱(7)和所述第二漏端N型重掺杂阱(8)之间的沟道区设有第一耗尽注入层(13),所述第二源端N型重掺杂阱(7)和所述第二漏端N型重掺杂阱(8)之间的沟道区上方设有第二栅氧化层(11),所述第二栅氧化层(11)上方设有第二多晶硅栅极(12),所述第一P型重掺杂体 1 according to the high and low pressure process of the integrated device according to claim, wherein said low pressure depletion type N-type metal oxide semiconductor field effect transistor (36) comprises a first P-type doped well (3 ), the first P-type doped well (provided with 3) of the first P-type heavily doped well body contact G), a second N-type heavily doped source well (7) and a second drain end of the N type heavily doped well (8), the low-voltage enhancement mode N-type metal-oxide semiconductor field effect transistor (3¾ drain terminal of a first heavily doped N-type well (6) and the low pressure depletion type It provided the N-type metal oxide semiconductor field effect transistor (36) of a second N + source well (7) between said first field oxide layer (14), the second source terminal N type heavily doped channel well region (7) and the drain terminal of the second N-type heavily doped well (8) is provided between the first depletion injection layer (13), said second N-type source the heavily doped wells (7) and said second heavily doped N-type drain terminal over the channel region between the well (8) is provided with a second gate oxide layer (11), the second gate oxide layer (11 ) provided above the second polysilicon gate electrode (12), said first heavily doped P-type body 触阱G)、所述第二源端N型重掺杂阱(7)及所述第二漏端N型重掺杂阱(8)上分别连接有金属引线,所述第一P型重掺杂体接触阱G)、所述第二源端N型重掺杂阱(7)、所述第二漏端N型重掺杂阱(8)、所述第一场氧化层(14)、所述第二栅氧化层(11)、所述第二多晶硅栅极(12)以及金属引线以外的区域设有介质氧化层(34)。 Touch trap G), the source terminal of the second N-type heavily doped well (7) and a drain terminal of the second N-type heavily doped well (8) are connected to the metal lead, the first P-type heavily doped well body contact G), the source terminal of the second N-type heavily doped well (7), the drain terminal of the second N-type heavily doped well (8), said first field oxide layer (14) , the second gate oxide layer (11), the second polysilicon gate electrode (12) and a region other than the dielectric oxide layer is provided with a metal lead (34).
4.根据权利要求1所述的高低压集成的工艺器件,其特征在于,所述高压纵向双扩散金属氧化物半导体场效应晶体管(37)包括所述N型重掺杂衬底(1),所述N型重掺杂衬底(1)上设有N型外延层O),所述N型外延层(¾上设有第二P型掺杂阱(15),所述第二P型掺杂阱(1¾上设有第二P型重掺杂体接触阱(16)和第三源端N型重掺杂阱(17),所述第二P型掺杂阱(1¾包括所述第三源端N型重掺杂阱(17)的沟道区上方设有第三栅氧化层(18),所述第二P型掺杂阱(1¾和所述第二P型重掺杂体接触阱(16)之间的区域设有第二场氧化层(19),所述第三栅氧化层(18)和所述第二场氧化层(19)上方设有第三多晶硅栅极(20),所述第二P型重掺杂体接触阱(16)、所述第三源端N型重掺杂阱(17)上连接有金属引线,所述第二P型重掺杂体接触阱(16)、所述第三源端N型重掺杂阱(17)、所述第二 1 according to the high and low pressure process of the integrated device according to claim, wherein said high voltage vertical double diffused metal oxide semiconductor field effect transistor (37) comprises a heavily doped N-type substrate (1), the N type heavily doped N type epitaxial layer O is provided on the substrate (1)), the N-type epitaxial layer (second P-type doped well is provided (on ¾ 15), said second P-type doped well (provided with the second P-type well 1¾ heavily doped body contact (16) and a third heavily doped source N type well (17), said second P-type doped well (including the 1¾ a third heavily doped source N type well (17) over the channel region with a third gate oxide layer (18), said second P-type doped well (1¾ and said second heavily doped P-type the second region is provided with a field oxide layer (19) contacting between the well (16), the third gate oxide layer (18) and said second field oxide layer (19) is provided above the third polysilicon a gate (20), said second heavily doped body contact P-type well (16), said third heavily doped N-type source connected to the well with a metal wire (17), said second P type heavily contacting the doped well (16), said third heavily doped source N type well (17), the second 场氧化层(19)、所述第三栅氧化层(18)、所述第三多晶硅栅极00)以及金属引线以外的区域设有所述介质氧化层(34),所述N型重掺杂衬底(1)底部设有金属引线作为漏端电极。 Field oxide region (19), the third gate oxide layer (18), said third polysilicon gate electrode 00) and the metal lead is provided outside of said dielectric oxide layer (34), the N-type a heavily doped substrate (1) is provided with a bottom drain terminal metal lead electrodes.
5.根据权利要求1所述的高低压集成的工艺器件,其特征在于,所述中高压增强型N型横向双扩散金属氧化物半导体场效应晶体管(38)包括第一P型掺杂阱(3),所述第一P型掺杂阱C3)上设有第一N型掺杂阱(21)、第四源端N型重掺杂区04)和第三P型重掺杂体接触阱(25),所述第一N型掺杂阱上设有第三漏端N型重掺杂阱(23),所述第一N型掺杂阱和所述源端N型重掺杂区04)之间的沟道区上方设有第四栅氧化层(¾),所述第三P型重掺杂体接触阱0¾和所述第四源端N型重掺杂阱(M)、所述第三漏端N型重掺杂阱03)及沟道区以外的区域均设有场氧化层(33),栅氧化层06)上方及所述第一N 型掺杂阱和所述第三漏端N型重掺杂阱之间的所述第三场氧化层(3¾近源一端上方设有第四多晶硅栅极(27),所述第三P型重掺杂体接触阱(25)、所述第四源端N型重掺杂阱04)及所述第三漏端N型 1 according to the high and low pressure process of the integrated device according to claim, wherein said N-type enhancement mode high voltage lateral double diffused metal oxide semiconductor field effect transistor (38) comprises a first P-type doped well ( 3), the first P-type doped well C3) is provided with a first N-type doped well (21), a fourth heavily doped N-type source region 04) and a third P-type heavily doped body contact on well (25), provided with a third drain terminal of the first N-type on a heavily doped N-type well doped well (23), the first N-type doped well and the heavily doped N-type source over the channel region between the region 04) is provided with a fourth gate oxide layer (¾), and contacting said fourth well 0¾ source of the third N-type heavily doped P-type heavily doped well (M) the drain terminal of the third N-type heavily doped well 03) and the other region has a channel region of the field oxide layer (33), a gate oxide layer 06) and above the first N-type doped well and the a third well between the field oxide layer over the proximal end (3¾ drain terminal of said third heavily doped N-type polysilicon gate with a fourth (27), said third heavily doped P-type body a contact well (25), said fourth heavily doped source N type well 04) and the drain terminal of the third N-type 掺杂阱上分别连接有金属引线,所述第三P型重掺杂体接触阱0¾、所述第四源端N型重掺杂阱04)、所述第三漏端N型重掺杂阱03)、 所述第三场氧化层(33)、所述第四栅氧化层(沈)、所述第四多晶硅栅极(XT)以及所述金属引线以外的区域设有介质氧化层(34)。 Doped metal leads are connected, said third heavily doped body contact P-type well 0¾, said fourth heavily doped source N type well 04) on the well, the drain terminal of the third N-type heavily doped well 03), the third oxide layer (33), the fourth gate oxide layer (Shen), said fourth gate polysilicon (XT) and the region outside the metal lead is provided with a dielectric oxide layer (34).
6.根据权利要求1所述的高低压集成的工艺器件,其特征在于,所述中高压耗尽型N型横向双扩散金属氧化物半导体场效应晶体管(39)包括第一P型掺杂阱(3),所述第一P型掺杂阱C3)上设有第二N型掺杂阱(22)、第五源端N型重掺杂区09)和第三P型重掺杂体接触阱(25),所述第二N型掺杂阱0¾上设有第四漏端N型重掺杂区(¾),所述第二N型掺杂阱0¾和所述第五源端N型重掺杂区09)之间的沟道区设有第二耗尽注入层(32), 所述第二N型掺杂阱0¾和所述第五源端N型重掺杂区09)之间的沟道区上方设有第五栅氧化层(30),所述第三P型重掺杂体接触阱0¾和所述第五源端N型重掺杂阱(¾)、所述第四漏端N型重掺杂阱08)及沟道区以外的区域均设有场氧化层(33),第五栅氧化层(30)上方及所述第二N型掺杂阱0¾和所述第四漏端N型重掺杂阱08)之间的所述第三场氧化层(3¾近源一端上 1 according to the high and low pressure process of the integrated device according to claim, wherein said N-type depletion mode high voltage lateral double diffused metal oxide semiconductor field effect transistor (39) comprises a first P-type doped well (3), the first P-type doped well C3) with a second N-type doped well (22), a fifth N + source region 09), and a third heavily doped P-type body a contact well (25), is provided on the second N-type doped well 0¾ drain terminal of the fourth N-type heavily doped region (¾), said second N-type doped well and said fifth source 0¾ a channel region between N + region 09) is provided with a second depletion implant layer (32), said second N-type doped well 0¾ and said fifth heavily doped N-type source region 09 over the channel region between) provided with a fifth gate oxide layer (30), and contacting said fifth well 0¾ source of the third N-type heavily doped P-type heavily doped well (¾), the the drain terminal of said fourth N-type heavily doped than 08) and the channel region of the well region has a field oxide layer (33), above the fifth gate oxide layer (30) and the second N-type doped well 0¾ one end of said drain terminal and said fourth heavily doped N-type well 08) between the third oxide layer (3¾ proximal 设有第五多晶硅栅极(31),所述第三P型重掺杂体接触阱(25)、所述第五源端N型重掺杂阱09)及所述第四漏端N型重掺杂阱08)上分别连接有金属引线,所述第三P型重掺杂体接触阱(25)、所述第五源端N型重掺杂阱(¾)、所述第四漏端N型重掺杂阱08)、所述第三场氧化层(3¾、所述第五栅氧化层(30)、所述第五多晶硅栅极(31)以及所述金属引线以外的区域设有介质氧化层(34)。 Is provided with a fifth polysilicon gate (31), said third body contact P + well (25), said fifth heavily doped source N type well 09) and the fourth drain end heavily doped N-type well 08) are connected to the metal leads, said third P-type heavy body contact well (25) doped, the source end of the fifth N-type heavily doped well (¾), said first four end N + drain well 08), the third oxide layer (3¾, the fifth gate oxide layer (30), said fifth polysilicon gate (31) and said metal leads other than the region provided with a dielectric oxide layer (34).
7.根据权利要求1所述的高低压集成的工艺器件,其特征在于,所述低压增强型N型金属氧化物半导体场效应晶体管(3¾、所述低压耗尽型N型金属氧化物半导体场效应晶体管(36)、所述中高压增强型N型横向双扩散金属氧化物半导体场效应晶体管(38)、所述中高压耗尽型N型横向双扩散金属氧化物半导体场效应晶体管(39)和所述高压纵向双扩散金属氧化物半导体场效应晶体管(37)之间通过所述N型外延层(¾与所述第一P型掺杂阱(3)形成PN结反向作用。 1 according to the high and low pressure process of the integrated device according to claim, wherein said low-voltage enhancement mode N-type metal-oxide semiconductor field effect transistor (3¾, the low depletion type N-type metal oxide semiconductor field effect transistor (36), the N-type enhancement mode high voltage lateral double diffused metal oxide semiconductor field effect transistor (38), said depletion type N-type high voltage lateral double diffused metal oxide semiconductor field effect transistor (39) and the high vertical double diffused metal oxide semiconductor field effect transistor between the PN junction reverse action (37) is formed by the N-type epitaxial layer (¾ of the first P-type doped well (3).
8.根据权利要求4所述的高低压集成的工艺器件,其特征在于,所述高压纵向双扩散金属氧化物半导体场效应晶体管(37)的沟道区第三栅氧化层(18)采用与所述低压增强型N型金属氧化物半导体场效应晶体管(35)、耗尽型N型金属氧化物半导体场效应晶体(36) 相同的栅氧工艺;所述高压纵向双扩散金属氧化物半导体场效应晶体管(37)的两个所述第二P型掺杂阱(1¾之间采用第二场氧化层(19)。 According to claim 4, wherein the high-low pressure integrated process of the device, characterized in that the high-pressure vertical double diffused metal oxide semiconductor field effect transistor (37) a third channel region of the gate oxide layer (18) Using the low-voltage enhancement mode N-type metal-oxide semiconductor field effect transistor (35), a depletion mode N-type metal oxide semiconductor field effect transistor (36) of the same gate oxide process; the high-voltage vertical double diffused metal oxide semiconductor field the second P-type two-effect transistor (37) doped well (second field oxide layer (19) employed between 1¾.
9. 一种用于如权利要求1所述的高低压集成的工艺器件结构的制备方法,其特征在于,它包括以下制备步骤:首先,取所述重掺杂的N型衬底(1),所述N型衬底(1)上生长所述N型外延层O),接着在所述N型外延层⑵上进行P型杂质的光刻注入,经高温退火形成所述低压增强型N型金属氧化物半导体场效应晶体管(3¾、所述低压耗尽型N型金属氧化物半导体场效应晶体管(36)和所述中高压增强型N型横向双扩散金属氧化物半导体场效应晶体管(38)、所述中高压耗尽型N型横向双扩散金属氧化物半导体场效应晶体管(39)所需的所述第一P型掺杂阱(3);接着在所述第一P型掺杂阱C3)上进行N型杂质的光刻注入,用以制作所述中高压增强型N型横向双扩散金属氧化物半导体场效应晶体管(38)和所述中高压耗尽型N型横向双扩散金属氧化物半导体场效应晶体管(39)的第一N型掺 A method for preparing a high or low pressure according to the integrated process device structure as claimed in claim, characterized in that it comprises the following preparation steps: firstly, taking the heavily doped N-type substrate (1) the growth of the upper N-type substrate (1) N-type epitaxial layer O), followed by photolithography implanted P-type impurities in the N-type epitaxial layer ⑵, is formed by the low temperature annealing enhancement N type metal-oxide semiconductor field effect transistor (3¾, the low depletion type N-type metal oxide semiconductor field effect transistor (36) and the N-type enhancement mode high voltage lateral double diffused metal oxide semiconductor field effect transistor (38 ), the required high pressure of the first P-type depletion type N-type lateral double diffused metal oxide semiconductor field effect transistor (39) doped well (3); followed by the first P-type doped photolithography on the N-type impurities implanted) well C3, used to make the high-voltage N-type enhancement mode lateral double diffused metal oxide semiconductor field effect transistor (38) and said depletion type high voltage lateral double diffused N-type metal oxide semiconductor field effect transistor (39) of the first N-type doping 阱(21)、第二N型掺杂阱(22),所述N型外延层(¾上进行P型杂质的光刻注入,用以制作所述高压纵向双扩散金属氧化物半导体场效应晶体管(37)的第二P型掺杂阱(15),然后进行高温退火工艺;接着进行有源区光刻,采用湿氧化工艺生长所述第一场氧化层(14)、所述第二场氧化层(19)、所述第三场氧化层(33),接着进行N型杂质的光刻注入,形成所述低压耗尽型N型金属氧化物半导体场效应晶体管(36)和所述中高压耗尽型N型横向双扩散金属氧化物半导体场效应晶体管(39)的所述第一耗尽注入层(1¾和第二耗尽注入层(32),清洗后再采用干氧化工艺生长所述第一栅氧化层(9)、所述第二栅氧化层(11)、所述第三栅氧化层(18)、所述第四栅氧化层06)和所述第五栅氧化层(30),然后进行多晶硅的淀积和刻蚀,以形成所述低压增强型N型金属氧化物半导体场效应 Well (21), a second N-type doped well (22), the N-type epitaxial layer (P type impurities implanted photolithography on ¾, used to make the high-pressure vertical double diffused metal oxide semiconductor field effect transistor (37) a second P-type doped well (15), then subjected to high temperature annealing process; active region followed by photolithography using a wet oxidation process of growing the first field oxide layer (14), the second field an oxide layer (19), said third oxide layer (33), followed by photolithography implanted N-type impurities, are formed the low pressure depletion type N-type metal oxide semiconductor field effect transistor (36) and in the the high-voltage depletion type N-type lateral double diffused metal oxide semiconductor field effect transistor (39) of the first depletion injection layer (1¾ injection and the second depletion layer (32), after cleaning by dry oxidation process growth said first gate oxide layer (9), the second gate oxide layer (11), the third gate oxide layer (18), the fourth gate oxide layer 06) and the fifth gate oxide ( 30), followed by deposition of polysilicon and etching to form the low-voltage enhancement mode N-type metal oxide semiconductor field effect 体管(3¾、所述低压耗尽型N型金属氧化物半导体场效应晶体管(36)、所述高压纵向双扩散金属氧化物半导体场效应晶体管(37)和所述中高压增强型N型横向双扩散金属氧化物半导体场效应晶体管(38)、所述中高压耗尽型N型横向双扩散金属氧化物半导体场效应晶体管(39)的所述第一多晶硅栅极(10)、所述第二多晶硅栅极(12)、所述第三多晶硅栅极(20)、所述第四多晶硅栅极(XT)和所述第五多晶硅栅极(31);然后,进行高浓度N型杂质的光刻注入,用以制作所述低压增强型N型金属氧化物半导体场效应晶体管(3¾的所述第一源端N型重掺杂阱(¾和所述第一漏端N型重掺杂阱(6)、所述低压耗尽型N型金属氧化物半导体场效应晶体管(36)的所述第二源端N型重掺杂阱(7)和所述第二漏端N型重掺杂阱(8)、所述高压纵向双扩散金属氧化物半导体场效应晶体管(37)的所 Transistor (3¾, the low depletion type N-type metal oxide semiconductor field effect transistor (36), the high-pressure vertical double diffused metal oxide semiconductor field effect transistor (37) and said high voltage lateral enhancement mode N-type double diffused metal oxide semiconductor field effect transistor (38), the high-voltage depletion type N-type lateral double diffused metal oxide semiconductor field effect transistor (39) a first polysilicon gate (10), the said second polysilicon gate electrode (12), said third polysilicon gate (20), said fourth gate polysilicon (XT) and the fifth polysilicon gate (31) ; then, photolithography implantation of high-concentration N-type impurity, used to make the low-voltage enhancement mode N-type metal oxide semiconductor field effect transistor (3¾ a first heavily doped N-type source well (and the ¾ the drain terminal of said first heavily doped N-type well (6), said low-voltage depletion type N-type metal oxide semiconductor field effect transistor (36) of a second N + source well (7) and the drain terminal of the second N-type heavily doped well (8), the longitudinal direction of the high-pressure double diffused metal oxide semiconductor field effect transistor (37) 第三源端N型重掺杂阱(17)以及所述中高压增强型N型横向双扩散金属氧化物半导体场效应晶体管(38)的所述第四源端N型重掺杂阱04)和第三所述漏端N 型重掺杂阱(23)、所述中高压耗尽型N型横向双扩散金属氧化物半导体场效应晶体管(39) 的所述第五源端N型重掺杂阱09)和所述第四漏端N型重掺杂阱08);接着进行高浓度P型杂质的光刻注入,用以制作所述低压增强型N型金属氧化物半导体场效应晶体管(35) 和所述低压耗尽型N型金属氧化物半导体场效应晶体管(36)的所述第一P型重掺杂体接触阱G)、所述高压纵向双扩散金属氧化物半导体场效应晶体管(37)的所述第二P型重掺杂体接触阱(16)以及所述中高压增强型N型横向双扩散金属氧化物半导体场效应晶体管(38)和所述中高压耗尽型N型横向双扩散金属氧化物半导体场效应晶体管(39)的所述第三P型重掺杂体接触阱 A third heavily doped source N type well (17) and said high-voltage N-type enhancement mode lateral double diffused metal oxide semiconductor field effect transistor (38) a fourth heavily doped source N type well 04) and the drain terminal of the third N-type heavily doped well (23), the high-voltage depletion type N-type lateral double diffused metal oxide semiconductor field effect transistor (39) a fifth N-type heavily doped source hetero-well 09) and the drain terminal of said fourth heavily doped N-type well 08); followed by photolithography injection of high-concentration P-type impurity for making the low-voltage enhancement mode N-type metal-oxide semiconductor field effect transistor ( the 35) and the low pressure depletion type N-type metal oxide semiconductor field effect transistor (36) of the first P-type heavily doped well body contact G), said high voltage vertical double diffused metal oxide semiconductor field effect transistor the (37) a second body contact P + well (16) and the N-type enhancement mode high voltage lateral double diffused metal oxide semiconductor field effect transistor (38) and said high voltage depletion type N contacting the well type lateral double diffused metal oxide semiconductor field effect transistor (39) of the third P-type heavily doped 0¾ ;然后进行退火工艺,接着淀积介质氧化层(34),刻蚀接触孔, 蒸铝,反刻铝,形成电极后进行钝化处理;最后,对圆片背面减薄,进行背面金属化处理后,作为所述高压纵向双扩散金属氧化物半导体场效应晶体管(37)的漏端电极。 0¾; annealing process is then performed, followed by depositing a dielectric oxide layer (34), etching the contact hole, aluminum evaporation, passivated aluminum engraved After the reaction, an electrode is formed; Finally, the back surface of the wafer is thinned, back-side metallization after the treatment, as the high voltage electrode longitudinal drain terminal double diffused metal oxide semiconductor field effect transistor (37).
CN2010102657999A 2010-08-30 2010-08-30 High-voltage and low-voltage integrated process device and preparation method thereof CN102386185A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2010102657999A CN102386185A (en) 2010-08-30 2010-08-30 High-voltage and low-voltage integrated process device and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2010102657999A CN102386185A (en) 2010-08-30 2010-08-30 High-voltage and low-voltage integrated process device and preparation method thereof

Publications (1)

Publication Number Publication Date
CN102386185A true CN102386185A (en) 2012-03-21

Family

ID=45825440

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2010102657999A CN102386185A (en) 2010-08-30 2010-08-30 High-voltage and low-voltage integrated process device and preparation method thereof

Country Status (1)

Country Link
CN (1) CN102386185A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103426880A (en) * 2013-05-22 2013-12-04 苏州博创集成电路设计有限公司 Complementary metal-oxide-semiconductor transistor (CMOS) type high voltage and low voltage integrated technological device structure and method for manufacturing same
CN104347618A (en) * 2013-08-09 2015-02-11 英飞凌科技奥地利有限公司 Electronic Component and Method
CN105652176A (en) * 2016-03-08 2016-06-08 上海华虹宏力半导体制造有限公司 Method and device for testing number of guard rings
WO2018040973A1 (en) * 2016-08-31 2018-03-08 无锡华润上华科技有限公司 Component integrated with depletion-mode junction field-effect transistor and method for manufacturing component

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6429481B1 (en) * 1997-11-14 2002-08-06 Fairchild Semiconductor Corporation Field effect transistor and method of its manufacture
US20050035398A1 (en) * 1999-05-25 2005-02-17 Williams Richard K. Trench MOSFET with recessed clamping diode
CN101552274A (en) * 2004-06-30 2009-10-07 先进模拟科技公司;先进模拟科技(香港)有限公司 Semiconductor device and manufacturing and processing method thereof
CN101694850A (en) * 2009-10-16 2010-04-14 电子科技大学; Carrier-storing grooved gate IGBT with P-type floating layer

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6429481B1 (en) * 1997-11-14 2002-08-06 Fairchild Semiconductor Corporation Field effect transistor and method of its manufacture
US20050035398A1 (en) * 1999-05-25 2005-02-17 Williams Richard K. Trench MOSFET with recessed clamping diode
CN101552274A (en) * 2004-06-30 2009-10-07 先进模拟科技公司;先进模拟科技(香港)有限公司 Semiconductor device and manufacturing and processing method thereof
CN101694850A (en) * 2009-10-16 2010-04-14 电子科技大学; Carrier-storing grooved gate IGBT with P-type floating layer

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103426880A (en) * 2013-05-22 2013-12-04 苏州博创集成电路设计有限公司 Complementary metal-oxide-semiconductor transistor (CMOS) type high voltage and low voltage integrated technological device structure and method for manufacturing same
CN104347618A (en) * 2013-08-09 2015-02-11 英飞凌科技奥地利有限公司 Electronic Component and Method
US9620472B2 (en) 2013-08-09 2017-04-11 Infineon Technologies Austria Ag Method of manufacturing an electronic component
CN104347618B (en) * 2013-08-09 2018-01-19 英飞凌科技奥地利有限公司 Electronic unit and method
CN105652176A (en) * 2016-03-08 2016-06-08 上海华虹宏力半导体制造有限公司 Method and device for testing number of guard rings
CN105652176B (en) * 2016-03-08 2018-06-05 上海华虹宏力半导体制造有限公司 A kind of test method and device of protection ring quantity
WO2018040973A1 (en) * 2016-08-31 2018-03-08 无锡华润上华科技有限公司 Component integrated with depletion-mode junction field-effect transistor and method for manufacturing component

Similar Documents

Publication Publication Date Title
US9673219B2 (en) Vertical semiconductor device with thinned substrate
TWI557884B (en) Monolithic microwave integrated circuit and method of forming
US20110241170A1 (en) Monolithic semiconductor switches and method for manufacturing
CN101807543A (en) Single die output power stage using trench-gate low-side and ldmos high-side mosfets, structure and method
JP2004319808A (en) Mis field effect transistor and its manufacturing method
CN101859769B (en) Semiconductor device and method for fabricating the same
CN101771049A (en) Real chip level package power metal oxide semiconductor field effect tube based on a bottom source electrode metal oxide semiconductor field effect tube
CN101471380A (en) Lateral double difused metal oxide semiconductor transistor and method for manufacturing the same
JP2005159349A (en) Metal-oxide-film semiconductor device formed in silicon-on-insulator
US8022446B2 (en) Integrated Schottky diode and power MOSFET
CN105655390A (en) Split gate field effect transistor
CN102656697B (en) The semiconductor device
US10079230B2 (en) Double-sided vertical semiconductor device with thinned substrate
CN101752421A (en) Semiconductor device and method for manufacturing the same
US8030705B2 (en) Semiconductor device and method of fabricating the same
CN102082174B (en) High voltage devices and methods for forming the high voltage devices
CN102130168A (en) Isolated LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and manufacturing method thereof
CN102971855A (en) Semiconductor device and method for manufacturing same
CN102097473B (en) The semiconductor device
CN101872724A (en) Manufacturing method of super junction MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor)
CN101510561B (en) Ultra-junction longitudinal bilateral diffusion metal oxide semiconductor tube
CN101026191A (en) Semiconductor device and method of manufacturing the same
US8338872B2 (en) Electronic device with capcitively coupled floating buried layer
US8704300B1 (en) Semiconductor device and fabricating method thereof
KR101593308B1 (en) Vertical Power MOSFET and Methods for Forming the Same

Legal Events

Date Code Title Description
C06 Publication
C10 Entry into substantive examination
C20 Patent right or utility model deemed to be abandoned or is abandoned