CN102386185A - High-voltage and low-voltage integrated process device and preparation method thereof - Google Patents
High-voltage and low-voltage integrated process device and preparation method thereof Download PDFInfo
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- CN102386185A CN102386185A CN2010102657999A CN201010265799A CN102386185A CN 102386185 A CN102386185 A CN 102386185A CN 2010102657999 A CN2010102657999 A CN 2010102657999A CN 201010265799 A CN201010265799 A CN 201010265799A CN 102386185 A CN102386185 A CN 102386185A
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Abstract
The invention discloses a high-voltage and low-voltage integrated process device and a preparation method thereof. The process device comprises low-voltage enhancement and depletion N-type metal oxide semiconductor field effect transistors, a high-voltage longitudinal double-diffusion metal oxide semiconductor field effect transistor, and medium-voltage and high-voltage enhancement and depletion N-type transverse double-diffusion metal oxide semiconductor field effect transistors. The preparation method comprises the following steps of: making an N-type epitaxial layer on an N-type heavy doped substrate, making different P-type doped wells on the N-type epitaxial layer, simultaneously making N-type voltage tolerance regions of the medium-voltage and the high-voltage enhancement and depletion N-type transverse double-diffusion metal oxide semiconductor field effect transistors on the P-type doped wells, and performing source and drain implantation on the P-type doped wells and the N-type voltage tolerance regions. The process device is an integrated longitudinal power device based on an epitaxial material, and has high process integration and reliability.
Description
Technical field
The present invention relates to the technical field of semiconductor device, be specifically related to integrated technology device architecture of a kind of high-low pressure and preparation method thereof, be applicable to power management, the smart-power IC design in fields such as automotive electronics.
Background technology
Power integrated circuit is high voltage power device and signal processing system and peripheral structure circuit, protective circuit, and testing circuits etc. are integrated on the same chip; Reduced the parts number in the system; The number of interconnection and solder joint number not only can improve the reliability of system, stability; And power consumption, volume weight and the cost of system have been subtracted.Power integrated circuit appears at the later stage seventies the earliest; But after the nineties, just get into the practical stage; Mainly need to solve two technical difficult problems: first, need the input impedance height, mos field effect transistor (MOS) the type power device of low driving power consumption; Second; Need to solve high-low voltage device and be integrated in structural design and technologic problem; Not only need guarantee that low pressure and high tension apparatus can both operate as normal but also do not influence each other; Higher reliability is arranged, and palpus ability compatible existing low pressure CMOS complementary metal-oxide-semiconductor field-effect transistor (CMOS) technology is prone to industrialization simultaneously.
The present invention proposes integrated technology device of a kind of high-low pressure and preparation method thereof; Have simplicity of design, reliability height, can avoid cmos device to have the advantages such as risk of Latch-Up (latch-up); Be applicable to power management, the smart-power IC design of the inside, fields such as automotive electronics.。
Summary of the invention
For overcoming the difference of prior art, the object of the present invention is to provide integrated technology device of a kind of high-low pressure and preparation method thereof.Be applicable to power management, the smart-power IC design of the inside, fields such as automotive electronics.
The integrated technology device architecture of high-low pressure according to the invention adopts following technical scheme:
The technology device that a kind of high-low pressure is integrated; Comprise: N type heavy doping substrate; Said N type substrate is provided with N type epitaxial loayer; Said N type epitaxial loayer is provided with low pressure enhancement mode N type metal oxide semiconductor field-effect transistor, low pressure depletion type N type metal oxide semiconductor field-effect transistor, high pressure longitudinal double diffusion metal oxide semiconductor field effect transistor and mesohigh enhancement mode N type lateral double diffusion metal oxide semiconductor field-effect transistor, mesohigh depletion type N type lateral double diffusion metal oxide semiconductor field-effect transistor; It is characterized in that; Said low pressure enhancement mode N type metal oxide semiconductor field-effect transistor, said low pressure depletion type N type metal oxide semiconductor field-effect transistor and said mesohigh enhancement mode N type lateral double diffusion metal oxide semiconductor field-effect transistor, said mesohigh depletion type N type lateral double diffusion metal oxide semiconductor field-effect transistor all are positioned at a P type dopant well, adopt the self-isolation structure between said low pressure enhancement mode N type metal oxide semiconductor field-effect transistor, said low pressure depletion type N type metal oxide semiconductor field-effect transistor, said mesohigh enhancement mode N type lateral double diffusion metal oxide semiconductor field-effect transistor, said mesohigh depletion type N type lateral double diffusion metal oxide semiconductor field-effect transistor and the said high pressure longitudinal double diffusion metal oxide semiconductor field effect transistor.
Preferably; Said low pressure enhancement mode N type metal oxide semiconductor field-effect transistor comprises a said P type dopant well; A said P type dopant well is provided with a P type heavy doping body contact trap, the first source end N type heavy doping trap and the first drain terminal N type heavy doping trap; Be provided with first field oxide between said P type heavy doping body contact trap and the said first source end N type heavy doping trap; Channel region top between said first source end N type heavy doping trap and the said first drain terminal N type heavy doping trap is provided with first grid oxide layer, and said first grid oxide layer top is provided with first polysilicon gate.Be connected with metal lead wire respectively on said a P type heavy doping body contact trap, the said first source end N type heavy doping trap and the said first drain terminal N type heavy doping trap, said P type heavy doping body contact trap, the said first source end N type heavy doping trap, the said first drain terminal N type heavy doping trap, said first field oxide, said first grid oxide layer, said first polysilicon gate and the zone beyond the metal lead wire are provided with the medium oxide layer.
Preferably; Said low pressure depletion type N type metal oxide semiconductor field-effect transistor comprises a said P type dopant well; On a said P type dopant well, be provided with said a P type heavy doping body contact trap, the second source end N type heavy doping trap and the second drain terminal N type heavy doping trap; Be provided with said first field oxide between the said second source end N type heavy doping trap of the said first drain terminal N type heavy doping trap of said low pressure enhancement mode N type metal oxide semiconductor field-effect transistor and said low pressure depletion type N type metal oxide semiconductor field-effect transistor; Channel region between said second source end N type heavy doping trap and the said second drain terminal N type heavy doping trap is provided with first and exhausts implanted layer; Channel region top between said second source end N type heavy doping trap and the said second drain terminal N type heavy doping trap is provided with second gate oxide; Said second gate oxide top is provided with second polysilicon gate; Be connected with metal lead wire respectively on said a P type heavy doping body contact trap, the said second source end N type heavy doping trap and the said second drain terminal N type heavy doping trap, said P type heavy doping body contact trap, the said second source end N type heavy doping trap, the said second drain terminal N type heavy doping trap, said first field oxide, said second gate oxide, said second polysilicon gate and the zone beyond the metal lead wire are provided with the medium oxide layer.
Preferably; Said high pressure longitudinal double diffusion metal oxide semiconductor field effect transistor comprises said N type heavy doping substrate; Said N type heavy doping substrate is provided with N type epitaxial loayer; Said N type epitaxial loayer is provided with the 2nd P type dopant well; Said the 2nd P type dopant well is provided with the 2nd P type heavy doping body contact trap and the 3rd source end N type heavy doping trap; Said the 2nd P type dopant well comprises that the channel region top of said the 3rd source end N type heavy doping trap is provided with the 3rd gate oxide; Zone between said the 2nd P type dopant well and said the 2nd P type heavy doping body contact trap is provided with second field oxide, and said the 3rd gate oxide and said second field oxide top are provided with the 3rd polysilicon gate, is connected with metal lead wire on said the 2nd P type heavy doping body contact trap, said the 3rd source end N type heavy doping trap; Said the 2nd P type heavy doping body contact trap, said the 3rd source end N type heavy doping trap, said second field oxide, said the 3rd gate oxide, said the 3rd polysilicon gate and the zone beyond the metal lead wire are provided with said medium oxide layer, and said N type heavy doping substrate bottom is provided with metal lead wire as the drain terminal electrode.
Preferably; Said mesohigh enhancement mode N type lateral double diffusion metal oxide semiconductor field-effect transistor comprises a P type dopant well; A said P type dopant well is provided with a N type dopant well, the 4th source end N type heavily doped region contacts trap with the 3rd P type heavy doping body; A said N type dopant well is provided with the 3rd drain terminal N type heavy doping trap; Channel region top between a said N type dopant well and the said source end N type heavily doped region is provided with the 4th gate oxide; Said the 3rd P type heavy doping body contact trap and the zone beyond said the 4th source end N type heavy doping trap, said the 3rd drain terminal N type heavy doping trap and the channel region are equipped with field oxide; One end top, the nearly source of said the 3rd field oxide between gate oxide top and a said N type dopant well and said the 3rd drain terminal N type heavy doping trap is provided with the 4th polysilicon gate; Be connected with metal lead wire respectively on the said contact of the 3rd P type heavy doping body trap, said the 4th source end N type heavy doping trap and said the 3rd drain terminal N type heavy doping trap, said the 3rd P type heavy doping body contact trap, said the 4th source end N type heavy doping trap, said the 3rd drain terminal N type heavy doping trap, said the 3rd field oxide, said the 4th gate oxide, said the 4th polysilicon gate and the zone beyond the said metal lead wire are provided with the medium oxide layer.
Preferably; Said mesohigh depletion type N type lateral double diffusion metal oxide semiconductor field-effect transistor comprises a P type dopant well; A said P type dopant well is provided with the 2nd N type dopant well, the 5th source end N type heavily doped region contacts trap with the 3rd P type heavy doping body; Said the 2nd N type dopant well is provided with the 4th drain terminal N type heavily doped region; Channel region between said the 2nd N type dopant well and said the 5th source end N type heavily doped region is provided with second and exhausts implanted layer; Channel region top between said the 2nd N type dopant well and said the 5th source end N type heavily doped region is provided with the 5th gate oxide; Said the 3rd P type heavy doping body contact trap and the zone beyond said the 5th source end N type heavy doping trap, said the 4th drain terminal N type heavy doping trap and the channel region are equipped with field oxide; One end top, the nearly source of said the 3rd field oxide between the 5th gate oxide top and said the 2nd N type dopant well and said the 4th drain terminal N type heavy doping trap is provided with the 5th polysilicon gate; Be connected with metal lead wire respectively on the said contact of the 3rd P type heavy doping body trap, said the 5th source end N type heavy doping trap and said the 4th drain terminal N type heavy doping trap, said the 3rd P type heavy doping body contact trap, said the 5th source end N type heavy doping trap, said the 4th drain terminal N type heavy doping trap, said the 3rd field oxide, said the 5th gate oxide, said the 5th polysilicon gate and the zone beyond the said metal lead wire are provided with the medium oxide layer.
Preferably, be to realize self-isolation between said low pressure enhancement mode N type metal oxide semiconductor field-effect transistor, said low pressure depletion type N type metal oxide semiconductor field-effect transistor, said mesohigh enhancement mode N type lateral double diffusion metal oxide semiconductor field-effect transistor, said mesohigh depletion type N type lateral double diffusion metal oxide semiconductor field-effect transistor and the said high pressure longitudinal double diffusion metal oxide semiconductor field effect transistor through the PN junction acting in opposition that a said N type epitaxial loayer and a said P type dopant well form.
Preferably, channel region the 3rd gate oxide of said high pressure longitudinal double diffusion metal oxide semiconductor field effect transistor adopts and said low pressure enhancement mode N type metal oxide semiconductor field-effect transistor, grid oxygen technology that depletion type N type metal oxide semiconductor field effect transistor is identical; Adopt second field oxide between two said the 2nd P type dopant wells of said high pressure longitudinal double diffusion metal oxide semiconductor field effect transistor.
The preparation process of the technology device that a kind of high-low pressure of the present invention is integrated is following:
At first; Get said heavily doped N type substrate; The said N type epitaxial loayer of growth on the said N type substrate; Then on said N type epitaxial loayer, carry out the photoetching of p type impurity and inject, form said low pressure enhancement mode N type metal oxide semiconductor field-effect transistor, said low pressure depletion type N type metal oxide semiconductor field-effect transistor and said mesohigh enhancement mode N type lateral double diffusion metal oxide semiconductor field-effect transistor, the required said P type dopant well of said mesohigh depletion type N type lateral double diffusion metal oxide semiconductor field-effect transistor through high annealing; Then on a said P type dopant well, carrying out the photoetching of N type impurity injects; In order to make a N type dopant well, the 2nd N type dopant well of said mesohigh enhancement mode N type lateral double diffusion metal oxide semiconductor field-effect transistor and said mesohigh depletion type N type lateral double diffusion metal oxide semiconductor field-effect transistor; Carrying out the photoetching of p type impurity on the said N type epitaxial loayer injects; In order to make the 2nd P type dopant well of said high pressure longitudinal double diffusion metal oxide semiconductor field effect transistor, carry out high-temperature annealing process then; Then carry out the active area photoetching; Adopt wet oxidation process grow said first field oxide, said second field oxide, said the 3rd field oxide; Then carrying out the photoetching of N type impurity injects; Forming said first of said low pressure depletion type N type metal oxide semiconductor field-effect transistor and said mesohigh depletion type N type lateral double diffusion metal oxide semiconductor field-effect transistor exhausts implanted layer and second and exhausts implanted layer; Adopt dry oxidation technology grow said first grid oxide layer, said second gate oxide, said the 3rd gate oxide, said the 4th gate oxide and said the 5th gate oxide after the cleaning again; Carry out the deposit and the etching of polysilicon then, to form said first polysilicon gate, said second polysilicon gate, said the 3rd polysilicon gate, said the 4th polysilicon gate and said the 5th polysilicon gate of said low pressure enhancement mode N type metal oxide semiconductor field-effect transistor, said low pressure depletion type N type metal oxide semiconductor field-effect transistor, said high pressure longitudinal double diffusion metal oxide semiconductor field effect transistor and said mesohigh enhancement mode N type lateral double diffusion metal oxide semiconductor field-effect transistor, said mesohigh depletion type N type lateral double diffusion metal oxide semiconductor field-effect transistor;
Then; Carry out the photoetching of high concentration N type impurity and inject, in order to said the 5th source end N type heavy doping trap and said the 4th drain terminal N type heavy doping trap of said the 4th source end N type heavy doping trap of said the 3rd source end N type heavy doping trap of the said second source end N type heavy doping trap of the said first source end N type heavy doping trap of making said low pressure enhancement mode N type metal oxide semiconductor field-effect transistor and the said first drain terminal N type heavy doping trap, said low pressure depletion type N type metal oxide semiconductor field-effect transistor and the said second drain terminal N type heavy doping trap, said high pressure longitudinal double diffusion metal oxide semiconductor field effect transistor and said mesohigh enhancement mode N type lateral double diffusion metal oxide semiconductor field-effect transistor and the 3rd said drain terminal N type heavy doping trap, said mesohigh depletion type N type lateral double diffusion metal oxide semiconductor field-effect transistor; Then carry out the photoetching of high concentration p type impurity and inject, said the 3rd P type heavy doping body that said the 2nd P type heavy doping body that contact trap, said high pressure longitudinal double diffusion metal oxide semiconductor field effect transistor in order to a said P type heavy doping body of making said low pressure enhancement mode N type metal oxide semiconductor field-effect transistor and said low pressure depletion type N type metal oxide semiconductor field-effect transistor contacts trap and said mesohigh enhancement mode N type lateral double diffusion metal oxide semiconductor field-effect transistor and said mesohigh depletion type N type lateral double diffusion metal oxide semiconductor field-effect transistor contacts trap; Carry out annealing process then, follow deposit medium oxide layer, the etching contact hole, evaporation of aluminum anti-carves aluminium, carries out Passivation Treatment behind the formation electrode;
At last, to the disk thinning back side, carry out after back face metalization handles, as the drain terminal electrode of said high pressure longitudinal double diffusion metal oxide semiconductor field effect transistor.
Compared with prior art, the present invention has following advantage:
(1) structure of the present invention and preparation method based on the integrated vertical power device of epitaxial material, compare with common lateral power is integrated, and integrated level is high, practice thrift the domain cost, and the while realizes that more easily different withstand voltage power devices with conducting resistance design.
(2) the present invention integrates low pressure enhancement mode N type metal oxide semiconductor field-effect transistor, low pressure depletion type N type metal oxide semiconductor field-effect transistor, enhancement mode N type lateral double diffusion metal oxide semiconductor field-effect transistor, depletion type N type lateral double diffusion metal oxide semiconductor field-effect transistor and high pressure longitudinal double diffusion metal oxide semiconductor FET transistor structure; Can compatible low voltage CMOS process make; And prepare the peculiar structure of high-voltage section branch earlier; And then preparation low-pressure section and low pressure and the total structure of high-pressure section, add back process at last.In view of after low-voltage device partly is prepared in; The preparation of high tension apparatus part formerly; So can not exert an influence to the low pressure metal oxide semiconductor field effect transistor; So, the manufacturing process that the preparation method of high-voltage device structure of the present invention can compatibility standard extension CMOS and have the high advantage of reliability.
(3) the present invention adopts enhancement mode/depletion type N type metal oxide semiconductor field-effect transistor (E/DMOS) low-voltage device structure, has avoided cmos device to have the risk of Latch-Up (latch-up).
Description of drawings
Fig. 1 is the integrated technology device structural representation of high-low pressure of the present invention.
Fig. 2 is the sketch map of the step of preparation process one of the integrated technology device architecture of high-low pressure of the present invention.
Fig. 3 is the sketch map of the step of preparation process two of the integrated technology device architecture of high-low pressure of the present invention.
Fig. 4 is the sketch map of the step of preparation process three of the integrated technology device architecture of high-low pressure of the present invention.
Fig. 5 is the sketch map of the step of preparation process four of the integrated technology device architecture of high-low pressure of the present invention.
Fig. 6 is the sketch map of the step of preparation process five of the integrated technology device architecture of high-low pressure of the present invention.
Fig. 7 is the sketch map of the step of preparation process six of the integrated technology device architecture of high-low pressure of the present invention.
Fig. 8 is the sketch map of the step of preparation process seven of the integrated technology device architecture of high-low pressure of the present invention.
Label declaration among the figure: 1.N type heavy doping substrate, 2.N type epitaxial loayer, 3. a P type dopant well, 4. P type heavy doping body contact trap; 5. the first source end N type heavy doping trap, the 6. first drain terminal N type heavy doping trap, the 7. second source end N type heavy doping trap, the 8. second drain terminal N type heavy doping trap; 9. first grid oxide layer, 10. first polysilicon gate, 11. second gate oxides; 12. second polysilicon gate, 13. first exhaust implanted layer 14. first field oxides, 15. the 2nd P type dopant wells; 16. the 2nd P type heavy doping body contact trap, 17. the 3rd source end N type heavy doping traps, 18. the 3rd gate oxides; 19. second field oxide, 20. the 3rd polysilicon gates, 21. the one N type dopant wells; 22. the 2nd N type dopant well, 23. drain terminal N type heavily doped regions, 24. source end N type heavily doped regions; 25. the 3rd P type heavy doping body contact trap, 26. the 4th gate oxides, 27. the 4th polysilicon gates; 28. the 3rd drain terminal N type heavy doping trap, 29. the 4th source end N type heavy doping traps, 30. the 5th gate oxides; 31. the 5th polysilicon gate and field plate, 32. second exhaust implanted layer, 33. the 3rd field oxides; 34. the medium oxide layer, 35. low pressure enhancement mode N type metal oxide semiconductor field-effect transistors, 36. low pressure depletion type N type metal oxide semiconductor field-effect transistors, 37. high pressure longitudinal double diffusion metal oxide semiconductor field effect transistors, 38. mesohigh enhancement mode N type lateral double diffusion metal oxide semiconductor field-effect transistors, 39. mesohigh depletion type N type lateral double diffusion metal oxide semiconductor field-effect transistors.
Embodiment
Below in conjunction with accompanying drawing, the structure of the integrated technology device of a kind of high-low pressure of the present invention is elaborated.
As shown in Figure 1; The technology device that a kind of high-low pressure is integrated; Comprise: N type heavy doping substrate 1; Said N type heavy doping substrate 1 is provided with N type epitaxial loayer 2; N type epitaxial loayer 2 is provided with low pressure enhancement mode N type metal oxide semiconductor field-effect transistor 35, low pressure depletion type N type metal oxide semiconductor field-effect transistor 36, high pressure longitudinal double diffusion metal oxide semiconductor field effect transistor 37 and mesohigh enhancement mode N type lateral double diffusion metal oxide semiconductor field-effect transistor 38, mesohigh depletion type N type lateral double diffusion metal oxide semiconductor field-effect transistor 39; It is characterized in that low pressure enhancement mode N type metal oxide semiconductor field-effect transistor 35, low pressure depletion type N type metal oxide semiconductor field-effect transistor 36 and mesohigh enhancement mode N type lateral double diffusion metal oxide semiconductor field-effect transistor 38, mesohigh depletion type N type lateral double diffusion metal oxide semiconductor field-effect transistor 39 all adopt the self-isolation structure between the first P type dopant well, 3 low pressure enhancement mode N type metal oxide semiconductor field-effect transistors 35, low pressure depletion type N type metal oxide semiconductor field-effect transistor 36, mesohigh enhancement mode N type lateral double diffusion metal oxide semiconductor field-effect transistor 38, mesohigh depletion type N type lateral double diffusion metal oxide semiconductor field-effect transistor 39 and high pressure longitudinal double diffusion metal oxide semiconductor field effect transistor 37.
Above-mentioned low pressure enhancement mode N type metal oxide semiconductor field-effect transistor 35 comprises a P type dopant well 3; The one P type dopant well 3 is provided with P type heavy doping body contact trap 4; The first source end N type heavy doping trap 5 and the first drain terminal N type heavy doping trap 6; Be provided with first field oxide 14 between the one P type heavy doping body contact trap 4 and the first source end N type heavy doping trap 5; Channel region top between the first source end N type heavy doping trap 5 and the first drain terminal N type heavy doping trap 6 is provided with first grid oxide layer 9; First grid oxide layer 9 tops are provided with first polysilicon gate 10; The one P type heavy doping body contact trap 4; Be connected with metal lead wire respectively on the first source end N type heavy doping trap 5 and the first drain terminal N type heavy doping trap 6; The one P type heavy doping body contact trap 4; The first source end N type heavy doping trap 5; The first drain terminal N type heavy doping trap 6; First field oxide 14; First grid oxide layer 9; Zone beyond first polysilicon gate 10 and the metal lead wire is provided with medium oxide layer 34
Above-mentioned low pressure depletion type N type metal oxide semiconductor field-effect transistor 36 comprises a said P type dopant well 3; The one P type dopant well 3 is provided with said a P type heavy doping body contact trap 4, the second source end N type heavy doping trap 7 and the second drain terminal N type heavy doping trap 8; Be provided with first field oxide 14 between the second source end N type heavy doping trap 7 of first drain terminal N type heavy doping trap 6 of low pressure enhancement mode N type metal oxide semiconductor field-effect transistor 35 and low pressure depletion type N type metal oxide semiconductor field-effect transistor 36; Channel region between the second source end N type heavy doping trap 7 and the second drain terminal N type heavy doping trap 8 is provided with first and exhausts implanted layer 13; Channel region top between the second source end N type heavy doping trap 7 and the second drain terminal N type heavy doping trap 8 is provided with second gate oxide 11; Second gate oxide, 11 tops are provided with second polysilicon gate 12; Be connected with metal lead wire respectively on the one P type heavy doping body contact trap 4, the second source end N type heavy doping trap 7 and the second drain terminal N type heavy doping trap 8, P type heavy doping body contact trap 4, the second source end N type heavy doping trap 7, the second drain terminal N type heavy doping trap 8, first field oxide 14, second gate oxide 11, second polysilicon gate 12 and the zone beyond the metal lead wire are provided with medium oxide layer 34.
Above-mentioned high pressure longitudinal double diffusion metal oxide semiconductor field effect transistor 37 comprises N type heavy doping substrate 1; N type heavy doping substrate 1 is provided with N type epitaxial loayer 2; N type epitaxial loayer 2 is provided with the 2nd P type dopant well 15; The 2nd P type dopant well 15 is provided with the 2nd P type heavy doping body contact trap 16 and the 3rd source end N type heavy doping trap 17; The 2nd P type dopant well 15 comprises that the channel region top of the 3rd source end N type heavy doping trap 17 is provided with the 3rd gate oxide 18; Zone between the 2nd P type dopant well 15 and the 2nd P type heavy doping body contact trap 16 is provided with second field oxide 19; The 3rd gate oxide 18 and second field oxide, 19 tops are provided with the 3rd polysilicon gate 20; Be connected with metal lead wire on the 2nd P type heavy doping body contact trap 16, the 3rd source end N type heavy doping trap 17, the 2nd P type heavy doping body contact trap 16, the 3rd source end N type heavy doping trap 17, second field oxide 19, the 3rd gate oxide 18, the 3rd polysilicon gate 20 and the zone beyond the metal lead wire are provided with said medium oxide layer 34, and N type heavy doping substrate 1 bottom is provided with metal lead wire as the drain terminal electrode.
Above-mentioned mesohigh enhancement mode N type lateral double diffusion metal oxide semiconductor field-effect transistor 38 comprises a P type dopant well 3; The one P type dopant well 3 is provided with a N type dopant well 21, the 4th source end N type heavily doped region 24 contacts trap 25 with the 3rd P type heavy doping body; The one N type dopant well 21 is provided with the 3rd drain terminal N type heavy doping trap 23; Channel region top between the one N type dopant well 21 and the said source end N type heavily doped region 24 is provided with the 4th gate oxide 26; The 3rd P type heavy doping body contact trap 25 is equipped with field oxide 33 with the 4th source end N type heavy doping trap 24, the 3rd drain terminal N type heavy doping trap 23 and channel region zone in addition; One end top, the 3rd field oxide 33 nearly sources between gate oxide 26 tops and a said N type dopant well 21 and the 3rd drain terminal N type heavy doping trap 23 is provided with the 4th polysilicon gate 27; Be connected with metal lead wire respectively on the 3rd P type heavy doping body contact trap 25, the 4th source end N type heavy doping trap 24 and the 3rd drain terminal N type heavy doping trap 23, the 3rd P type heavy doping body contact trap 25, the 4th source end N type heavy doping trap 24, the 3rd drain terminal N type heavy doping trap 23, the 3rd field oxide 33, the 4th gate oxide 26, the 4th polysilicon gate 27 and the zone beyond the said metal lead wire are provided with medium oxide layer 34.
Above-mentioned mesohigh depletion type N type lateral double diffusion metal oxide semiconductor field-effect transistor 39 comprises a P type dopant well 3; The one P type dopant well 3 is provided with the 2nd N type dopant well 22, the 5th source end N type heavily doped region 29 contacts trap 25 with the 3rd P type heavy doping body; The 2nd N type dopant well 22 is provided with channel region between the 4th drain terminal N type heavily doped region 28 the 2nd N type dopant well 22 and the 5th source end N type heavily doped region 29 and is provided with second and exhausts implanted layer 32; Channel region top between the 2nd N type dopant well 22 and the 5th source end N type heavily doped region 29 is provided with the 5th gate oxide 30; The 3rd P type heavy doping body contact trap 25 is equipped with field oxide 33 with the 5th source end N type heavy doping trap 29, the 4th drain terminal N type heavy doping trap 28 and channel region zone in addition; One end top, the 3rd field oxide 33 nearly sources between the 5th gate oxide 30 tops and said the 2nd N type dopant well 22 and the 4th drain terminal N type heavy doping trap 28 is provided with the 5th polysilicon gate 31; Be connected with metal lead wire respectively on the 3rd P type heavy doping body contact trap 25, the 5th source end N type heavy doping trap 29 and the 4th drain terminal N type heavy doping trap 28, the 3rd P type heavy doping body contact trap 25, the 5th source end N type heavy doping trap 29, the 4th drain terminal N type heavy doping trap 28, the 3rd field oxide 33, the 5th gate oxide 30, institute's the 5th polysilicon gate 31 and metal lead wire zone in addition are provided with the medium oxide layer.
Above-mentioned low pressure enhancement mode N type metal oxide semiconductor field-effect transistor 35; Low pressure depletion type N type metal oxide semiconductor field-effect transistor 36; Mesohigh enhancement mode N type lateral double diffusion metal oxide semiconductor field-effect transistor 38; Be to form through a N type epitaxial loayer 2 and a P type dopant well 3 to come the PN junction acting in opposition to realize self-isolation between mesohigh depletion type N type lateral double diffusion metal oxide semiconductor field-effect transistor 39 and the high pressure longitudinal double diffusion metal oxide semiconductor field effect transistor 37.
Channel region the 3rd gate oxide 18 of above-mentioned high pressure longitudinal double diffusion metal oxide semiconductor field effect transistor 37 adopts the grid oxygen technology identical with low pressure enhancement mode N type metal oxide semiconductor field-effect transistor 35, depletion type N type metal oxide semiconductor field effect transistor 36; Adopt second field oxide 19 between two said the 2nd P type dopant wells 15 of high pressure longitudinal double diffusion metal oxide semiconductor field effect transistor 37.
The preparation process of the technology device that a kind of high-low pressure of the present invention is integrated is following:
At first, as shown in Figure 2, get heavily doped N type substrate 1, the said N type epitaxial loayer 2 of growth on the N type substrate 1.
Then; As shown in Figure 3; On N type epitaxial loayer 2, carry out the photoetching of p type impurity and inject, form the required P type dopant well 3 of low pressure enhancement mode N type metal oxide semiconductor field-effect transistor 35, low pressure depletion type N type metal oxide semiconductor field-effect transistor 36 and mesohigh enhancement mode N type lateral double diffusion metal oxide semiconductor field-effect transistor 38, mesohigh depletion type N type lateral double diffusion metal oxide semiconductor field-effect transistor 39 through high annealing.
Then; As shown in Figure 4; On a P type dopant well 3, carrying out the photoetching of N type impurity injects; In order to make a N type dopant well 21, the 2nd N type dopant well 22 of mesohigh enhancement mode N type lateral double diffusion metal oxide semiconductor field-effect transistor 38 and mesohigh depletion type N type lateral double diffusion metal oxide semiconductor field-effect transistor 39; Carry out the photoetching of p type impurity on the N type epitaxial loayer 2 and inject,, carry out high-temperature annealing process then in order to make the 2nd P type dopant well 15 of said high pressure longitudinal double diffusion metal oxide semiconductor field effect transistor 37.
Then, as shown in Figure 5, carry out the active area photoetching, adopt wet oxidation process grow said first field oxide 14, institute second field oxide 19, the 3rd field oxide 33.
Then; As shown in Figure 6; Carrying out the photoetching of N type impurity injects; First of formation low pressure depletion type N type metal oxide semiconductor field-effect transistor 36 and mesohigh depletion type N type lateral double diffusion metal oxide semiconductor field-effect transistor 39 exhausts implanted layer 13 and second and exhausts implanted layer 32; Adopt dry oxidation technology grow said first grid oxide layer 9, second gate oxide 11, the 3rd gate oxide 18, the 4th gate oxide 26 and the 5th gate oxide 30 after the cleaning again; Carry out the deposit and the etching of polysilicon then, with first polysilicon gate 10 that forms low pressure enhancement mode N type metal oxide semiconductor field-effect transistor 35, low pressure depletion type N type metal oxide semiconductor field-effect transistor 36, high pressure longitudinal double diffusion metal oxide semiconductor field effect transistor 37 and mesohigh enhancement mode N type lateral double diffusion metal oxide semiconductor field-effect transistor 38, mesohigh depletion type N type lateral double diffusion metal oxide semiconductor field-effect transistor 39, second polysilicon gate 12, the 3rd polysilicon gate 20, the 4th polysilicon gate 27 and the 5th polysilicon gate 31.
Then; As shown in Figure 7; Carry out the photoetching of high concentration N type impurity and inject, in order to the 5th source end N type heavy doping trap 29 and the 4th drain terminal N type heavy doping trap 28 of the 4th source end N type heavy doping trap 24 of the 3rd source end N type heavy doping trap 17 of the second source end N type heavy doping trap 7 of the first source end N type heavy doping trap 5 of making said low pressure enhancement mode N type metal oxide semiconductor field-effect transistor 35 and the first drain terminal N type heavy doping trap 6, low pressure depletion type N type metal oxide semiconductor field-effect transistor 36 and the second drain terminal N type heavy doping trap 8, high pressure longitudinal double diffusion metal oxide semiconductor field effect transistor 37 and mesohigh enhancement mode N type lateral double diffusion metal oxide semiconductor field-effect transistor 38 and the 3rd drain terminal N type heavy doping trap 23, mesohigh depletion type N type lateral double diffusion metal oxide semiconductor field-effect transistor 39; Then carry out the photoetching of high concentration p type impurity and inject, the 3rd P type heavy doping body that the 2nd P type heavy doping body that contacts trap 4, high pressure longitudinal double diffusion metal oxide semiconductor field effect transistor 37 in order to a P type heavy doping body of making said low pressure enhancement mode N type metal oxide semiconductor field-effect transistor 35 and low pressure depletion type N type metal oxide semiconductor field-effect transistor 36 contacts trap 16 and mesohigh enhancement mode N type lateral double diffusion metal oxide semiconductor field-effect transistor 38 and mesohigh depletion type N type lateral double diffusion metal oxide semiconductor field-effect transistor 39 contacts trap 25; Carry out annealing process then, follow deposit medium oxide layer 34, the etching contact hole, evaporation of aluminum anti-carves aluminium, carries out Passivation Treatment behind the formation electrode.
At last, as shown in Figure 8, to the disk thinning back side, carry out after back face metalization handles, as the drain terminal electrode of high pressure longitudinal double diffusion metal oxide semiconductor field effect transistor 37.
Claims (9)
1. technology device that high-low pressure is integrated; Comprise: N type heavy doping substrate (1); Said N type heavy doping substrate (1) is provided with N type epitaxial loayer (2); Said N type epitaxial loayer (2) is provided with low pressure enhancement mode N type metal oxide semiconductor field-effect transistor (35), low pressure depletion type N type metal oxide semiconductor field-effect transistor (36), high pressure longitudinal double diffusion metal oxide semiconductor field effect transistor (37) and mesohigh enhancement mode N type lateral double diffusion metal oxide semiconductor field-effect transistor (38), mesohigh depletion type N type lateral double diffusion metal oxide semiconductor field-effect transistor (39); It is characterized in that; Said low pressure enhancement mode N type metal oxide semiconductor field-effect transistor (35), said low pressure depletion type N type metal oxide semiconductor field-effect transistor (36) and said mesohigh enhancement mode N type lateral double diffusion metal oxide semiconductor field-effect transistor (38), said mesohigh depletion type N type lateral double diffusion metal oxide semiconductor field-effect transistor (39) all are positioned at a P type dopant well (3), adopt the self-isolation structure between said low pressure enhancement mode N type metal oxide semiconductor field-effect transistor (35), said low pressure depletion type N type metal oxide semiconductor field-effect transistor (36), said mesohigh enhancement mode N type lateral double diffusion metal oxide semiconductor field-effect transistor (38), said mesohigh depletion type N type lateral double diffusion metal oxide semiconductor field-effect transistor (39) and the said high pressure longitudinal double diffusion metal oxide semiconductor field effect transistor (37).
2. the technology device that high-low pressure according to claim 1 is integrated; It is characterized in that; Said low pressure enhancement mode N type metal oxide semiconductor field-effect transistor (35) comprises a said P type dopant well (3); A said P type dopant well (3) is provided with a P type heavy doping body contact trap (4), the first source end N type heavy doping trap (5) and the first drain terminal N type heavy doping trap (6); Be provided with first field oxide (14) between said P type heavy doping body contact trap (4) and the said first source end N type heavy doping trap (5); Channel region top between said first source end N type heavy doping trap (5) and the said first drain terminal N type heavy doping trap (6) is provided with first grid oxide layer (9); Said first grid oxide layer (9) top is provided with first polysilicon gate (10); Be connected with metal lead wire respectively on said a P type heavy doping body contact trap (4), the said first source end N type heavy doping trap (5) and the said first drain terminal N type heavy doping trap (6), said P type heavy doping body contact trap (4), the said first source end N type heavy doping trap (5), the said first drain terminal N type heavy doping trap (6), said first field oxide (14), said first grid oxide layer (9), said first polysilicon gate (10) and the zone beyond the metal lead wire are provided with medium oxide layer (34).
3. the technology device that high-low pressure according to claim 1 is integrated; It is characterized in that; Said low pressure depletion type N type metal oxide semiconductor field-effect transistor (36) comprises a said P type dopant well (3); On a said P type dopant well (3), be provided with said a P type heavy doping body contact trap (4), the second source end N type heavy doping trap (7) and the second drain terminal N type heavy doping trap (8); Be provided with said first field oxide (14) between the said first drain terminal N type heavy doping trap (6) of said low pressure enhancement mode N type metal oxide semiconductor field-effect transistor (35) and the said second source end N type heavy doping trap (7) of said low pressure depletion type N type metal oxide semiconductor field-effect transistor (36); Channel region between said second source end N type heavy doping trap (7) and the said second drain terminal N type heavy doping trap (8) is provided with first and exhausts implanted layer (13); Channel region top between said second source end N type heavy doping trap (7) and the said second drain terminal N type heavy doping trap (8) is provided with second gate oxide (11); Said second gate oxide (11) top is provided with second polysilicon gate (12); Be connected with metal lead wire respectively on said a P type heavy doping body contact trap (4), the said second source end N type heavy doping trap (7) and the said second drain terminal N type heavy doping trap (8), said P type heavy doping body contact trap (4), the said second source end N type heavy doping trap (7), the said second drain terminal N type heavy doping trap (8), said first field oxide (14), said second gate oxide (11), said second polysilicon gate (12) and the zone beyond the metal lead wire are provided with medium oxide layer (34).
4. the technology device that high-low pressure according to claim 1 is integrated; It is characterized in that; Said high pressure longitudinal double diffusion metal oxide semiconductor field effect transistor (37) comprises said N type heavy doping substrate (1); Said N type heavy doping substrate (1) is provided with N type epitaxial loayer (2); Said N type epitaxial loayer (2) is provided with the 2nd P type dopant well (15); Said the 2nd P type dopant well (15) is provided with the 2nd P type heavy doping body contact trap (16) and the 3rd source end N type heavy doping trap (17); Said the 2nd P type dopant well (15) comprises that the channel region top of said the 3rd source end N type heavy doping trap (17) is provided with the 3rd gate oxide (18); Zone between said the 2nd P type dopant well (15) and said the 2nd P type heavy doping body contact trap (16) is provided with second field oxide (19); Said the 3rd gate oxide (18) and said second field oxide (19) top are provided with the 3rd polysilicon gate (20); Be connected with metal lead wire on said the 2nd P type heavy doping body contact trap (16), said the 3rd source end N type heavy doping trap (17), said the 2nd P type heavy doping body contact trap (16), said the 3rd source end N type heavy doping trap (17), said second field oxide (19), said the 3rd gate oxide (18), said the 3rd polysilicon gate (20) and the zone beyond the metal lead wire are provided with said medium oxide layer (34), and said N type heavy doping substrate (1) bottom is provided with metal lead wire as the drain terminal electrode.
5. the technology device that high-low pressure according to claim 1 is integrated; It is characterized in that; Said mesohigh enhancement mode N type lateral double diffusion metal oxide semiconductor field-effect transistor (38) comprises a P type dopant well (3); A said P type dopant well (3) is provided with a N type dopant well (21), the 4th source end N type heavily doped region (24) and the 3rd P type heavy doping body and contacts trap (25); A said N type dopant well (21) is provided with the 3rd drain terminal N type heavy doping trap (23); Channel region top between a said N type dopant well (21) and the said source end N type heavily doped region (24) is provided with the 4th gate oxide (26); Said the 3rd P type heavy doping body contact trap (25) and the zone beyond said the 4th source end N type heavy doping trap (24), said the 3rd drain terminal N type heavy doping trap (23) and the channel region are equipped with field oxide (33); One end top, the nearly source of said the 3rd field oxide (33) between gate oxide (26) top and a said N type dopant well (21) and said the 3rd drain terminal N type heavy doping trap (23) is provided with the 4th polysilicon gate (27); Be connected with metal lead wire respectively on the said contact of the 3rd P type heavy doping body trap (25), said the 4th source end N type heavy doping trap (24) and said the 3rd drain terminal N type heavy doping trap (23), said the 3rd P type heavy doping body contact trap (25), said the 4th source end N type heavy doping trap (24), said the 3rd drain terminal N type heavy doping trap (23), said the 3rd field oxide (33), said the 4th gate oxide (26), said the 4th polysilicon gate (27) and the zone beyond the said metal lead wire are provided with medium oxide layer (34).
6. the technology device that high-low pressure according to claim 1 is integrated; It is characterized in that; Said mesohigh depletion type N type lateral double diffusion metal oxide semiconductor field-effect transistor (39) comprises a P type dopant well (3); A said P type dopant well (3) is provided with the 2nd N type dopant well (22), the 5th source end N type heavily doped region (29) and the 3rd P type heavy doping body and contacts trap (25); Said the 2nd N type dopant well (22) is provided with the 4th drain terminal N type heavily doped region (28); Channel region between said the 2nd N type dopant well (22) and said the 5th source end N type heavily doped region (29) is provided with second and exhausts implanted layer (32); Channel region top between said the 2nd N type dopant well (22) and said the 5th source end N type heavily doped region (29) is provided with the 5th gate oxide (30); Said the 3rd P type heavy doping body contact trap (25) and the zone beyond said the 5th source end N type heavy doping trap (29), said the 4th drain terminal N type heavy doping trap (28) and the channel region are equipped with field oxide (33); One end top, the nearly source of said the 3rd field oxide (33) between the 5th gate oxide (30) top and said the 2nd N type dopant well (22) and said the 4th drain terminal N type heavy doping trap (28) is provided with the 5th polysilicon gate (31); Be connected with metal lead wire respectively on the said contact of the 3rd P type heavy doping body trap (25), said the 5th source end N type heavy doping trap (29) and said the 4th drain terminal N type heavy doping trap (28), said the 3rd P type heavy doping body contact trap (25), said the 5th source end N type heavy doping trap (29), said the 4th drain terminal N type heavy doping trap (28), said the 3rd field oxide (33), said the 5th gate oxide (30), said the 5th polysilicon gate (31) and the zone beyond the said metal lead wire are provided with medium oxide layer (34).
7. the technology device that high-low pressure according to claim 1 is integrated; It is characterized in that, form the PN junction acting in opposition through a said N type epitaxial loayer (2) and a said P type dopant well (3) between said low pressure enhancement mode N type metal oxide semiconductor field-effect transistor (35), said low pressure depletion type N type metal oxide semiconductor field-effect transistor (36), said mesohigh enhancement mode N type lateral double diffusion metal oxide semiconductor field-effect transistor (38), said mesohigh depletion type N type lateral double diffusion metal oxide semiconductor field-effect transistor (39) and the said high pressure longitudinal double diffusion metal oxide semiconductor field effect transistor (37).
8. the technology device that high-low pressure according to claim 4 is integrated; It is characterized in that channel region the 3rd gate oxide (18) of said high pressure longitudinal double diffusion metal oxide semiconductor field effect transistor (37) adopts and said low pressure enhancement mode N type metal oxide semiconductor field-effect transistor (35), grid oxygen technology that depletion type N type metal oxide semiconductor field effect transistor (36) is identical; Adopt second field oxide (19) between two said the 2nd P type dopant wells (15) of said high pressure longitudinal double diffusion metal oxide semiconductor field effect transistor (37).
9. preparation method who is used for the integrated technology device architecture of high-low pressure as claimed in claim 1 is characterized in that it comprises following preparation process:
At first; Get said heavily doped N type substrate (1); Said N type substrate (1) is gone up growth said N type epitaxial loayer (2); Then on said N type epitaxial loayer (2), carry out the photoetching of p type impurity and inject, form said low pressure enhancement mode N type metal oxide semiconductor field-effect transistor (35), said low pressure depletion type N type metal oxide semiconductor field-effect transistor (36) and said mesohigh enhancement mode N type lateral double diffusion metal oxide semiconductor field-effect transistor (38), the required said P type dopant well (3) of said mesohigh depletion type N type lateral double diffusion metal oxide semiconductor field-effect transistor (39) through high annealing; Then on a said P type dopant well (3), carrying out the photoetching of N type impurity injects; In order to a N type dopant well (21), the 2nd N type dopant well (22) of making said mesohigh enhancement mode N type lateral double diffusion metal oxide semiconductor field-effect transistor (38) and said mesohigh depletion type N type lateral double diffusion metal oxide semiconductor field-effect transistor (39); Carrying out the photoetching of p type impurity on the said N type epitaxial loayer (2) injects; In order to make the 2nd P type dopant well (15) of said high pressure longitudinal double diffusion metal oxide semiconductor field effect transistor (37), carry out high-temperature annealing process then; Then carry out the active area photoetching; Adopt wet oxidation process grow said first field oxide (14), said second field oxide (19), said the 3rd field oxide (33); Then carrying out the photoetching of N type impurity injects; Forming said first of said low pressure depletion type N type metal oxide semiconductor field-effect transistor (36) and said mesohigh depletion type N type lateral double diffusion metal oxide semiconductor field-effect transistor (39) exhausts implanted layer (13) and second and exhausts implanted layer (32); Adopt dry oxidation technology grow said first grid oxide layer (9), said second gate oxide (11), said the 3rd gate oxide (18), said the 4th gate oxide (26) and said the 5th gate oxide (30) after the cleaning again; Carry out the deposit and the etching of polysilicon then, with said first polysilicon gate (10), said second polysilicon gate (12), said the 3rd polysilicon gate (20), said the 4th polysilicon gate (27) and said the 5th polysilicon gate (31) that forms said low pressure enhancement mode N type metal oxide semiconductor field-effect transistor (35), said low pressure depletion type N type metal oxide semiconductor field-effect transistor (36), said high pressure longitudinal double diffusion metal oxide semiconductor field effect transistor (37) and said mesohigh enhancement mode N type lateral double diffusion metal oxide semiconductor field-effect transistor (38), said mesohigh depletion type N type lateral double diffusion metal oxide semiconductor field-effect transistor (39);
Then; Carry out the photoetching of high concentration N type impurity and inject, in order to said the 5th source end N type heavy doping trap (29) and said the 4th drain terminal N type heavy doping trap (28) of said the 4th source end N type heavy doping trap (24) of said the 3rd source end N type heavy doping trap (17) of the said second source end N type heavy doping trap (7) of the said first source end N type heavy doping trap (5) of making said low pressure enhancement mode N type metal oxide semiconductor field-effect transistor (35) and the said first drain terminal N type heavy doping trap (6), said low pressure depletion type N type metal oxide semiconductor field-effect transistor (36) and the said second drain terminal N type heavy doping trap (8), said high pressure longitudinal double diffusion metal oxide semiconductor field effect transistor (37) and said mesohigh enhancement mode N type lateral double diffusion metal oxide semiconductor field-effect transistor (38) and the 3rd said drain terminal N type heavy doping trap (23), said mesohigh depletion type N type lateral double diffusion metal oxide semiconductor field-effect transistor (39); Then carry out the photoetching of high concentration p type impurity and inject, said the 3rd P type heavy doping body that said the 2nd P type heavy doping body that contacts trap (4), said high pressure longitudinal double diffusion metal oxide semiconductor field effect transistor (37) in order to a said P type heavy doping body of making said low pressure enhancement mode N type metal oxide semiconductor field-effect transistor (35) and said low pressure depletion type N type metal oxide semiconductor field-effect transistor (36) contacts trap (16) and said mesohigh enhancement mode N type lateral double diffusion metal oxide semiconductor field-effect transistor (38) and said mesohigh depletion type N type lateral double diffusion metal oxide semiconductor field-effect transistor (39) contacts trap (25); Carry out annealing process then, follow deposit medium oxide layer (34), the etching contact hole, evaporation of aluminum anti-carves aluminium, carries out Passivation Treatment behind the formation electrode;
At last, to the disk thinning back side, carry out after back face metalization handles, as the drain terminal electrode of said high pressure longitudinal double diffusion metal oxide semiconductor field effect transistor (37).
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103426880A (en) * | 2013-05-22 | 2013-12-04 | 苏州博创集成电路设计有限公司 | Complementary metal-oxide-semiconductor transistor (CMOS) type high voltage and low voltage integrated technological device structure and method for manufacturing same |
| CN104347618A (en) * | 2013-08-09 | 2015-02-11 | 英飞凌科技奥地利有限公司 | Electronic Component and Method |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6429481B1 (en) * | 1997-11-14 | 2002-08-06 | Fairchild Semiconductor Corporation | Field effect transistor and method of its manufacture |
| US20050035398A1 (en) * | 1999-05-25 | 2005-02-17 | Williams Richard K. | Trench MOSFET with recessed clamping diode |
| CN101552274A (en) * | 2004-06-30 | 2009-10-07 | 先进模拟科技公司 | Semiconductor device and manufacturing and processing method thereof |
| CN101694850A (en) * | 2009-10-16 | 2010-04-14 | 电子科技大学 | Carrier-storing grooved gate IGBT with P-type floating layer |
-
2010
- 2010-08-30 CN CN2010102657999A patent/CN102386185A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6429481B1 (en) * | 1997-11-14 | 2002-08-06 | Fairchild Semiconductor Corporation | Field effect transistor and method of its manufacture |
| US20050035398A1 (en) * | 1999-05-25 | 2005-02-17 | Williams Richard K. | Trench MOSFET with recessed clamping diode |
| CN101552274A (en) * | 2004-06-30 | 2009-10-07 | 先进模拟科技公司 | Semiconductor device and manufacturing and processing method thereof |
| CN101694850A (en) * | 2009-10-16 | 2010-04-14 | 电子科技大学 | Carrier-storing grooved gate IGBT with P-type floating layer |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103426880A (en) * | 2013-05-22 | 2013-12-04 | 苏州博创集成电路设计有限公司 | Complementary metal-oxide-semiconductor transistor (CMOS) type high voltage and low voltage integrated technological device structure and method for manufacturing same |
| CN104347618A (en) * | 2013-08-09 | 2015-02-11 | 英飞凌科技奥地利有限公司 | Electronic Component and Method |
| US9620472B2 (en) | 2013-08-09 | 2017-04-11 | Infineon Technologies Austria Ag | Method of manufacturing an electronic component |
| CN104347618B (en) * | 2013-08-09 | 2018-01-19 | 英飞凌科技奥地利有限公司 | Electronic unit and method |
| CN105652176A (en) * | 2016-03-08 | 2016-06-08 | 上海华虹宏力半导体制造有限公司 | Method and device for testing number of guard rings |
| CN105652176B (en) * | 2016-03-08 | 2018-06-05 | 上海华虹宏力半导体制造有限公司 | A kind of test method and device of protection ring quantity |
| CN105762149B (en) * | 2016-05-13 | 2021-06-25 | 上海贝岭股份有限公司 | CMOS integrated circuit and process method |
| CN105762149A (en) * | 2016-05-13 | 2016-07-13 | 上海贝岭股份有限公司 | CMOS integrated circuit and process method |
| WO2018040973A1 (en) * | 2016-08-31 | 2018-03-08 | 无锡华润上华科技有限公司 | Component integrated with depletion-mode junction field-effect transistor and method for manufacturing component |
| US10867995B2 (en) | 2016-08-31 | 2020-12-15 | Csmc Technologies Fab2 Co., Ltd. | Device integrated with depletion-mode junction fielf-effect transistor and method for manufacturing the same |
| CN109980010B (en) * | 2017-12-28 | 2020-10-13 | 无锡华润上华科技有限公司 | Method for manufacturing semiconductor device and integrated semiconductor device |
| CN109980010A (en) * | 2017-12-28 | 2019-07-05 | 无锡华润上华科技有限公司 | A kind of manufacturing method and integrated-semiconductor device of semiconductor devices |
| CN110534513A (en) * | 2019-09-06 | 2019-12-03 | 电子科技大学 | A kind of high-low pressure integrated device and its manufacturing method |
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