CN105652070B - A kind of differential signal amplitude detection circuit - Google Patents
A kind of differential signal amplitude detection circuit Download PDFInfo
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- CN105652070B CN105652070B CN201610039867.7A CN201610039867A CN105652070B CN 105652070 B CN105652070 B CN 105652070B CN 201610039867 A CN201610039867 A CN 201610039867A CN 105652070 B CN105652070 B CN 105652070B
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Abstract
The invention discloses a kind of differential signal amplitude detection circuit, the first and second NMOS tube grid connects negative, positive input, and the first and second NMOS tube source electrode is connected, and is grounded through the first constant-current source；Third and fourth NMOS tube grid connects positive and negative input, third and fourth NMOS tube source electrode is connected, and is grounded through the second constant-current source；The drain electrode of first and third NMOS tube is connected, and connects power supply through first resistor；The second, four NMOS tubes drain electrode is connected to the first tie point, connects power supply through second resistance；Third and fourth ohmic connection points is connected with the five, the six NMOS tube grids, five, the six NMOS tube source electrodes are connected, it is grounded through third constant-current source, the drain electrode of the five, the six NMOS tubes connects power supply through the five, the six resistance, and the 6th NMOS tube and the 6th ohmic connection points are the second tie point；First and second tie point connects two input terminals of comparator, exports VOUT.The configuration of the present invention is simple, it is low in energy consumption, a millivolt rank differential small-signal can be effectively detected, it is widely applicable.
Description
Technical field
The present invention relates to analog signal processing and fields of communication technology, and in particular to a kind of differential signal amplitude detection electricity
Road.
Background technique
Differential signal amplitude detection circuit is applied very extensively in terms of data sampling as a kind of basic analog circuit, is being communicated
In system, it is often necessary to which whether the normal transmission signal of judgement has interrupted as system alarm condition, or opens sleep mould
Formula is to save power consumption.
When high speed signal is transmitted, generally differential signal, differential amplitude is lower, at this moment needs to detect lesser difference
Amplitude, sometimes even only several millivolts, for example, limiting amplifier, laser driver in 10G SFP+ optical module and
Inside 10G multiplexing reconciliation multiplexing chip, it is required to whether detection input signal loses, and differential amplitude may be as low as millivolt level
Not.
Differential signal is converted to list using the diode characteristic of diode or certain devices by traditional detection circuit
Nonpolarity signal is held, connects a comparator separately then to judge whether this signal amplitude is greater than the detection threshold of setting.But this
The transfer efficiency of kind mode is more low, in the lower situation of differential input signal amplitude, the amplitude very little of Single-end output,
Even close to zero, therefore it is unable to get correct testing result.Meanwhile (Bipolar either is managed using diode, BJT
Junction Transistor, bipolar junction transistor) common collector framework or metal-oxide-semiconductor source follower framework, increase
Benefit, i.e. the ratio between Single-end output amplitude and differential input signal amplitude, calculated value are limited to semiconductors manufacture less than 1
Area limitation in technique and actual circuit design, gain can be smaller.It is single-ended defeated when difference input signal amplitude is smaller
Amplitude can not follow differential input signal amplitude out, or even close to zero, therefore can not carry out differential small-signal detection.
In view of this, being badly in need of providing a kind of new differential signal amplitude detection circuit, existing differential signal amplitude is solved
Detection circuit transfer efficiency is low, and when difference input signal amplitude is smaller, Single-end output amplitude can not follow Differential Input
Signal amplitude, or even close to zero, lead to not the problem of carrying out differential small-signal detection.
Summary of the invention
The technical problem to be solved by the present invention is to existing differential signal amplitude detection circuit transfer efficiency is low, it is on duty
When dividing input signal amplitude smaller, Single-end output amplitude can not follow differential input signal amplitude, or even close to zero, cause
The problem of can not carrying out differential small-signal detection.
In order to solve the above-mentioned technical problem, the technical scheme adopted by the invention is that providing a kind of differential signal amplitude detection
The grid of circuit, the first NMOS tube and the second NMOS tube connects the negative input end and positive input terminal of differential input signal respectively, and first
NMOS tube is connected with the source electrode of the second NMOS tube, and is grounded through the first constant-current source；
The grid of third NMOS tube and the 4th NMOS tube connects the positive input terminal and negative input end of differential input signal respectively, the
Three NMOS tubes are connected with the source electrode of the 4th NMOS tube, and are grounded through the second constant-current source；
First NMOS tube is connected with the drain electrode of third NMOS tube, and connects supply voltage through first resistor；Described second
NMOS tube is connected with the drain electrode of the 4th NMOS tube, forms the first tie point, and connect supply voltage through second resistance；
The negative input end of one termination differential input signal of 3rd resistor, the other end connect differential input signal through the 4th resistance
Positive input terminal, the tie point of 3rd resistor and the 4th resistance is connected with the grid of the 5th NMOS tube and the 6th NMOS tube, the 5th
NMOS tube is connected with the source electrode of the 6th NMOS tube, and is grounded through third constant-current source, the drain electrode of the 5th NMOS tube and the 6th NMOS tube
Supply voltage is connect through the 5th resistance and the 6th resistance respectively, wherein the 6th NMOS tube is connect with the tie point of the 6th resistance for second
Point；
First tie point and the second tie point are respectively connected to two input terminals of comparator, export comparison result VOUT.
In the above-mentioned technical solutions, first NMOS tube is identical as the third NMOS tube size, the 2nd NMOS
Manage identical with the 4th NMOS tube size, and the size of second NMOS tube and the 4th NMOS tube is respectively described the
N times of one NMOS tube and the third NMOS tube size, the n of the 6th NMOS tube having a size of the 5th NMOS tube size
Times.
In the above-mentioned technical solutions, first constant-current source and second constant-current source 115 are set as ISS, the third perseverance
Stream source is set as ISET；The second resistance is set as RP, the 3rd resistor is identical as the 4th resistance, and the 6th resistance is set
For RS；First tie point is set as VPEAK, second tie point is set as VSET。
In the above-mentioned technical solutions, it is assumed that when difference input signal amplitude increases to some particular value, described first is permanent
The electric current in stream source all flows to second NMOS tube, that is, meets following formula (1) and formula (2), wherein ID1And ID2Respectively
The drain terminal electric current of first NMOS tube and second NMOS tube, VGS1And VGS2Respectively described first NMOS tube and described
The gate source voltage of two NMOS tubes is poor,
Formula (2) evolution subtracts formula (1) evolution, enables VGS2-VGS1=VID>=0, it can be obtained,
Formula (3) has actually been bigger differential signal, and all analyses and calculating are only limitted to small signal below,
I.e.Following formula (4) and (5) similarly can be obtained for small signal, wherein Δ ID2>=0 is second NMOS tube
Drain terminal current variation value, as difference input signal amplitude VIDWhen being 0, ID1=ISS/ (n+1), ID2=n*ISS/ (n+1), has
Formula (5) evolution subtracts formula (4) evolution, can obtain,
The solution that equation is greater than 0 can be obtained by formula (6),
Similarly, for the third NMOS tube and the 4th NMOS tube, Δ ID4>=0 is the drain terminal of the 4th NMOS tube
Current variation value has
Pass through VGS3-VGS4=VID, the solution greater than 0 can be obtained,
First tie point V can be calculated by formula (7) and formula (10)PEAKThe variation of voltage value is,
ΔVPEAKAs circuit Single-end output amplitude, it can be seen that, as difference input signal amplitude VIDIt is single-ended defeated when being 0
Amplitude, ao V outPEAKIt is 0, with differential input signal amplitude VIDIncrease, Single-end output amplitude, ao VPEAKIt is stepped up, by public affairs
Formula (11) is as can be seen that by being arranged suitable RPValue, can make the gain of circuit, i.e.,Therefore for difference
Small signal detection not enough will not can not detect the amplitude of differential small-signal because of gain,
It is calculated below as the differential input signal amplitude VIDWhen being 0, the first tie point VPEAKVoltage and
The second tie point VSETVoltage,
(work as VID=0) (12)
Formula (13) subtracts formula (12), can obtain
By formula (14) it is found that passing through the third constant-current source ISETWith the 6th resistance RSThe amplitude of settable circuit
Detection threshold value Δ Vth。
It in the above-mentioned technical solutions, further include fourth constant-current source in parallel with the third constant-current source, the 4th constant current
The source electrode of one termination the 5th NMOS tube in source and the source electrode of the 6th NMOS tube, other end ground connection, the 4th constant current
Source is set as IHYS, on-off controlled by the VOUT.
It in the above-mentioned technical solutions, further include respectively the in parallel with first constant-current source and second constant-current source the 5th
Constant-current source and the 6th constant-current source, the source electrode of termination first NMOS tube of the 5th constant-current source and second NMOS tube
Source electrode, the other end ground connection；The source electrode of the one termination third NMOS tube of the 6th constant-current source and the 4th NMOS tube
Source electrode, the other end ground connection, the 5th constant-current source and the 6th constant-current source are set as IHYS, the 5th constant-current source and institute
The on-off for stating the 6th constant-current source is controlled by the VOUT.
In the above-mentioned technical solutions, the replacement of NPN pipe can be used in all NMOS tubes in BiCMOS or Bipolar technique.
While differential signal is converted into single-ended nonpolarity output signal by the present invention, this signal is amplified, so that
Single-end output amplitude can follow differential input signal amplitude, even higher, therefore under differential small-signal mode, also can be into
The normal amplitude detection of row, differential signal amplitude detection circuit of the present invention, structure is simple, and area occupied is small, low in energy consumption,
The other differential small-signal of millivolt level can be effectively detected, applicable surface is very wide.
Detailed description of the invention
Fig. 1 is a kind of differential signal amplitude detection circuit figure that the embodiment of the present invention one provides；
Fig. 2 is traditional differential signal amplitude detection circuit figure；
Fig. 3 is a kind of differential signal amplitude detection circuit figure provided by Embodiment 2 of the present invention；
Fig. 4 is a kind of differential signal amplitude detection circuit figure that the embodiment of the present invention three provides.
Specific embodiment
By the present invention in that with two groups of asymmetrical cascode grades or common-source stage circuit and connecing, differential input signal is converted into
While single-ended nonpolarity output signal, this signal is amplified, enables Single-end output amplitude that Differential Input is followed to believe
Number amplitude, it is even higher, therefore normal amplitude detection is also able to carry out under differential small-signal mode.The present invention can be
CMOS (Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductor) technique or
It is realized in BiCMOS (Bipolar CMOS is CMOS and bipolar device while being integrated on same chip technology) technique.
The present invention is described in detail with specific embodiment with reference to the accompanying drawings of the specification.
As shown in Figure 1, for a kind of differential signal amplitude detection circuit figure that the embodiment of the present invention one provides, circuit structure
It is as follows：
The grid of first NMOS tube 101 and the second NMOS tube 102 connect respectively differential input signal negative input end (VIN) and
Positive input terminal (VIP), the first NMOS tube 101 are connected with the source electrode of the second NMOS tube 102, and are grounded through the first constant-current source 114；
The grid of third NMOS tube 103 and the 4th NMOS tube 104 connects the positive input terminal of differential input signal respectively and bears defeated
Enter end, third NMOS tube 103 is connected with the source electrode of the 4th NMOS tube 104, and is grounded through the second constant-current source 115；
First NMOS tube 101 is connected with the drain electrode of third NMOS tube 103, and connects supply voltage through first resistor 107；Second
NMOS tube 102 is connected with the drain electrode of the 4th NMOS tube 104, forms the first tie point, and connect supply voltage through second resistance 108；
The negative input end of one termination differential input signal of 3rd resistor 109, it is defeated that the other end through the 4th resistance 110 connects difference
Enter the positive input terminal of signal, the tie point and the 5th NMOS tube 105 and the 6th NMOS tube of 3rd resistor 109 and the 4th resistance 110
106 grid is connected, and the 5th NMOS tube 105 is connected with the source electrode of the 6th NMOS tube 106, and is grounded through third constant-current source 116, the
The drain electrode of five NMOS tubes 105 and the 6th NMOS tube 106 connects supply voltage through the 5th resistance 111 and the 6th resistance 112 respectively, wherein
The tie point of 6th NMOS tube 106 and the 6th resistance 112 is the second tie point；
First tie point and the second tie point are respectively connected to two input terminals of comparator 113, export comparison result VOUT.
In above-described embodiment one, the first NMOS tube 101 is identical as 103 size of third NMOS tube, the second NMOS tube 102 with
4th NMOS tube, 104 size is identical, and the size of the second NMOS tube 102 and the 4th NMOS tube 104 is respectively the first NMOS tube
101 with n times of 103 size of third NMOS tube, n times having a size of 105 size of the 5th NMOS tube of the 6th NMOS tube 106；First is permanent
Stream source 114 and the second constant-current source 115 are set as ISS, third constant-current source 116 is set as ISET；Second resistance 108 is set as RP, third electricity
Resistance 109 is identical as the 4th resistance 110, and the 6th resistance 112 is set as RS；First tie point is set as VPEAK, the second tie point is set as VSET；
Wherein, the replacement of NPN pipe can be used in all NMOS tubes in the present invention in BiCMOS or Bipolar technique, no longer superfluous herein
It states.
Ignore bulk effect and channel-length modulation, ensures NMOS tube work in saturation region, through dividing by rationally designing
Analysis is it is found that the first tie point VPEAKVoltage it is unrelated with the polarity of differential input signal, following analysis calculate all assume VIP be
Positive input terminal, VIN are negative input end：
Assuming that the electric current of the first constant-current source 114 all flows to when difference input signal amplitude increases to some particular value
Second NMOS tube 102 meets following formula (1) and formula (2), wherein ID1And ID2Respectively the first NMOS tube 101 and second
The drain terminal electric current of NMOS tube 102, VGS1And VGS2The respectively gate source voltage of the first NMOS tube 101 and the second NMOS tube 102 is poor,
Formula (2) evolution subtracts formula (1) evolution, enables VGS2-VGS1=VID>=0, it can be obtained,
Formula (3) has actually been bigger differential signal, and all analyses and calculating are only limitted to small signal below,
I.e.Following formula (4) and formula (5) similarly can be obtained for small signal, wherein Δ ID2>=0 is the 2nd NMOS
The drain terminal current variation value of pipe 102, as difference input signal amplitude VIDWhen being 0, ID1=ISS/ (n+1), ID2=n*ISS/(n+
1), have
Formula (5) evolution subtracts formula (4) evolution, can obtain,
The solution that equation is greater than 0 can be obtained by formula (6),
Similarly, for third NMOS tube 103 and the 4th NMOS tube 104, Δ ID4>=0 is electric for the drain terminal of the 4th NMOS tube 104
Changing value is flowed, is had
Pass through VGS3-VGS4=VID, the solution greater than 0 can be obtained,
First tie point V can be calculated by formula (7) and formula (10)PEAKThe variation of voltage value is,
ΔVPEAKAs circuit Single-end output amplitude, it can be seen that, as difference input signal amplitude VIDIt is single-ended defeated when being 0
Amplitude, ao V outPEAKIt is 0, with differential input signal amplitude VIDIncrease, Single-end output amplitude, ao VPEAKIt is stepped up, by public affairs
Formula (11) is as can be seen that by being arranged suitable RPValue, can make the gain of circuit, i.e.,Therefore for difference
Small signal detection not enough will not can not detect the amplitude of differential small-signal because of gain.
It is calculated below as difference input signal amplitude VIDFirst tie point V when being 0PEAKVoltage and the second tie point
VSETVoltage,
(work as VID=0) (12)
Formula (13) subtracts formula (12), can obtain
By formula (14) it is found that passing through third constant-current source ISETWith the 6th resistance RSThe amplitude detection threshold of settable circuit
ΔVth。
As shown in Fig. 2, can be close when differential input signal is larger for traditional differential signal amplitude detection circuit figure
It is seemingly source follower, tie point VPEAKEnd gain is consistently less than 1, and when differential input signal is very small, constant-current source ISSIt keeps
It is constant, i.e. gmΔVgs1+gmΔVgs2=0, Δ V can be calculatedPEAK=0, tie point VPEAKHold voltage almost unchanged, gain connects
Close is 0, therefore can not carry out the detection by a small margin of differential signal.
As shown in figure 3, being a kind of differential signal amplitude detection circuit figure provided by Embodiment 2 of the present invention, circuit structure
With in embodiment one circuit structure the difference is that：Embodiment two increase on the basis of circuit diagram in example 1 one with
The 4th constant-current source 117 in parallel of third constant-current source 116, the source electrode of the 5th NMOS tube 105 of termination of the 4th constant-current source 117 and the
The source electrode of six NMOS tubes 106, other end ground connection, the 4th constant-current source 117 are set as IHYS, the on-off of the 4th constant-current source 117 believed by output
Number VOUT control, can analyze by formula (14) and obtains, when VOUT from 0 to 1 overturning or from 1 to when 0 overturning, can change difference
The threshold value of signal amplitude detection circuit thus forms the retarding window of amplitude detection, can avoid the interference of noise significantly, mention
The stability and practicability of high circuit.Wherein, the NMOS tube in embodiment two can use in BiCMOS or Bipolar technique
NPN pipe replaces, and details are not described herein again.
As shown in figure 4, for a kind of differential signal amplitude detection circuit figure that the embodiment of the present invention three provides, circuit structure
With in embodiment one circuit structure the difference is that：Embodiment three increase on the basis of circuit diagram in example 1 two by
The 5th constant-current source 118 and the 6th constant-current source 119 of output signal VOUT control, the 5th constant-current source 118 and the 6th constant-current source 119 divide
It is not in parallel with the first constant-current source 114 and the second constant-current source 115, the source electrode of first NMOS tube 101 of termination of the 5th constant-current source 118
With the source electrode of the second NMOS tube 102, other end ground connection, the source electrode and the of a termination third NMOS tube 103 of the 6th constant-current source 119
The source electrode of four NMOS tubes 104, other end ground connection, the 5th constant-current source 118 and the 6th constant-current source 119 are set as IHYS, the 5th constant-current source
118 and the 6th the on-off of constant-current source 119 controlled by output signal VOUT.Wherein, the NMOS tube in embodiment three in BiCMOS or
It can be replaced using NPN pipe in Bipolar technique, details are not described herein again.
By the present invention in that with two groups of asymmetrical cascode grades or common-source stage circuit and connecing, differential input signal is converted into
While single-ended nonpolarity output signal, this signal is amplified, enables Single-end output amplitude that Differential Input is followed to believe
Number amplitude, it is even higher, therefore under differential small-signal mode, it is also able to carry out normal amplitude detection, it is of the present invention
Differential signal amplitude detection circuit, structure is simple, and area occupied is small, low in energy consumption, and it is small can effectively to detect the other difference of millivolt level
Signal, applicable surface are very wide.
The present invention is not limited to above-mentioned preferred forms, anyone structure change made under the inspiration of the present invention,
The technical schemes that are same or similar to the present invention are fallen within the scope of protection of the present invention.It should be noted that
The term used in embodiments of the present invention is only to be not intended to limit the invention merely for for the purpose of describing particular embodiments.
Packet is also intended in the embodiment of the present invention and the "an" of singular used in the attached claims, " described " and "the"
Most forms are included, unless the context clearly indicates other meaning.It is also understood that term "and/or" used herein is
Refer to and includes that one or more associated any or all of project listed may combine.
Claims (7)
1. a kind of differential signal amplitude detection circuit, which is characterized in that the grid of the first NMOS tube and the second NMOS tube connects respectively
The negative input end and positive input terminal of differential input signal, the first NMOS tube are connected with the source electrode of the second NMOS tube, and through the first perseverance
Stream source ground connection；
The grid of third NMOS tube and the 4th NMOS tube connects the positive input terminal and negative input end of differential input signal, third respectively
NMOS tube is connected with the source electrode of the 4th NMOS tube, and is grounded through the second constant-current source；
First NMOS tube is connected with the drain electrode of third NMOS tube, and connects supply voltage through first resistor；2nd NMOS
The drain electrode of tetra- NMOS tube of Guan Yu is connected, and forms the first tie point, and connect supply voltage through second resistance；
The negative input end of one termination differential input signal of 3rd resistor, the other end are connecing differential input signal just through the 4th resistance
The tie point of input terminal, 3rd resistor and the 4th resistance is connected with the grid of the 5th NMOS tube and the 6th NMOS tube, the 5th NMOS
Pipe is connected with the source electrode of the 6th NMOS tube, and is grounded through third constant-current source, the drain electrode difference of the 5th NMOS tube and the 6th NMOS tube
Supply voltage is connect through the 5th resistance and the 6th resistance, wherein the tie point of the 6th NMOS tube and the 6th resistance is the second tie point；
First tie point and the second tie point are respectively connected to two input terminals of comparator, export comparison result VOUT.
2. differential signal amplitude detection circuit as described in claim 1, which is characterized in that first NMOS tube and described the
Three NMOS tube sizes are identical, and second NMOS tube is identical as the 4th NMOS tube size, and second NMOS tube and institute
The size for stating the 4th NMOS tube is respectively n times of first NMOS tube and the third NMOS tube size, the 6th NMOS
Pipe size is n times of the 5th NMOS tube size.
3. differential signal amplitude detection circuit as claimed in claim 2, which is characterized in that first constant-current source and described the
Two constant-current sources are set as ISS, the third constant-current source is set as ISET；The second resistance is set as RP, the 3rd resistor with it is described
4th resistance is identical, and the 6th resistance is set as RS；First tie point is set as VPEAK, second tie point is set as VSET。
4. differential signal amplitude detection circuit as claimed in claim 3, which is characterized in that assuming that working as difference input signal amplitude
When increasing to some particular value, the electric current of first constant-current source all flows to second NMOS tube, that is, meets following formula
(1) and formula (2), wherein ID1And ID2The drain terminal electric current of respectively described first NMOS tube and second NMOS tube, VGS1With
VGS2The gate source voltage of respectively described first NMOS tube and second NMOS tube is poor,
Formula (2) evolution subtracts formula (1) evolution, enables VGS2-VGS1=VID>=0, it can be obtained,
Formula (3) has actually been bigger differential signal, and all analyses and calculating are only limitted to small signal below, i.e.,Following formula (4) and (5) similarly can be obtained for small signal, wherein Δ ID2>=0 is second NMOS tube
Drain terminal current variation value, as difference input signal amplitude VIDWhen being 0, ID1=ISS/ (n+1), ID2=n*ISS/ (n+1), has
Formula (5) evolution subtracts formula (4) evolution, can obtain,
The solution that equation is greater than 0 can be obtained by formula (6),
Similarly, for the third NMOS tube and the 4th NMOS tube, Δ ID4>=0 is the drain terminal electric current of the 4th NMOS tube
Changing value has
Pass through VGS3-VGS4=VID, the solution greater than 0 can be obtained,
First tie point V can be calculated by formula (7) and formula (10)PEAKThe variation of voltage value is,
ΔVPEAKAs circuit Single-end output amplitude, it can be seen that, as difference input signal amplitude VIDWhen being 0, Single-end output width
Spend Δ VPEAKIt is 0, with differential input signal amplitude VIDIncrease, Single-end output amplitude, ao VPEAKIt is stepped up, by formula
(11) as can be seen that by the way that suitable R is arrangedPValue, can make the gain of circuit, i.e.,Therefore small for difference
Signal detection not enough will not can not detect the amplitude of differential small-signal because of gain,
It is calculated below as the differential input signal amplitude VIDWhen being 0, the first tie point VPEAKVoltage and described
Second tie point VSETVoltage,
Formula (13) subtracts formula (12), can obtain
By formula (14) it is found that passing through the third constant-current source ISETWith the 6th resistance RSThe amplitude detection threshold of settable circuit
It is worth Δ Vth。
5. differential signal amplitude detection circuit as described in claim 1, which is characterized in that further include and the third constant-current source
The 4th constant-current source in parallel, the source electrode of termination the 5th NMOS tube of the 4th constant-current source and the 6th NMOS tube
Source electrode, other end ground connection, the 4th constant-current source are set as IHYS, on-off controlled by the VOUT.
6. differential signal amplitude detection circuit as described in claim 1, which is characterized in that further include permanent with described first respectively
5th constant-current source and the 6th constant-current source in stream source and second constant-current source parallel connection, a termination described the of the 5th constant-current source
The source electrode of the source electrode of one NMOS tube and second NMOS tube, other end ground connection；One termination described the of the 6th constant-current source
The source electrode of the source electrode of three NMOS tubes and the 4th NMOS tube, other end ground connection, the 5th constant-current source and the 6th constant current
Source is set as IHYS, the on-off of the 5th constant-current source and the 6th constant-current source controlled by the VOUT.
7. differential signal amplitude detection circuit as described in claim 1, which is characterized in that all NMOS tubes in BiCMOS or
The replacement of NPN pipe can be used in Bipolar technique.
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