CN1056470C

CN1056470C - Method for making complementary MOS field-effect transistor

Info

Publication number: CN1056470C
Application number: CN96102410A
Authority: CN
Inventors: 王志贤; 陈民良
Original assignee: Promos Technologies Inc
Current assignee: Maode Science and Technology Co., Ltd.
Priority date: 1996-02-15
Filing date: 1996-02-15
Publication date: 2000-09-13
Anticipated expiration: 2016-02-15
Also published as: CN1157484A

Abstract

The present invention relates to a method for making a complementary MOS field-effect transistor by using a double side wall and large-angle ion implantation, which can form an N-channel field-effect transistor and a P-channel field-effect transistor on a silicon substrate. The method comprises the following steps that (a) the silicon substrate provided with a P-type well region, an N-type well region and a plurality of grids is provided; (b) the grids are used as a photomask to form an N-type ion implantation region; (c) a first side wall is formed; (d) a second N-type ion implantation region is formed; (e) a second side wall is formed; (f) a third N-type ion implantation region is formed; (g) a first P-type ion implantation region and a second P-type ion implantation region are formed; (h) an insulation layer is deposited on a field oxide layer and the transistor; (i) a part of the insulation layer is etched to form a contact window.

Description

The manufacture method of CMOS (Complementary Metal Oxide Semiconductor) field-effect transistor

The present invention is characterized in reducing photomask access times in the manufacture process relevant for a kind of manufacture method of utilizing the CMOS (Complementary Metal Oxide Semiconductor) field-effect transistor of double side wall wall (Double Spacer) and ion injection or thick side wall spacers and ion injection.

In semiconductor applications, because component structure tends to miniaturization day by day, therefore meticulous manufacturing method thereof is updated and is developed.

When component size is constantly dwindled, then grid length reduces thereupon, the also constantly reduction of nature raceway groove (channel) length, when channel length when inferior micron is following, promptly produce so-called short-channel effect (Short ChannelEffect), wherein merit attention most with the penetration effect (Punchthrongh Effect) in hot carrier effect in the caused N-channel MOS transistor in short-channel effect (Hot Carrier Effect) and the channel MOS transistor, the generation of hot carrier is because the component size reduction, to such an extent as to hot carrier produced near then the transverse electric field of element can roll up and concentrate on drain electrode if power supply still keeps definite value, in addition, because transverse electric field can make the electronics in the N raceway groove obtain than macro-energy in the element, right to produce electronics electricity hole, wherein the portion of hot carrier is subjected to electric field influence and the injector grid oxide layer, therefore change element limit voltage Vt, the full in addition electric current (saturation current) that closes, transefer conductance (Transconductance), carrier mobility (Carrier Mobility) all effected and reduce or reduce, general conventional art is in lightly doped drain (Light Doped Drain) mode, improve the hot carrier effect in the N-channel MOS transistor, for PMOS, when channel length during less than 0.6 μ m penetration effect just very serious, in addition because hot carrier effect also can make P channel element limit voltage Vt (ThresholdVoltage) change (making 1Vt| reduce), give birth to leakage current and produce, for reducing penetration effect, improve leakage phenomenon, conventional method is removed and is adopted ldd structure, effectively penetrate prevention (Effect Punchthrough Stopper in addition, EPS) structure (or claiming Pocket) can effectively be improved leakage phenomenon.

Below the manufacture method of traditional LDD MOS transistor with N raceway groove and P raceway groove is done an explanation:

(1) provides a P type silicon substrate 1, form an oxysome 2, P type potential well 3, N type potential well 4 and to grow up to its thickness of a grid oxic horizon 5 (Gate Oxide) be 1000 , (seeing Figure 1A).

(2) form first polysilicon layer 6 and mix impurity with the low-pressure chemical vapor phase deposition method, and then form silicon dioxide layer 7, and then use a photomask and define grid, (seeing Figure 1B);

(3) use photomask 8, the ion that carries out N-type LDD with phosphonium ion injects 9, and ion dose is 3E13cm ^-2, ion energy 30KeV is to form N ^-Type LDD impurity injection region 10 (seeing Fig. 1 C);

(4) using photomask 11, is 30KeV with the energy, and concentration is 1E13cm ^-2BF ₂Ion 12 carries out P ^-Type LDD impurity injects, and forms injection region 13 (seeing Fig. 1 D);

(5) after the deposition of dielectric layer, carry out unidirectional etch-back, form side wall spacers 14 with two sides at gate pattern, its thickness is approximately 400 -1000 (seeing Fig. 1 E);

(6) using photomask 15, is 40kev with the energy, and concentration is 4E15cm ^-2Arsenic ion 16 carry out a N ⁺Type impurity injects, and forms injection region 17 (seeing Fig. 1 F);

(7) using photomask 18, is 50Kev with the energy, and concentration is 4E15cm ^-2BF219 carry out a P ⁺Type impurity injects, and forms injection region 20 (seeing Fig. 1 G);

(8) on field oxide and element area, form a silicon dioxide layer that does not mix other ion with CVD (Chemical Vapor Deposition) method (CVD), be referred to as NSG (Neutral Silicate Glass) insulating barrier 21, on insulating barrier 21, contain the silicon dioxide (SiO of boron and phosphorus matter again with CVD method deposit one ₂), form boron phosphorus silicate glass layer (BPSG; Boronphosphosilicate Glass) 22 (seeing Fig. 1 H);

(9) use photomask 23,, make the contact hole pattern of Fig. 1 I with the conventional photomask etching technique.

(10) use photomask 24, with energy 50KeV, concentration 4E15cm ^-2BF225 carry out the 2nd P ⁺Type impurity injects, and forms the ion implanted region 26 (seeing Fig. 1 J) in P type contact hole district;

(11) use photomask 27, with energy 40kev, concentration 4E15cm ^-2Arsenic 28 carry out the 2nd N ⁺Type impurity injects, and forms the ion implanted region 29 (seeing Fig. 1 K) in N type contact hole district;

Because Figure 1A is to Fig. 1 K, we have finished P raceway groove and N raceway groove lightly doped drain (LDD) MOS transistor, are just to finish the LDD structure via seven photomasks.

Because the increase that photomask is used not only increases complexity, cost and the time of manufacturing, in addition also can be owing to extra photomask is used down, the variation of introducing other manufacturing district is (for example: unnecessary particulate), increased the instability of its product performance.Therefore the access times that reduce photomask are very important problems; In addition, above-mentioned traditional manufacture process is not easy to make element Electric Field Distribution optimization, and hot carrier effect is still quite serious.

Therefore, main purpose of the present invention, be to provide a kind of double side wall wall and 20 that utilizes to spend to the manufacture method of the CMOS (Complementary Metal Oxide Semiconductor) field-effect transistor (CMOSFET) of 70 degree ions injections, this method can be utilized at short channel element (Short Channel Device), utilize double side wall wall technology, during suitable alternative condition, can be separate so that form the LDD structural condition of source electrode (Surce) and drain electrode (Drain), it is minimum to interact, to obtain fabulous transistor characteristic, further, utilize again 20 spend to 70 the degree ion implantation techniques can form double side wall wall LDD structure, can favourable minimizing photomask access times, can reduce the complexity of manufacturing, cost and time, in addition, can be owing to the additional light mask is used down, introduce it and make parameter, can effectively reduce the unsteadiness of product performance, therefore, use double side wall wall and 20 to spend the CMOSFET manufacture method of injecting to 70 degree ions, can effectively reduce the hot carrier effect and the penetration effect of element, to obtain transistor characteristic preferably, and reduce and use the photomask number, can make manufacture process greatly simplify.

Another object of the present invention is to provide a kind of utilizes 20 to spend to the manufacture method of the CMOS (Complementary Metal Oxide Semiconductor) field-effect transistor of 70 degree ions injections and thick side wall spacers processing procedure, reduce the photomask number that uses with this manufacture method, make manufacture process greatly simplify and reduce the complexity of processing procedure, can effectively shorten the time of delivery and reduce cost.

Three of the object of the invention is to provide a kind of manufacture method that reduces the CMOS (Complementary Metal Oxide Semiconductor) field-effect transistor of hot carrier effect and penetration effect, utilization can effectively reduce hot carrier effect and penetration effect at short channel element (Short Channel Device).

For achieving the above object, the present invention takes following measure:

The manufacture method of a kind of CMOS (Complementary Metal Oxide Semiconductor) field-effect transistor of the present invention, it can form the N slot field-effect transistor on a silicon substrate, and its step is as follows:

(a) provide a silicon substrate, formed P type potential well, N type potential well, several grids on it at least;

(b) be photomask with these several grids, for the comprehensive N that carries out of silicon substrate ^-Ion 0 is spent to 7 degree and is injected, to form a N type ion implanted region;

(c) form the first side wall wall;

(d) cover desire and form the P-channel field-effect transistor (PEFT) transistor area, carry out a N ⁺Type ion 0 is spent to 7 degree and is injected, to form the 2nd N type ion implanted region;

(e) form second side wall spacers;

(f) cover desire and form the P-channel field-effect transistor (PEFT) transistor area, carry out the 2nd N ⁺Type ion 0 is spent to 7 degree and is injected, and forms the 3rd N type ion implanted region;

(g) cover desire and form N slot field-effect transistor zone, carry out P ^-Type ion 20 is spent to 70 degree and is injected, and forms a P type ion implanted region, carries out P again ⁺Type ion 0 is spent to 7 degree and is injected, and forms the 2nd P type ion implanted region;

(h) on field oxide and transistor unit, deposition insulating layer;

(i) etching part insulating barrier forms contact hole.

The manufacture method of another kind of CMOS (Complementary Metal Oxide Semiconductor) field-effect transistor of the present invention is characterized in that, on a silicon substrate, forms N slot field-effect transistor and P-channel field-effect transistor (PEFT) transistor, and its step is as follows:

(a) provide described silicon substrate, formed P type potential well, N type potential well, several grids on it at least;

(b) form the first side wall wall;

(c) cover desire and form described P-channel field-effect transistor (PEFT) transistor area, carry out N ^-The type ion injects, and the angle between injection direction and the vertical substrates direction is 20 to spend to 70 and spend, to form a N type ion implanted region; And then carry out a N ⁺The type ion injects, and the angle between injection direction and the vertical substrates direction is 0 to spend to 7 and spend, to form the 2nd N type injection region;

(d) form second side wall spacers;

(e) cover desire and form the transistorized zone of P-channel field-effect transistor (PEFT), carry out the 2nd N ⁺The type ion injects, and forms the 3rd N type ion implanted region;

(f) cover desire and form territory, the brilliant area under control of described N channel field-effect, carry out P ^-The type ion injects, and forming a P type ion implanted region, and then carries out P ⁺The type ion injects, to form the 2nd P type ion implanted region;

(g) on field oxide and transistor unit, deposition insulating layer;

(h) etching part insulating barrier is to form contact hole.

Reaching accompanying drawing in conjunction with the embodiments is described as follows manufacture method of the present invention:

Brief Description Of Drawings:

Figure 1A is the manufacture process schematic diagram of the light assorted drain electrode structure CMOS (Complementary Metal Oxide Semiconductor) field-effect transistor of tradition to Fig. 1 K;

Fig. 2 A is the manufacture process schematic diagram of first embodiment of the invention to Fig. 2 J.

Fig. 3 A is the manufacture process schematic diagram of second embodiment of the invention to Figure 31.

Fig. 4 A is the manufacture process schematic diagram of third embodiment of the invention to Fig. 4 H.

At first,, at first provide a P type silicon substrate 151, use traditional isolation technology and form field oxide 152 as conventional process with reference to Fig. 2 A, P type potential well 153, N type potential well 154 grows up to the about 1000A of one deck grid oxic horizon 155 its thickness then.

Please refer to Fig. 2 B, first deposit one gate polysilicon layer, and then form silicon dioxide layer thereon, define polysilicon gate 156 with the conventional photomask etching technique.

To N-channel MOS transistor on the entire substrate 151 and P channel MOS transistor, carry out N then ^-Ion 0 is spent to 7 degree and is injected 158, forms a N type (lightly doped drain LDD); Ion implanted region 159, its injector angle depart between vertical substrates direction O degree to 7 degree, and it is concentration 5E12-5E13cm that employed value is gone into species ^-2, energy is the phosphonium ion of 30-80KeV, please refer to shown in Fig. 2 C.

Finish N ^-After ion injects, form one deck CVD-SiO2 layer again, use anisotropic etching (anisotropic etching) technology etching CVD-SiO2 layer then and form the first side wall wall 160, its thickness is 400 dusts () to 1000 dusts (), please refer to shown in Fig. 2 D.

Please refer to Fig. 2 E, use photomask 161 for the first time, cover desire and form P channel MOS transistor part, carry out a N ⁺Ion 0 is spent to 7 degree values and is gone into 162, and its injector angle departs from vertical substrates direction 0 degree between 7 degree, forms the 2nd N type ion (source/drain) injection region 163, its inject species be energy 60 to 90KeV, concentration is 1E15 to 5E15cm ^-2Arsenic.

Please refer to Fig. 2 F, form one deck CVD insulating barrier in a conventional manner, use anisotropic etching (anisotropic etching) technology etching CVD insulating barrier then, and form second side wall spacers 164, about 800 to 2000 of its side wall spacers width.

Please refer to Fig. 2 G, use photomask 165 for the second time, cover the MOS transistor part that desire forms the P raceway groove, carry out the 2nd N ⁺Type ion 0 is spent to 7 degree and is injected 166, and its injector angle departs from vertical substrates direction 0 degree between 7 degree, forms the 3rd N type (N type contact hole) ion implanted region 167, its inject species be energy 30 to 80KeV, concentration is 3E15 to 6E15cm ^-2Phosphorus.

Please refer to Fig. 2 H, use the 4th photomask 168, cover the MOS transistor part that desire forms the N raceway groove, carry out P ^-Type ion 20 is spent to 70 degree and is injected 169, and its injector angle departs from vertical substrates direction 20 degree between 70 degree, forms a P type ion implanted region 159, and it injects species is that energy is 30 to 120KeV, and concentration is 1E13 to 3E13cm ^-2Boron difluoride (BF ₂); Do not remove photomask, proceed P ⁺Type ion 0 is spent to 7 degree and is injected 170, and its injector angle departs from vertical substrates direction 0 degree between 7 degree, forms the 2nd P type ion implanted region 171, and it injects species energy is 30 to 60KeV, and concentration is 2E15 to 6E15cm ^-2Boron difluoride (BF ₂), wherein, P ^-Type and P ⁺It is commutative that the type ion injects precedence.

Please refer to Figure 21, on oxide layer and element area, form a silicon dioxide insulating layer 172 that does not mix other ion with CVD (Chemical Vapor Deposition) method, on it again with CVD method deposit one have the whole effect of stream boron phosphorus silicate glass 173 (BPSG); Wherein the NSG layer can stop effectively that boron, phosphonium ion in its bpsg layer are diffused into substrate, to avoid its CMOS electrical property influenced.

Please refer to Fig. 2 J, use photomask the 4th time,, make the contact hole pattern of Fig. 2 J with the conventional photomask etching technique.

Please refer to Fig. 3 A, as classical production process, at first we provide a P type silicon substrate 251, and use traditional isolation technology and form field oxide 252, P type potential well 253, N type potential well 254 grows up to about 1000 dusts of one deck grid oxic horizon 255 its thickness then.

Please refer to Fig. 3 B, first deposit one gate polysilicon layer forms silicon dioxide layer then thereon, defines polysilicon gate 256 with the conventional photomask etching technique.

Then, form one deck CVD-SiO2 layer again, use anisotropic etching (anisotropic etching) technology etching CVD-SiO2 layer then and form the first side wall wall 257, its thickness is 400 dust to the 1000 Izod right sides, please refer to shown in Fig. 3 C.

Please refer to Fig. 3 D, application photomask 258 for the first time covers formation P channel MOS transistor part on the substrate 251, carries out N ^-Type ion 20 is spent to 70 degree 259 and is injected, and injector angle departs from vertical substrates direction 20 degree between 70 degree, and employed injection species concentration is 5E12-5E13cm ^-2, energy is the phosphonium ion of 30-80KeV, to form N type (lightly doped drain) ion implanted region 260, carries out a N afterwards again ⁺Type ion 2610 is spent to 7 degree and is injected, and it 0 is spent and mean its injector angle to 7 degree and depart from vertical substrates direction 0 degree between 7 degree, and employed injection species concentration is 1E15-5E15cm ^-2, energy is the arsenic ion of 60-90KeV, to form the 2nd N type ion (source/drain) ion implanted region 262, wherein N ^-A type ion and a N ⁺It is commutative that the type ion injects precedence.

Please refer to Fig. 3 E, form one deck CVD insulating barrier in a conventional manner, use anisotropic etch techniques etching CVD insulating barrier then, and form second side wall spacers 263, about 800 to 2000 of its side wall spacers width.

Please refer to Fig. 3 F, use second photomask 265, cover the MOS transistor part that desire forms the P raceway groove, carry out the 2nd N ⁺Type ion 0 is spent to 7 degree and is injected 264, and its injector angle departs from vertical substrates direction 0 degree between 7 degree, forms the 3rd N type (N type contact hole) ion implanted region 266, and it injects species energy is 30 to 80KeV, and concentration is 3E15 to 6E15cm ^-2Phosphorus.

Please refer to Fig. 3 G, use for the third time photomask 267 and cover that desire forms the N-channel MOS transistor part on the substrate 251, carry out P ^-Type ion 20 is spent to 70 degree 268 and is injected, and its injector angle departs from vertical substrates direction 20 degree between 70 degree, and the injection species concentration of using is 1E13-3E13cm ^-2, energy is the boron difluoride (BF of 30-120KeV ₂) ion, to form a P type ion implanted region 288, carry out P afterwards ⁺Type ion 2690 is spent to 7 degree and is injected, and its implant angle departs from vertical substrates direction 0 degree between 7 degree, employed injection species concentration 2E15-6E15cm ^-2, energy is the BF of 30-60KeV ₂Ion forms the 2nd P type ion implanted region 270, wherein P ^-Type ion and P ⁺It is commutative that the type ion injects precedence.

Please refer to Fig. 3 H, form silicon dioxide (NSG) insulating barrier 271 that does not mix any ion at field oxide and element area with CVD (Chemical Vapor Deposition) method, the boron phosphorus silicate glass layer 272 (BPSG) that has mobilization on it again with CVD method deposit one, wherein the NSG layer can stop effectively that boron, phosphonium ion in its bpsg layer are diffused into substrate, to avoid its CMOS electrical property influenced.

Please refer to Fig. 3 I, use photomask the 4th time,, make the contact hole pattern of Fig. 3 H with the conventional photomask etching technique.

Please refer to Fig. 4 A, as classical production process, at first we provide a P type silicon substrate 351, use traditional isolation technology and form field oxide 352, P type potential well 353, N type potential well 354, the grid oxic horizon 355 of growing up then.

Please refer to Fig. 4 B, deposit one deck gate polysilicon layer, and then form silicon dioxide layer on it, define

polysilicon gate

356a, 356b with the conventional photomask etching technique.

To N-channel MOS transistor on the entire substrate 351 and P channel MOS transistor, carry out N then ^- Ion 20 is spent to 70 degree and is injected 358, and forms N ^-Type lightly doped drain ion implanted

region

359a, 359b, its injector angle depart from vertical substrates direction 20 degree between 70 degree, and employed injection species concentration is E12-5E13cm ^-2, energy is the phosphonium ion of 30-80KeV, please refer to shown in Fig. 4 C.

Finish N ^-After ion injects, form one deck CVD-SiO2 layer again and form

side wall spacers

360a, 360b, its thickness is 2000 dust to the 4000 Izod right sides, and more traditional sidewall spacers layer thickness is thick, please refer to shown in Fig. 4 D.

Please refer to Fig. 4 E, application photomask 361 for the first time covers formation P channel MOS transistor part on the substrate 351, carries out a N ⁺Type ion 20 is spent to 70 degree 362 and is injected, and employed injection species concentration is 1E15-5E15cm ^-2, energy is the arsenic ion of 60-90KeV, to form source/drain ion injection region 380, carries out the 2nd N afterwards again ⁺Ion 3630 is spent to 7 degree and is injected, and it 0 is spent and mean its injector angle to 7 degree and depart from vertical substrates direction 0 degree between 7 degree, and employed injection species concentration is 3E15-6E15cm ^-2, energy is the phosphonium ion of 30-80KeV, to form the ion implanted region 364 in N type ion contact hole district.

Please refer to Fig. 4 F, application photomask 365 for the second time covers desire formation N-channel MOS transistor part on the substrate 351, carries out P ^-Type ion 20 is spent to 70 degree 366 and is injected, and the injection species concentration of using is 1E13-3E13cm ^-2, energy is boron difluoride (BF2) ion of 30-120KeV, to form P type ion implanted region 388, carries out a P afterwards ⁺Type ion 3670 is spent to 7 degree and is injected, and employed injection species are concentration 2E15-6E15cm ^-2, energy is the BF of 30-60KeV ₂Ion, the ion implanted region 368 in formation P type ion contact hole district.

Please refer to Fig. 4 G, form a silicon dioxide (NSG) that does not have a dopant ion with CVD (Chemical Vapor Deposition) method at field oxide and element area; Insulating barrier 369 has the boron phosphorus silicate glass layer 370 (BPSG) of mobilization again with CVD method deposit one on it, wherein, the NSG layer can stop effectively that boron, the phosphonium ion in its bpsg layer is diffused into substrate, to avoid its CMOS Effect on Performance.

Please refer to Fig. 4 H, use photomask for the third time,, make the contact hole pattern of Fig. 4 H with the conventional photomask etching technique.

With respect to located by prior art, the present invention has following effect:

(1) according to located by prior art, needing at least to use seven road photomasks could be complete Become quality good, the CMOS unit of tool LDD structure and contact hole ion implanted region Part, however first and second embodiment according to the present invention are all owing to having used 20 Degree to 70 degree Implantation and double side wall wall processing procedure only need four road photomasks Get final product the same good cmos element of difficulty action accomplishment; In addition, according to the present invention Three embodiment are owing to used 20 degree to 70 degree Implantation and thick sidewall spacers Layer method only needs three road photomasks to get final product the same good CMOS of difficulty action accomplishment Element; Photo mask step reduces, and can reduce the cost of manufacturing;

(2) owing to the use that reduces photomask, so manufacturing time (wor K-in-process time) greatly reduces;

(3) minimizing used of photomask can reduce because of the standard processing procedure and introduce Particulate, the defective of whole wafer also can greatly reduce, this will make product performance comparatively Stable;

(4) according to the resulting element of the present invention, the concentration of its source/drain Very easily reach optimization and obtain good Electric Field Distribution, so that hot carrier effect greatly Improve.

Claims

1, a kind of manufacture method of CMOS (Complementary Metal Oxide Semiconductor) field-effect transistor, it can form the N slot field-effect transistor on a silicon substrate, and its step is as follows:

(c) form the first side wall wall;

(e) form second side wall spacers;

(h) on field oxide and transistor unit, deposition insulating layer;

(i) etching part insulating barrier forms contact hole.

2, manufacture method according to claim 1 is characterized in that, described N ^-The injection direction of ion and perpendicular to the angle between described silicon substrate direction be 0 degree to 7 degree, the energy that injects species is 30 to 80KeV, concentration is 5E12 to 5E13cm ^-2Phosphorus.

3, manufacture method according to claim 1 is characterized in that, the width of described the first side wall wall is between 400 to 1000 .

4, manufacture method according to claim 1 is characterized in that, a described N ⁺Type ion injection direction and perpendicular to the angle between described silicon substrate direction be 0 degree to 7 degree, the energy that injects species is 60 to 90KeV, concentration is 1E15 to 5E15cm ^-2Arsenic.

5, manufacture method according to claim 1 is characterized in that, the width of described second sidewall spacers is between 800 to 2000 .

6, manufacture method according to claim 1 is characterized in that, described the 2nd N ⁺The injection direction of type ion and perpendicular to the angle between described silicon substrate direction be 0 degree to 7 degree, the energy that injects species is 30 to 80KeV, concentration is 3E15 to 6E15cm ^-2Phosphorus.

7, manufacture method according to claim 1 is characterized in that, described the 2nd P ^-The injection direction of type ion and angle between vertical described silicon substrate direction be 20 degree to 70 degree, inject the species energy and be 30 to 120KeV, concentration is the boron difluoride of 1E13 to 3E13.

8, manufacture method according to claim 1 is characterized in that, described P ⁺Type ion injection direction degree and angle between vertical described silicon substrate direction be 0 degree to 7 degree, inject the species energy and be 30 to 60KeV, concentration is the boron difluoride of 2E15 to 6E15.

9, manufacture method according to claim 1 is characterized in that, described injection P ^-Type ion and P ⁺The injection precedence of type ion is commutative.

10, manufacture method according to claim 1 is characterized in that, the described insulating barrier that is deposited on field oxide and the transistor unit is the silicate glass insulating barrier.

11, a kind of manufacture method of CMOS (Complementary Metal Oxide Semiconductor) field-effect transistor is characterized in that, on a silicon substrate, forms N slot field-effect transistor and P-channel field-effect transistor (PEFT) transistor, and its step is as follows:

(b) form the first side wall wall;

(d) form second side wall spacers;

(g) on field oxide and transistor unit, deposition insulating layer;

(h) etching part insulating barrier is to form contact hole.

12, manufacture method according to claim 11 is characterized in that, the width of described the first side wall wall is between 400 to 1000 .

13, manufacture method according to claim 11 is characterized in that, described N ^-The injection direction of type ion and angle between vertical described silicon substrate direction be 20 degree to 70 degree, the species of injection are arsenic, its concentration is 5E12-5E13cm ^-2, it injects energy is 30KeV to 80KeV.

14, manufacture method according to claim 11 is characterized in that, a described N ⁺Type ion injection direction and angle between the vertical described silicon substrate direction be 0 degree to 7 degree, the species of injection are phosphorus, concentration is 1E15 to 5E15cm ^-2, it injects energy is 60KeV to 90KeV.

15, manufacture method according to claim 11 is characterized in that, the width of described second side wall spacers is between 800 to 2000 .

16, manufacture method according to claim 11 is characterized in that, described the 2nd N ⁺Type ion injection direction and angle between vertical described silicon substrate direction be 0 degree to 7 degree, the energy that injects species is 30 to 80KeV, concentration is 3E15 to 6E15cm ^-2Phosphorus.

17, manufacture method according to claim 11 is characterized in that, described P ^-The injection direction of type ion and angle between vertical described silicon substrate direction be 20 degree between 70 degree, the species of injection are boron difluoride BF ₂, implantation concentration is 1E13-3E13cm ^-2, injecting energy is between the 30KeV to 120KeV.

18, manufacture method according to claim 11 is characterized in that, described P ⁺The injection of type ion, its injection direction is 0 to 7 degree with angle between vertical described silicon substrate direction, the species of injection are boron difluoride BF ₂, implantation concentration is 2E15-6E15cm ^-2, injecting energy is between the 30KeV to 60KeV.

19, manufacture method according to claim 11 is characterized in that, the insulating barrier of deposit is the silicon dioxide of boron phosphorus silicate glass layer or any impurity of non-impurity-doped on described field oxide and the transistor unit.

20, manufacture method according to claim 11 is characterized in that, described injection N ^-A type ion and a N ⁺The injection precedence of type ion is commutative.

21, manufacture method according to claim 11 is characterized in that, described injection P ^-Type ion and P ⁺The injection precedence of type ion is commutative.