CN1303657C - Method for manufacturing pMOS for titanium silicide preparing process window - Google Patents
Method for manufacturing pMOS for titanium silicide preparing process window Download PDFInfo
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- CN1303657C CN1303657C CNB2003101229217A CN200310122921A CN1303657C CN 1303657 C CN1303657 C CN 1303657C CN B2003101229217 A CNB2003101229217 A CN B2003101229217A CN 200310122921 A CN200310122921 A CN 200310122921A CN 1303657 C CN1303657 C CN 1303657C
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- Prior art keywords
- pmos
- process window
- titanium silicide
- ion
- manufacturing process
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- 238000000034 method Methods 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 32
- 229910021341 titanium silicide Inorganic materials 0.000 title claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 150000002500 ions Chemical class 0.000 claims abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 9
- 238000005468 ion implantation Methods 0.000 claims abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 229940090044 injection Drugs 0.000 claims description 6
- 238000002347 injection Methods 0.000 claims description 6
- 239000007924 injection Substances 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 239000007943 implant Substances 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 abstract description 6
- 239000004065 semiconductor Substances 0.000 abstract description 6
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- 239000002184 metal Substances 0.000 description 14
- 229910052751 metal Inorganic materials 0.000 description 14
- 229910021332 silicide Inorganic materials 0.000 description 8
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 8
- 230000000694 effects Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 125000004429 atom Chemical group 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 125000005843 halogen group Chemical group 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- WSGDRFHJFJRSFY-UHFFFAOYSA-N 4-oxo-TEMPO Chemical compound CC1(C)CC(=O)CC(C)(C)N1[O] WSGDRFHJFJRSFY-UHFFFAOYSA-N 0.000 description 1
- 206010010144 Completed suicide Diseases 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000005496 tempering Methods 0.000 description 1
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Abstract
The present invention discloses a method for manufacturing P-type metal-oxide semiconductors (pMOS) for a titanium-silicide preparing process window, which comprises the following steps: a substrate with a P well and an N well which are formed in the substrate is provided; then, an oxidization layer is formed on the substrate as a gate oxidization layer; a polycrystalline silicon layer is formed on the gate oxidization layer; the polycrystalline silicon layer and the oxidization layer are etched to respectively form gate structures on the P well and the N well; first gap walls are formed on the side walls of a gate electrode and the gate oxidization layer; ions implanted by an ion implanting method of an oblique angle enter the substrate to form a lightly doped source electrode (LDD), and a second ion implanting method is executed by covering a first light resistor on the N well for manufacturing a drain electrode and a source electrode of an nMOS; then, the first light resistor is removed; second gap walls are formed on the first gap walls; the P well is exposed by covering the N well with a second light resistor to execute a third-time ion implantation for making a source electrode and a drain electrode of the pMOS and removing the second light resistor.
Description
Technical field
The present invention relates to semiconductor subassembly, particularly about a kind of manufacture method that is used for the P-type mos (pMOS) of Titanium silicide manufacture craft window.
Background technology
Semi-conductor industry has been entered rank to ultra-large type integrated circuit (ULSI) technical field, and its dimension has narrowed down to time micron even the size of nanometer.Along with dwindling of size of components, its cost is that ghost effect will cause RC to postpone and increase source electrode and drain series resistance.Hot carrier is for reducing other emphasis of assembly property, and DESCRIPTION OF THE PRIOR ART is doped into multi-crystal silicification metal gates and silicon substrate by an ion implantation with high dose nitrogen, will improve the performance of deep-sub-micrometer assembly.For increasing service speed, aim at metal silicide (salicide) manufacturing process voluntarily by many years of development, this technology is used to reach the purpose that reduces grid, source electrode and drain resistance, service speed is the primary demand of utmost point short channel MOSFET fast, people such as M.T.Takagi propose one and form the method for metal silicide manufacturing process in IEDM, Tech.Dig., p.455,1996; Aim at the metal silicide contact procedure voluntarily and be a general method in order to reduce the resistance of grid, drain electrode and source electrode, for example, one metal level by sputter on base material and grid, under specific range of temperatures, carry out a Rapid Thermal tempering (RTA) so that metal and grid and base material reaction, then, one strip step is used to remove unreacted metal on the gate lateral wall clearance wall, and so, metal silicide layer is aimed at voluntarily and is formed on grid, source electrode and the drain region.But after the Titanium silicide manufacture craft, because bad TiSix-Si interface constitutes, the technical process of Titanium silicide can reduce the performance of pMOS, thereby causes higher interface resistance.(But the Ti-Salicide process can degrade pMOS performance due to formation of poorTiSix-Si interface, resulting in higher interface resistance, after Ti-Salicidation.) so be necessary to propose the P-type mos that a brand-new method making has the Ti metal silicide.
Summary of the invention
Main purpose of the present invention is to provide a kind of manufacture method that is used for the pMOS of Titanium silicide (Ti-salicide) manufacturing process window.
The present invention discloses a kind of pMOS manufacture method of the Ti-salicide of being used for manufacturing process window, and this method comprises the steps: to provide to be had P trap and N trap and be formed at wherein substrate; Form oxide layer on this substrate as a gate oxide; Form a polysilicon layer on this gate oxide; This polysilicon layer of etching and this oxide layer form grid structure respectively on this P trap and this N trap; Form first clearance wall on the sidewall of this grid and this gate oxide; Utilize an ion implantation to inject ion and enter substrate, so form light dope source electrode (LDD) structure adjacent gate; Utilize first photoresist to be covered in and carry out second ion implantation on the n trap to make drain electrode and the source electrode of nMOS; Remove first photoresist afterwards; Form second clearance wall on first clearance wall; Utilize second photoresist to hide this P well area to expose this N well area; Carrying out for the third time, ion injects to make drain electrode and the source electrode of pMOS; And remove this second photoresist.
Description of drawings
Fig. 1 is the sectional view of semi-conductive substrate, illustrates according to the present invention to form the step of a LDD in Semiconductor substrate.
Fig. 2 is the sectional view of semi-conductive substrate, illustrates according to the present invention to form nMOS drain electrode and the step of source electrode in Semiconductor substrate.
Fig. 3 is the sectional view of semi-conductive substrate, and the step that forms second clearance wall according to the present invention is described.
Fig. 4 is the sectional view of semi-conductive substrate, illustrates according to the present invention to form pMOS drain electrode and the step of source electrode in Semiconductor substrate.
Embodiment
The present invention proposes a kind of method to have one in order to manufacturing and aims at P-type mos (pMOS) transistor of metal suicide structure voluntarily, is described in detail as follows, and sees also accompanying drawing.
With reference to figure 1, use to have＜100〉crystallization direction a substrate (substrate) 2 be preferred embodiment, substrate comprises that a plurality of oxide in field (not indicating) and two traps (P trap and N trap) are pre-formed in wherein, and in this embodiment, thick field oxidation (FOX) zone is as the purpose of isolation.One thin oxide layer 4 is formed on the substrate 2 as a gate oxide, and in preferred embodiment, gate oxide 4 is made up of silicon dioxide, utilizes in one oxygen-steam ambient temperature about 800 to 1100 degree Celsius formation down.In preferred embodiment, about 15 to 200 of the thickness of gate oxide 4.Silicon oxide layer 4 utilizes chemical vapour deposition technique to deposit a doped polysilicon layer 6 on gate oxide 4 after forming, then polysilicon layer 6, and oxide layer 4 form grid structure respectively on P trap and N trap with the etching method etching.An oxide layer is formed on the grid structure that comprises grid 6 and gate oxide 4 subsequently, utilizes anisotropic etch process to eat-back oxide layer subsequently, and therefore first clearance wall 8 is formed on the sidewall of grid structure.With reference to figure 1, utilize an ion implantation to inject ion and enter substrate, so form light dope source electrode (LDD) structure 10 adjacent gate structures, this LDD injects sheet and uses phosphorus to inject sheet (minimizing break-through) as nMOS LDD injection sheet (minimizing hot carrier effect) and pMOS Halo.(This LDD implant uses " Phosphorus " to serve as nMOS LDDimplant (reduce hot carrier effect) and pMOS Halo implant (reduce punch through.) in addition, because above-mentioned technology is carried out on whole wafer, lithographic printing has not just needed.(Furthermore, nolitho step is needed since it is done on the whole wafer.) energy and implantation dosage are respectively about 20～200KeV and 1E12～1E15 atom/square centimeter (The dosage is～1E12～1E151/cm^2, energy 20～200KeV) this implant angle is about the 0-60 degree.
As shown in Figure 2, carry out a high dose ion injection method and go into the substrate 2 of P trap to inject ion, a photoresist 12 is covered on the N trap as shown in the figure.This injects drain electrode and the source electrode 14 that forms nMOS.Energy and implantation dosage are respectively approximately as previously mentioned or P5 to 200KeV and 1E13 to 1E16 atom/square centimeter.Remove photoresist afterwards.Be connected on first clearance wall (spacer) 8 and make second clearance wall 16, in like manner, also adopt the deposit dielectric film after, utilize etching technique to make, as shown in Figure 3.
Then consult Fig. 4, utilize second photoresist 18 to hide the P well area to expose the N well area.Carrying out for the third time at last, ion injects drain electrode and the source electrode 20 of making PMOS.Remove photoresist 18 afterwards.Energy and implantation dosage are respectively about B2 to 40KeV and 1E13 to 1E16 atom/square centimeter.The method can provide darker p+ to inject, darker closeer P+S/D helps to reduce the TiSix-Si interface resistance, second clearance wall provides longer pMOS channel length, and this is darker to reduce/short-channel effect that closeer P+S/D causes, thereby (The deeper and denser P+S/D can help to reduceTiSix-Si interface resistance, and the 2 have been improved
NdSpacer provides longer pMOS channel lengthto reduce short channel effect by this deeper/denser P+S/D, thus improving the) the manufacturing process window (Ti salicide process window) of Titanium silicide.
Subsequent step can comprise Ti salicide technical process.Aiming at metal silicide (SALICIDE) technology voluntarily is used to reduce the resistance of grid, source electrode and drain electrode.Make the reaction of metal and polysilicon and substrate form metal silicide layer in grid, source electrode and drain electrode than specified temp one, thus metal silicide respectively voluntarily aligning be formed on grid and the substrate.
The present invention with preferred embodiment explanation as above; only be used for helping to understand enforcement of the present invention; non-in order to limit protection scope of the present invention; and the technical staff who is familiar with this field is after comprehension content of the present invention; in not breaking away from spiritual scope of the present invention; replace when the variation that can do a little change retouching and be equal to, its scope of patent protection should be as the criterion with claims institute restricted portion.
Claims (8)
1. pMOS manufacture method that is used for Titanium silicide manufacturing process window, this method comprises the steps:
Provide and have P trap and N trap and be formed at wherein substrate;
Form oxide layer on this substrate as a gate oxide;
Form a polysilicon layer on this gate oxide;
This polysilicon layer of etching and this oxide layer form grid structure respectively on this P trap and this N trap;
Form first clearance wall on the sidewall of this grid and this gate oxide; Utilize an ion implantation to inject ion and enter substrate, so form lightly-doped source electrode structure adjacent gate;
Utilize first photoresist to be covered in and carry out second ion implantation on the N trap to make drain electrode and the source electrode of nMOS;
Remove first photoresist;
Form second clearance wall on first clearance wall;
Utilize second photoresist to hide this P well area to expose this N well area;
Carrying out for the third time, ion injects to make drain electrode and the source electrode of pMOS; And
Remove this second photoresist.
2. the pMOS manufacture method that is used for Titanium silicide manufacturing process window as claimed in claim 1 is characterized in that, the energy that described first time, ion injected is 20 to 200KeV.
3. the pMOS manufacture method that is used for Titanium silicide manufacturing process window as claimed in claim 1 is characterized in that, the dosage that the described first time, ion injected is 1E12 to 1E15 atom/square centimeter.
4. the pMOS manufacture method that is used for Titanium silicide manufacturing process window as claimed in claim 1 is characterized in that, the implant angle that the described first time, ion injected is the 0-60 degree.
5. the pMOS manufacture method that is used for Titanium silicide manufacturing process window as claimed in claim 1 is characterized in that, the energy that described second time, ion injected is 5 to 200KeV.
6. the pMOS manufacture method that is used for Titanium silicide manufacturing process window as claimed in claim 1 is characterized in that, the dosage that the described second time, ion injected is 1E13 to 1E16 atom/square centimeter.
7. the pMOS manufacture method that is used for Titanium silicide manufacturing process window as claimed in claim 1 is characterized in that, described ion implantation energy for the third time is 2 to 40KeV.
8. the pMOS manufacture method that is used for Titanium silicide manufacturing process window as claimed in claim 1 is characterized in that, the dosage that described ion for the third time injects is 1E13 to 1E16 atom/square centimeter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101229217A CN1303657C (en) | 2003-12-29 | 2003-12-29 | Method for manufacturing pMOS for titanium silicide preparing process window |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101229217A CN1303657C (en) | 2003-12-29 | 2003-12-29 | Method for manufacturing pMOS for titanium silicide preparing process window |
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| Publication Number | Publication Date |
|---|---|
| CN1635617A CN1635617A (en) | 2005-07-06 |
| CN1303657C true CN1303657C (en) | 2007-03-07 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2003101229217A Expired - Lifetime CN1303657C (en) | 2003-12-29 | 2003-12-29 | Method for manufacturing pMOS for titanium silicide preparing process window |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102315131B (en) * | 2011-09-28 | 2016-03-09 | 上海华虹宏力半导体制造有限公司 | The manufacture method of transistor |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5081518A (en) * | 1989-05-24 | 1992-01-14 | National Semiconductor Corporation | Use of a polysilicon layer for local interconnect in a CMOS or BICMOS technology incorporating sidewall spacers |
| CN1157484A (en) * | 1996-02-15 | 1997-08-20 | 台湾茂矽电子股份有限公司 | Method for making complementary MOS field-effect transistor |
| CN1188982A (en) * | 1997-01-20 | 1998-07-29 | 日本电气株式会社 | Semiconductor device and method for producing same |
| JP2001267558A (en) * | 2000-03-16 | 2001-09-28 | Matsushita Electric Ind Co Ltd | Method of manufacturing for semiconductor device |
-
2003
- 2003-12-29 CN CNB2003101229217A patent/CN1303657C/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5081518A (en) * | 1989-05-24 | 1992-01-14 | National Semiconductor Corporation | Use of a polysilicon layer for local interconnect in a CMOS or BICMOS technology incorporating sidewall spacers |
| CN1157484A (en) * | 1996-02-15 | 1997-08-20 | 台湾茂矽电子股份有限公司 | Method for making complementary MOS field-effect transistor |
| CN1188982A (en) * | 1997-01-20 | 1998-07-29 | 日本电气株式会社 | Semiconductor device and method for producing same |
| JP2001267558A (en) * | 2000-03-16 | 2001-09-28 | Matsushita Electric Ind Co Ltd | Method of manufacturing for semiconductor device |
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| CN1635617A (en) | 2005-07-06 |
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Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING Effective date: 20111205 |
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Effective date of registration: 20111205 Address after: 201203 Shanghai Zhangjiang Road, Zhangjiang High Tech Park of Pudong New Area No. 18 Co-patentee after: Semiconductor Manufacturing International (Beijing) Corp. Patentee after: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) Corp. Address before: 201203 Shanghai Zhangjiang Road, Zhangjiang High Tech Park of Pudong New Area No. 18 Patentee before: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) Corp. |
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Granted publication date: 20070307 |