CN105634471B - A kind of counter filtered - Google Patents
A kind of counter filtered Download PDFInfo
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- CN105634471B CN105634471B CN201511001553.XA CN201511001553A CN105634471B CN 105634471 B CN105634471 B CN 105634471B CN 201511001553 A CN201511001553 A CN 201511001553A CN 105634471 B CN105634471 B CN 105634471B
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- counter
- etv
- filter
- count
- filtered
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K21/00—Details of pulse counters or frequency dividers
- H03K21/02—Input circuits
Abstract
The invention discloses a kind of counter filtered, including two-way I/O port PAD, synchronous circuit, filter circuit and counter, the two-way I/O port PAD is sequentially connected synchronous circuit, filter circuit and counter.The shake of waveform when the present invention is by level transitions is filtered, and to make counter correctly be worked, filters signal jitter, counter is made correctly to count, and is simplified program, is reduced the workload of operation of mcu.
Description
Technical field
The present invention relates to a kind of counter, specifically a kind of counter filtered.
Background technology
With the rapid rising of smart home, conventional one-piece machine central processing unit（mcu）The independent peripheral integrated counts
General ability is sex-limited increasing, is limited in that and a large amount of software program deallocation total number device is needed to work, increase software
Complexity, and the resource of central processing unit is occupied, to reduce the speed of service of algorithm.
For using counter tally function when, since external input signal can be shaken in level transitions,
Counter miscount is caused, to influence the program operation of whole system, traditional solution is exactly to need in program
Face adds a delay process, causes mcu that cannot go to handle other algorithms in time.
Invention content
The purpose of the present invention is to provide a kind of counters filtered, to solve mentioned above in the background art ask
Topic.
To achieve the above object, the present invention provides the following technical solutions：
A kind of counter filtered, including two-way I/O port PAD, synchronous circuit, filter circuit and counter, it is described two-way
I/O port PAD is sequentially connected synchronous circuit, filter circuit and counter.
As a further solution of the present invention：The input signal of the two-way I/O port PAD obtains after synchronous circuit
Etv_in signals indicate the clock clk1 of counter without being divided, when frequency dividing psc is other in advance as frequency dividing psc=0 in advance
When value, the clock of counter carries out psc+1 and divides to obtain clk2, clk1 and clk2 when obtaining clk_cnt by a selector
Clock；As 32 filter width N=0, indicate that etv_in signals are a clean signals without being filtered；When 32 filtering are wide
When spending N not equal to 0, indicates to open filter function, use clock clk_cnt continuous samplings to N+1 etv_in；It is filtered opening
When, etv_in obtains etv_in_reg after a register, when etv_in is not equal to etv_in_reg, filter
Count automatic clears or count add one when each clk_cnt rising edge arrives, until count is equal to 32 filtering
When width N, it is assumed that current etv_in_reg is an effective signal, and count automatic clears；It is effective when obtaining one
Etv_in_reg signals, it will be able to be rising edge/failing edge according to the configuration of counter, counter adds one/subtracts one.
As further scheme of the invention：It is opened when counter enables cen signals, two-way I/O port PAD automatically switches
At input state.
Compared with prior art, the beneficial effects of the invention are as follows：The shake of waveform when the present invention is by level transitions carries out
Filtering, to make counter correctly be worked, filters signal jitter, counter is made correctly to count, and simplifies program, reduces mcu
Workload of operation.
Description of the drawings
Fig. 1 is the structural schematic diagram for the counter that can be filtered.
Specific implementation mode
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation describes, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
Referring to Fig. 1, in the embodiment of the present invention, a kind of counter filtered, including two-way I/O port PAD, synchronous circuit,
Filter circuit and counter, the two-way I/O port PAD are sequentially connected synchronous circuit, filter circuit and counter.
The input signal of the two-way I/O port PAD obtains etv_in signals after synchronous circuit, when pre- frequency dividing psc=0
When, the clock clk1 of counter is indicated without being divided, and when frequency dividing psc is other values in advance, the clock of counter carries out psc
+ 1 frequency dividing obtains clk2, clk1 and clk2 and obtains clk_cnt clocks by a selector；As 32 filter width N=0, table
Show that etv_in signals are a clean signals without being filtered；When 32 filter width N are not equal to 0, indicate to open filtering
Function uses clock clk_cnt continuous samplings to N+1 etv_in；When opening filtering, etv_in is after a register
Etv_in_reg is obtained, when etv_in is not equal to etv_in_reg, the count automatic clears or count of filter are every
One clk_cnt rising edge adds one when arriving, when count is equal to 32 filter width N, it is assumed that current etv_in_reg
It is an effective signal, and count automatic clears；When obtaining an effective etv_in_reg signal, it will be able to according to
The configuration of counter, is rising edge/failing edge, and counter adds one/subtracts one.
It is opened when counter enables cen signals, two-way I/O port PAD automatically switches into input state.
The present invention operation principle be：Referring to Fig. 1, the basic function of counter of the present invention include 32 upwards plus/to
Lower down counter（cnt）, 32 pre- frequency dividings（psc）, 32 filter widths (N).
Innovation of the present invention is increasing filter circuit, filters signal jitter, and counter is made correctly to count, and simplifies journey
Sequence reduces the workload of operation of mcu.
1, PAD is a two-way I/O port, is opened when counter enables cen signals, PAD automatically switches into input state；
2, PAD input signals can eliminate metastable state after synchronous circuit, obtain etv_in signals；
3, as psc=0, indicate the clock clk1 of counter without being divided, when other values, the clock of counter into
Row psc+1 divides to obtain clk2, clk1 and clk2 obtains clk_cnt clocks by a selector；
4, as N=0, indicate that etv_in signals are a clean signals without being filtered；
5, it when N is not equal to 0, indicates to open filter function, uses clock clk_cnt continuous samplings to N+1 etv_in
6, when opening filtering, etv_in obtains etv_in_reg after a register, when etv_in is not equal to
When etv_in_reg, the count automatic clears or count of filter add one when each clk_cnt rising edge arrives,
When count is equal to N, it is assumed that current etv_in_reg is an effective signal, and count automatic clears；When
To an effective etv_in_reg signal, so that it may according to the configuration of counter, to be rising edge/failing edge, counter adds one/
Subtract one.
It is obvious to a person skilled in the art that invention is not limited to the details of the above exemplary embodiments, Er Qie
In the case of without departing substantially from spirit or essential attributes of the invention, the present invention can be realized in other specific forms.Therefore, no matter
From the point of view of which point, the present embodiments are to be considered as illustrative and not restrictive, and the scope of the present invention is by appended power
Profit requires rather than above description limits, it is intended that all by what is fallen within the meaning and scope of the equivalent requirements of the claims
Variation is included within the present invention.Any reference signs in the claims should not be construed as limiting the involved claims.
In addition, it should be understood that although this specification is described in terms of embodiments, but not each embodiment is only wrapped
Containing an independent technical solution, this description of the specification is merely for the sake of clarity, and those skilled in the art should
It considers the specification as a whole, the technical solutions in the various embodiments may also be suitably combined, forms those skilled in the art
The other embodiment being appreciated that.
Claims (2)
1. a kind of counter filtered, including two-way I/O port PAD, synchronous circuit, filter circuit and counter, feature exist
In the two-way I/O port PAD is sequentially connected synchronous circuit, filter circuit and counter；The input signal of the two-way I/O port PAD
After synchronous circuit, etv_in signals are obtained, as frequency dividing psc=0 in advance, indicate the clock clk1 of counter without being divided
Frequently, when frequency dividing psc is other values in advance, the clock of counter carries out psc+1 and divides to obtain clk2, clk1 and clk2 by one
Selector obtains clk_cnt clocks；As 32 filter width N=0, indicate that etv_in signals are one without being filtered
Clean signal；When 32 filter width N are not equal to 0, indicate to open filter function, use clock clk_cnt continuous samplings to N
+ 1 etv_in；When opening filtering, etv_in obtains etv_in_reg after a register, when etv_in is not equal to
When etv_in_reg, the count automatic clears or count of filter add one when each clk_cnt rising edge arrives,
When count is equal to 32 filter width N, it is assumed that current etv_in_reg is an effective signal, and count is certainly
It is dynamic to reset；When obtaining an effective etv_in_reg signal, it will be able to it is rising edge/failing edge according to the configuration of counter,
Counter adds one/subtracts one.
2. the counter according to claim 1 filtered, which is characterized in that it is opened when counter enables cen signals, it is double
Input state is automatically switched into I/O port PAD.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511001553.XA CN105634471B (en) | 2015-12-29 | 2015-12-29 | A kind of counter filtered |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511001553.XA CN105634471B (en) | 2015-12-29 | 2015-12-29 | A kind of counter filtered |
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| Publication Number | Publication Date |
|---|---|
| CN105634471A CN105634471A (en) | 2016-06-01 |
| CN105634471B true CN105634471B (en) | 2018-07-17 |
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| CN201511001553.XA Active CN105634471B (en) | 2015-12-29 | 2015-12-29 | A kind of counter filtered |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109947226A (en) * | 2019-04-03 | 2019-06-28 | 深圳芯马科技有限公司 | A kind of UART wake-up circuit of MCU chip |
| CN110471520B (en) * | 2019-07-29 | 2020-08-18 | 广芯微电子（广州）股份有限公司 | MCU circuit anti-shake method based on external reset |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA2038778C (en) * | 1990-03-26 | 1995-10-24 | Ronald Eugene Fernsler | Synchronized horizontal scanning at horizontal frequency multiples |
| US7598784B2 (en) * | 2005-10-07 | 2009-10-06 | Freescale Semiconductor, Inc. | System and method for controlling signal transitions |
| CN2922277Y (en) * | 2005-10-25 | 2007-07-11 | 中兴通讯股份有限公司 | Clock burr testing circuit |
| CN101871968B (en) * | 2009-04-24 | 2011-12-07 | 郑州威科姆科技股份有限公司 | Reliable time scale pulse measurement method and measurement device thereof |
| CN101788941A (en) * | 2010-01-27 | 2010-07-28 | 清华大学 | Data synchronization circuit of redundancy fault-tolerant computer based on programmable device |
| CN103427803B (en) * | 2012-05-22 | 2015-10-28 | 中国航空工业集团公司第六三一研究所 | Based on the method for the filtering burr of synchronous circuit |
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Address after: 518000 Shenzhen Nanshan District, Guangdong Province, Guangdong Province, Yuehai Street High-tech Zone Community Science and Technology South Road 18 Shenzhen Bay Science and Technology Eco-Park 12 Skirt Building 732 Patentee after: Shenzhen Bojuxing Microelectronics Technology Co., Ltd. Address before: 518000 4th Floor, New Material Port D(4) Building, No.2 Changyuan New Material Port, Zhongxin Road, Nanshan District, Shenzhen City, Guangdong Province Patentee before: Shenzhen Bojuxing Industrial Development Co., Ltd. |