CN110262647A - A kind of cmos data removes circuit and computer equipment - Google Patents
A kind of cmos data removes circuit and computer equipment Download PDFInfo
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- CN110262647A CN110262647A CN201910566363.4A CN201910566363A CN110262647A CN 110262647 A CN110262647 A CN 110262647A CN 201910566363 A CN201910566363 A CN 201910566363A CN 110262647 A CN110262647 A CN 110262647A
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Abstract
The embodiment of the invention provides a kind of cmos datas to remove circuit and computer equipment, it is related to computer equipment technical field, it includes reset signal output circuit, the first time delay module, the second time delay module, embedded controller, cmos data removing module that cmos data, which removes circuit, and reset signal output circuit is for output reset signal to first time delay module.First time delay module receives reset signal and is delayed after the first preset duration, sends Restart Signal to embedded controller and the second time delay module.Second time delay module receives Restart Signal and is delayed after the second preset duration, sends clear signal to cmos data and removes module, so as to remove the data in CMOS chip.Due to removing the data in CMOS chip using the Restart Signal triggering of insertion controller, being realized merely with existing key and remove function, avoid tearing motor-driven work open, simplify maintenance or after sale operating process when restarting insertion controller using reset key.
Description
Technical field
The present embodiments relate to computer equipment technical fields more particularly to a kind of cmos data to remove circuit and calculating
Machine equipment.
Background technique
Computer design has real-time clock (Real-Time Clock, abbreviation RTC) battery at present, which can be
Button cell is integrated into system battery, is used to maintain system under the power blackout situation that shuts down to the holding of time and basic
Related setting in input-output system (Basic Input Output System, BIOS) is constant.When machine needs to remove mutually
When mending metal-oxide semiconductor (MOS) (Complementary Metal Oxide Semiconductor, abbreviation CMOS), at present
It is that machine of tearing open pulls out battery to achieve the purpose that remove CMOS, this operation is difficult to complete in user terminal, and increases the risk of burning machine.
Summary of the invention
Cmos data is removed due to pulling out battery by tearing machine open, is difficult to complete in user terminal, and increase the wind of burning machine
The problem of danger, the embodiment of the invention provides a kind of cmos datas to remove circuit and computer equipment.
On the one hand, the embodiment of the invention provides a kind of cmos datas to remove circuit, comprising:
Reset signal output circuit, the first time delay module, the second time delay module, embedded controller, cmos data are removed
Module；
The reset signal output circuit is for output reset signal to first time delay module；
For first time delay module for receiving the reset signal and after first preset duration that is delayed, letter is restarted in transmission
Number to the embedded controller and second time delay module；
Second time delay module sends for receiving the Restart Signal and after second preset duration that is delayed and removes letter
Number to the cmos data remove module；
The cmos data removes module for removing the data in CMOS chip when receiving the clear signal.
Optionally, the reset signal output circuit includes reset key；
In reset key closure, the reset signal output circuit output reset signal, the reset signal is low
Level.
Optionally, first time delay module includes first switch, first resistor, second resistance, first capacitor；
The first end of the first switch is connect with the reset signal output circuit, the second end of the first switch with
First resistor connection, the third end ground connection of the first switch；
One end of the second resistance is connect with the first power supply, and the other end of the second resistance is connect with first node,
Node of the first node between the first resistor and the first capacitor；
One end of the first capacitor is connect with the first node, the other end ground connection of the first capacitor；
The first node is connect with the embedded controller and second time delay module respectively.
Optionally, second time delay module includes second switch, 3rd resistor, the 4th resistance, the second capacitor；
The first end of the second switch is connect with first time delay module, the second end and third of the second switch
Resistance connection, the third end ground connection of the second switch；
One end of 4th resistance is connect with second source, and the other end of the 4th resistance is connect with second node,
Node of the second node between the 3rd resistor and second capacitor；
One end of second capacitor is connect with the second node, the other end ground connection of second capacitor；
The second node is removed module with the cmos data and is connect.
Optionally, second time delay module further includes third capacitor；
One end of the third capacitor is connect with the first end of the second switch, another termination of the third capacitor
Ground.
Optionally, the first switch be the first MOS type field-effect tube, the grid of the first MOS type field-effect tube with
The reset signal output circuit connection, the drain electrode of the first MOS type field-effect tube are connect with first resistor, and described first
The source electrode of MOS type field-effect tube is grounded；
The second switch is the second MOS type field-effect tube, the grid of the second MOS type field-effect tube and described first
Time delay module connection, the drain electrode of the second MOS type field-effect tube are connect with 3rd resistor, the second MOS type field-effect tube
Source electrode ground connection.
Optionally, first preset duration is determined according to the second resistance and the first capacitor；
Second preset duration is determined according to the 4th resistance and second capacitor.
Optionally, it includes third switch that the cmos data, which removes module,；
The first end of the third switch is connect with second time delay module, the second end and CMOS of the third switch
Chip connection, the third end ground connection of the third switch.
Optionally, third switch is third MOS type field-effect tube, the grid of the third MOS type field-effect tube with
The second time delay module connection, the drain electrode of the third MOS type field-effect tube are connect with CMOS chip, the third MOS type
The source electrode of field-effect tube is grounded.
On the one hand, the embodiment of the invention provides a kind of computer equipments, including above-mentioned cmos data to remove circuit.
In the embodiment of the present invention, it includes reset signal output circuit, the first time delay module, second that cmos data, which removes circuit,
Time delay module, embedded controller, cmos data remove module, wherein reset signal output circuit is used for output reset signal
To first time delay module.First time delay module sends weight for receiving reset signal and after first preset duration that is delayed
Signal is opened to embedded controller and the second time delay module.Second time delay module is for receiving Restart Signal and being delayed second in advance
If after duration, sending clear signal to cmos data and removing module, so that cmos data is removed module and removed in CMOS chip
Data.Due to removing CMOS core using the Restart Signal triggering of insertion controller when restarting insertion controller using reset key
Data in piece are realized merely with existing key and remove CMOS function, avoid tearing motor-driven work open, simplify maintenance or after sale operation stream
Journey.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly introduced, it should be apparent that, drawings in the following description are only some embodiments of the invention, for this
For the those of ordinary skill in field, without any creative labor, it can also be obtained according to these attached drawings
His attached drawing.
Fig. 1 is the structural schematic diagram that a kind of cmos data provided in an embodiment of the present invention removes circuit；
Fig. 2 is the structural schematic diagram that a kind of cmos data provided in an embodiment of the present invention removes circuit；
Fig. 3 is the structural schematic diagram that a kind of cmos data provided in an embodiment of the present invention removes circuit；
Fig. 4 is the structural schematic diagram that a kind of cmos data provided in an embodiment of the present invention removes circuit；
Fig. 5 is the structural schematic diagram that a kind of cmos data provided in an embodiment of the present invention removes circuit；
Fig. 6 is the structural schematic diagram that a kind of cmos data provided in an embodiment of the present invention removes circuit；
Fig. 7 is the structural schematic diagram that a kind of cmos data provided in an embodiment of the present invention removes circuit；
Fig. 8 is the structural schematic diagram that a kind of cmos data provided in an embodiment of the present invention removes circuit；
Fig. 9 is the structural schematic diagram that a kind of cmos data provided in an embodiment of the present invention removes circuit；
Figure 10 is a kind of structural schematic diagram of computer equipment provided in an embodiment of the present invention.
Specific embodiment
In order to which the purpose of the present invention, technical solution and beneficial effect is more clearly understood, below in conjunction with attached drawing and implementation
Example, the present invention will be described in further detail.It should be appreciated that specific embodiment described herein is only used to explain this hair
It is bright, it is not intended to limit the present invention.
Cmos data in the embodiment of the present invention, which removes circuit, can be applied to all kinds of computer equipments, calculate for removing
Data in machine equipment in CMOS chip, wherein computer equipment can be smart phone, tablet computer or Portable, personal meter
Calculation machine etc..
Fig. 1 illustrates a kind of cmos data provided in an embodiment of the present invention and removes circuit, comprising: reset signal is defeated
Circuit 101, the first time delay module 102, the second time delay module 103, embedded controller 104, cmos data remove module out
105.Wherein, reset signal output circuit 101 is for output reset signal to the first time delay module 102, the first time delay module 102
For receiving reset signal and after first preset duration that is delayed, sends Restart Signal to embedded controller 104 and second and prolong
When module 103, the second time delay module 103 for receive Restart Signal and be delayed the second preset duration after, send clear signal
Module 105 is removed to cmos data, cmos data removes module 105 and is used to remove in CMOS chip when receiving clear signal
Data.Optionally, embedded controller 104 when receiving Restart Signal, restarted by pressure.
Due to removing CMOS using the Restart Signal triggering of insertion controller when restarting insertion controller using reset key
Data in chip are realized merely with existing key and remove CMOS function, avoid tearing motor-driven work open, simplify maintenance or operate after sale
Process.
In a kind of possible embodiment, as shown in Fig. 2, reset signal output circuit 101 includes reset key 201,
When reset key 201 is closed, 101 output reset signal of reset signal output circuit, reset signal is low level.
In specific implementation, reset key 201 can be the reset key of computer equipment, and reset signal output circuit 101 exports
Reset signal time can be pinned according to user reset key make reset key be in closed state time determine, output reset
When the time difference of signal, the corresponding function of reset signal is different.For example, reset signal is used when user pins reset key 1s
In shutdown, when user pins reset key 4s, reset signal can be used for computer forced shutdown.When user pins reset key
When 15s, embedded controller 104 can be restarted when embedded controller 104 is abnormal.When user pins reset key 30s,
Embedded controller 104 can be restarted, and remove the data in CMOS chip when embedded controller 104 is abnormal.Using meter
It calculates the existing reset key of machine equipment and realizes that cmos data is removed, without doing big change to computer equipment, ensure that computer
The integrality of equipment.
In a kind of possible embodiment, as shown in figure 3, the first time delay module 102 includes first switch 301, first
The first end of resistance 302, second resistance 303, first capacitor 304, first switch 301 is connect with reset signal output circuit 101,
The second end of first switch 301 is connect with first resistor 302, the third end ground connection of first switch 301；The one of second resistance 303
End is connect with the first power supply 305, and the other end of second resistance 303 is connect with first node 306, and first node 306 is the first electricity
Node between resistance 302 and first capacitor 304；One end of first capacitor 304 is connect with first node 306, first capacitor 304
Other end ground connection；First node 306 is connect with embedded controller 104 and the second time delay module 103 respectively.
In specific implementation, the first end of first switch 301 is the enable end of first switch 301, when reset signal exports electricity
Road 101 not output reset signal when, the first end of first switch 301 is set to high level, the second end of first switch 301 and
The third end of one switch 301 disconnects, and first capacitor 304 is filled by the circuit that the first power supply 305, second resistance 303 form
Electricity, first node 306 are set to high level, and the first time delay module 102 does not export Restart Signal to embedded controller 104 and
Two time delay modules 103.
When reset signal 101 output reset signal of output circuit, the first end of first switch 301 is set to low level,
The second end of first switch 301 is connected to the third end of first switch 301, and first capacitor 304 passes through first switch 301, first
The circuit that resistance 302 forms is discharged, and first node 306 is set to low level, and the first time delay module 102 exports Restart Signal
To embedded controller 104 and the second time delay module 103.
In a kind of possible embodiment, as shown in figure 4, the second time delay module 103 includes second switch 401, third
Resistance 402, the 4th resistance 403, the second capacitor 404；The first end of second switch 401 is connect with the first time delay module 102, and second
The second end of switch 401 is connect with 3rd resistor 402, the third end ground connection of second switch 401；One end of 4th resistance 403 with
Second source 405 connects, and the other end of the 4th resistance 403 is connect with second node 406, and second node 406 is 3rd resistor 402
With the node between the second capacitor 404；One end of second capacitor 404 is connect with second node 406, the second capacitor 404 it is another
End ground connection；Second node 406 is removed module 105 with cmos data and is connect.
In specific implementation, the first end of second switch 401 is the enable end of second switch 401, when the first time delay module 102
When portion does not export Restart Signal, the first end of second switch 401 is set to high level, the second end of second switch 401 and second
The third end of switch 401 is connected to, and the second capacitor 404 passes through 3rd resistor 402, the second end of second switch 401 and second switch
The circuit of 401 third end composition is discharged, and second node 406 is set to low level, and the second time delay module 103 does not export clearly
Except signal to cmos data removes module 105.
When the first time delay module 102 exports Restart Signal, the first end of second switch 401 is set to low level, and second
The second end of switch 401 and the third end of second switch 401 disconnect, and the second capacitor 404 passes through second source 405, the 4th resistance
The circuit of 403 compositions is charged, and second node 406 is set to high level, and the second time delay module 103 exports clear signal extremely
Cmos data removes module 105.
In a kind of possible embodiment, as shown in figure 5, the second time delay module 103 further includes third capacitor 501；The
One end of three capacitors 501 is connect with the first end of second switch 401, the other end ground connection of third capacitor 501.Third capacitor 501
The noise signal in the Restart Signal of the first time delay module 102 output can be filtered, Restart Signal is avoided to shake.
In a kind of possible embodiment, as shown in fig. 6, first switch 301 is the first MOS type field-effect tube 601, the
The grid G of one MOS type field-effect tube 601 is connect with reset signal output circuit 101, the drain electrode of the first MOS type field-effect tube 601
D is connect with first resistor 302, the source S ground connection of the first MOS type field-effect tube 601；Second switch 401 is the second MOS type field effect
Should pipe 602, the grid of the second MOS type field-effect tube 602 connect with the first time delay module 102, the second MOS type field-effect tube 602
Drain electrode connect with 3rd resistor 402, the source electrode of the second MOS type field-effect tube 602 ground connection.
In specific implementation, the first MOS type field-effect tube 601 is P-channel field-effect transistor (PEFT) pipe, the first MOS type field-effect tube 601
When grid is high level, the drain electrode of the first MOS type field-effect tube 601 and source electrode are disconnected, the grid of the first MOS type field-effect tube 601
Extremely low level when, the drain electrode of the first MOS type field-effect tube 601 is connected to source electrode.Second MOS type field-effect tube 602 is N-channel
Field-effect tube, when the grid of the second MOS type field-effect tube 602 is low level, the drain electrode of the second MOS type field-effect tube 602 and source
Pole disconnects, when the grid of the second MOS type field-effect tube 602 is high level, the drain electrode of the second MOS type field-effect tube 602 and source electrode
Connection.
In a kind of possible embodiment, the first preset duration is determined according to second resistance 303 and first capacitor 304
, specifically meet following formula (1):
T1=-R2*C1*ln ((Va-Vb)/Va) ... ... ... ... ... ... (1)
Wherein, T1 is the first preset duration, and R2 is the resistance value of second resistance 303, and C1 is the capacitor of first capacitor 304
Value, Va are the voltage value of the first power supply 305, and Vb is the threshold voltage value of Restart Signal, and Va and Vb are constant, for example, Va=
3.5V, Vb=1V.
By adjusting adjustable first preset duration of size of second resistance 303 and first capacitor 304, for example, passing through
Increase the resistance value of second resistance 303 and/or increase 304 capacitance of first capacitor, realizes and increase the first preset duration, by subtracting
The resistance value and/or reduction 304 capacitance of first capacitor of small second resistance 303, realize and reduce the first preset duration.
Second preset duration is determined according to the 4th resistance 403 and the second capacitor 404, and following formula (2) are specifically met:
T2=-R4*C2*ln ((Vc-Vd)/Vc) ... ... ... ... ... ... (2)
Wherein, T2 is the second preset duration, and R4 is the resistance value of the 4th resistance 403, and C2 is the capacitor of the second capacitor 404
Value, Vc are the voltage value of second source 405, and Vd is the threshold voltage value of clear signal, and Vc and Vd are constant, for example, Vc=
3.5V, Vd=0.7V.
By adjusting adjustable second preset duration of size of the 4th resistance 403 and the second capacitor 404, for example, passing through
Increase the resistance value of the 4th resistance 403 and/or increase 404 capacitance of the second capacitor, realizes and increase the second preset duration, by subtracting
The resistance value and/or reduction 404 capacitance of the second capacitor of small 4th resistance 403, realize and reduce the second preset duration.
In a kind of possible embodiment, as shown in fig. 7, it includes third switch 701 that cmos data, which removes module 105,
The first end of third switch 701 is connect with the second time delay module 103, and the second end of third switch 701 is connect with CMOS chip, the
The third end of three switches 701 is grounded.
In specific implementation, when the second time delay module 103 does not export clear signal, the first end of third switch 701 is set to
For low level, the second end of third switch 701 and the third end of third switch 701 are disconnected, and the second end of third switch 701 is height
Level does not remove the data in CMOS chip.When the second time delay module 103 exports clear signal, the first of third switch 701
End is set to high level, and the second end of third switch 701 and the third end of third switch 701 are connected, and the second of third switch 701
End is low level, removes the data in CMOS chip.
In a kind of possible embodiment, as shown in figure 8, third switch 701 is third MOS type field-effect tube 801, the
The grid of three MOS type field-effect tube 801 is connect with the second time delay module 103, the drain electrode of third MOS type field-effect tube 801 with
CMOS chip connection, the source electrode ground connection of third MOS type field-effect tube 801.
Specifically, third MOS type field-effect tube 801 is N-channel field-effect tube, the grid of third MOS type field-effect tube 801
When for low level, the drain electrode of third MOS type field-effect tube 801 and source electrode are disconnected, and the grid of third MOS type field-effect tube 801 is
When high level, the drain electrode of third MOS type field-effect tube 801 is connected to source electrode.
Fig. 9 illustrates a kind of cmos data provided in an embodiment of the present invention and removes circuit, comprising:
Reset signal output circuit 101, the first time delay module 102, the second time delay module 103, embedded controller 104,
Cmos data removes module 105.
Reset signal output circuit 101 includes reset key 201.
First time delay module 102 includes the first MOS type field-effect tube 601, first resistor 302, second resistance 303, first
The grid G of capacitor 304, the first MOS type field-effect tube 601 is connect with reset signal output circuit 101, the first MOS type field-effect
The drain D of pipe 601 is connect with first resistor 302, the source S ground connection of the first MOS type field-effect tube 601；The one of second resistance 303
End is connect with the first power supply 305, and the other end of second resistance 303 is connect with first node 306, and first node 306 is the first electricity
Node between resistance 302 and first capacitor 304；One end of first capacitor 304 is connect with first node 306, first capacitor 304
Other end ground connection；First node 306 is connect with embedded controller 104 and the second time delay module 103 respectively.
Second time delay module 103 includes the second MOS type field-effect tube 602,3rd resistor 402, the 4th resistance 403, second
Capacitor 404；The grid of second MOS type field-effect tube 602 is connect with the first time delay module 102, the second MOS type field-effect tube 602
Drain electrode connect with 3rd resistor 402, the source electrode of the second MOS type field-effect tube 602 ground connection.One end of 4th resistance 403 and the
The connection of two power supplys 405, the other end of the 4th resistance 403 connect with second node 406, second node 406 for 3rd resistor 402 and
Node between second capacitor 404；One end of second capacitor 404 is connect with second node 406, the other end of the second capacitor 404
Ground connection；Second node 406 is removed module 105 with cmos data and is connect.Second time delay module 103 further includes third capacitor 501；The
One end of three capacitors 501 is connect with the grid of the second MOS type field-effect tube 602, the other end ground connection of third capacitor 501.
Cmos data removes the grid that module 105 includes third MOS type field-effect tube 801 and the second time delay module 103 connects
It connecing, the drain electrode of third MOS type field-effect tube 801 is connect with CMOS chip, the source electrode ground connection of third MOS type field-effect tube 801, the
Three MOS type field-effect tube 801 are N-channel field-effect tube.
Due to removing CMOS using the Restart Signal triggering of insertion controller when restarting insertion controller using reset key
Data in chip are realized merely with existing key and remove CMOS function, avoid tearing motor-driven work open, simplify maintenance or operate after sale
Process.
Figure 10 illustrates a kind of computer equipment provided in an embodiment of the present invention, which includes CMOS
Data clear circuit 1001, CMOS chip 1002.
It should be understood by those skilled in the art that, the embodiment of the present invention can provide as method or computer program product.
Therefore, complete hardware embodiment, complete software embodiment or embodiment combining software and hardware aspects can be used in the present invention
Form.It is deposited moreover, the present invention can be used to can be used in the computer that one or more wherein includes computer usable program code
The shape for the computer program product implemented on storage media (including but not limited to magnetic disk storage, CD-ROM, optical memory etc.)
Formula.
The present invention be referring to according to the method for the embodiment of the present invention, the process of equipment (system) and computer program product
Figure and/or block diagram describe.It should be understood that every one stream in flowchart and/or the block diagram can be realized by computer program instructions
The combination of process and/or box in journey and/or box and flowchart and/or the block diagram.It can provide these computer programs
Instruct the processor of general purpose computer, special purpose computer, Embedded Processor or other programmable data processing devices to produce
A raw machine, so that being generated by the instruction that computer or the processor of other programmable data processing devices execute for real
The device for the function of being specified in present one or more flows of the flowchart and/or one or more blocks of the block diagram.
These computer program instructions, which may also be stored in, is able to guide computer or other programmable data processing devices with spy
Determine in the computer-readable memory that mode works, so that it includes referring to that instruction stored in the computer readable memory, which generates,
Enable the manufacture of device, the command device realize in one box of one or more flows of the flowchart and/or block diagram or
The function of being specified in multiple boxes.
These computer program instructions also can be loaded onto a computer or other programmable data processing device, so that counting
Series of operation steps are executed on calculation machine or other programmable devices to generate computer implemented processing, thus in computer or
The instruction executed on other programmable devices is provided for realizing in one or more flows of the flowchart and/or block diagram one
The step of function of being specified in a box or multiple boxes.
Although preferred embodiments of the present invention have been described, it is created once a person skilled in the art knows basic
Property concept, then additional changes and modifications may be made to these embodiments.So it includes excellent that the following claims are intended to be interpreted as
It selects embodiment and falls into all change and modification of the scope of the invention.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
Mind and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (10)
1. a kind of cmos data removes circuit characterized by comprising
Reset signal output circuit, the first time delay module, the second time delay module, embedded controller, cmos data remove module；
The reset signal output circuit is for output reset signal to first time delay module；
First time delay module sends Restart Signal extremely for receiving the reset signal and after first preset duration that is delayed
The embedded controller and second time delay module；
Second time delay module sends clear signal extremely for receiving the Restart Signal and after second preset duration that is delayed
The cmos data removes module；
The cmos data removes module for removing the data in CMOS chip when receiving the clear signal.
2. circuit as described in claim 1, which is characterized in that the reset signal output circuit includes reset key；
In reset key closure, the reset signal output circuit output reset signal, the reset signal is low level.
3. circuit as described in claim 1, which is characterized in that first time delay module include first switch, first resistor,
Second resistance, first capacitor；
The first end of the first switch is connect with the reset signal output circuit, the second end of the first switch and first
Resistance connection, the third end ground connection of the first switch；
One end of the second resistance is connect with the first power supply, and the other end of the second resistance is connect with first node, described
Node of the first node between the first resistor and the first capacitor；
One end of the first capacitor is connect with the first node, the other end ground connection of the first capacitor；
The first node is connect with the embedded controller and second time delay module respectively.
4. the circuit as described in claims 1 to 3 is any, which is characterized in that second time delay module includes second switch,
Three resistance, the 4th resistance, the second capacitor；
The first end of the second switch is connect with first time delay module, the second end and 3rd resistor of the second switch
Connection, the third end ground connection of the second switch；
One end of 4th resistance is connect with second source, and the other end of the 4th resistance is connect with second node, described
Node of the second node between the 3rd resistor and second capacitor；
One end of second capacitor is connect with the second node, the other end ground connection of second capacitor；
The second node is removed module with the cmos data and is connect.
5. circuit as claimed in claim 4, which is characterized in that second time delay module further includes third capacitor；
One end of the third capacitor is connect with the first end of the second switch, the other end ground connection of the third capacitor.
6. circuit as claimed in claim 4, which is characterized in that the first switch is the first MOS type field-effect tube, described the
The grid of one MOS type field-effect tube is connect with the reset signal output circuit, the drain electrode of the first MOS type field-effect tube with
First resistor connection, the source electrode ground connection of the first MOS type field-effect tube；
The second switch is the second MOS type field-effect tube, the grid of the second MOS type field-effect tube and first delay
Module connection, the drain electrode of the second MOS type field-effect tube are connect with 3rd resistor, the source of the second MOS type field-effect tube
Pole ground connection.
7. circuit as claimed in claim 4, which is characterized in that first preset duration is according to the second resistance and institute
State what first capacitor determined；
Second preset duration is determined according to the 4th resistance and second capacitor.
8. circuit as described in claim 1, which is characterized in that it includes third switch that the cmos data, which removes module,；
The first end of the third switch is connect with second time delay module, the second end and CMOS chip of the third switch
Connection, the third end ground connection of the third switch.
9. circuit as claimed in claim 8, which is characterized in that third switch is third MOS type field-effect tube, described the
The grid of three MOS type field-effect tube is connect with second time delay module, the drain electrode of the third MOS type field-effect tube and CMOS
Chip connection, the source electrode ground connection of the third MOS type field-effect tube.
10. a kind of computer equipment characterized by comprising any cmos data of claim 1-9 removes circuit.
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| CN201910566363.4A CN110262647B (en) | 2019-06-27 | 2019-06-27 | CMOS data clearing circuit and computer equipment |
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| CN201910566363.4A CN110262647B (en) | 2019-06-27 | 2019-06-27 | CMOS data clearing circuit and computer equipment |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110884448A (en) * | 2019-10-17 | 2020-03-17 | 联创汽车电子有限公司 | Power-off control module of communication unit |
| US11842201B2 (en) | 2020-08-24 | 2023-12-12 | Pegatron Corporation | Portable electronic device capable of resetting system |
| WO2024103802A1 (en) * | 2022-11-15 | 2024-05-23 | 深圳市汇川技术股份有限公司 | Automatic cmos clearing control method and automatic cmos clearing circuit |
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| US11842201B2 (en) | 2020-08-24 | 2023-12-12 | Pegatron Corporation | Portable electronic device capable of resetting system |
| WO2024103802A1 (en) * | 2022-11-15 | 2024-05-23 | 深圳市汇川技术股份有限公司 | Automatic cmos clearing control method and automatic cmos clearing circuit |
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