CN110262647B - CMOS data clearing circuit and computer equipment - Google Patents
CMOS data clearing circuit and computer equipment Download PDFInfo
- Publication number
- CN110262647B CN110262647B CN201910566363.4A CN201910566363A CN110262647B CN 110262647 B CN110262647 B CN 110262647B CN 201910566363 A CN201910566363 A CN 201910566363A CN 110262647 B CN110262647 B CN 110262647B
- Authority
- CN
- China
- Prior art keywords
- switch
- resistor
- capacitor
- delay module
- node
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
Abstract
The embodiment of the invention provides a CMOS data clearing circuit and computer equipment, and relates to the technical field of computer equipment. And after receiving the reset signal and delaying the first preset time length, the first delay module sends a restart signal to the embedded controller and the second delay module. And after receiving the restart signal and delaying a second preset time, the second delay module sends a clearing signal to the CMOS data clearing module so as to clear the data in the CMOS chip. When the embedded controller is restarted by using the reset key, the restart signal of the embedded controller is used for triggering and clearing the data in the CMOS chip, and the clearing function is realized only by using the existing key, so that the disassembly action is avoided, and the maintenance or after-sale operation flow is simplified.
Description
Technical Field
The embodiment of the invention relates to the technical field of computer equipment, in particular to a CMOS (complementary metal oxide semiconductor) data clearing circuit and computer equipment.
Background
Currently, a Real-Time Clock (RTC) battery is provided in a computer design, and the RTC battery may be a button battery or integrated into a System battery to maintain Time keeping of the System under a power-off condition and maintain relevant settings in a Basic Input Output System (BIOS). When a machine needs to clean a Complementary Metal Oxide Semiconductor (CMOS), the CMOS is cleaned by removing a battery, which is difficult to be done at a user end and increases the risk of burn-in.
Disclosure of Invention
The embodiment of the invention provides a CMOS data clearing circuit and computer equipment, and solves the problems that the CMOS data clearing is difficult to finish at a user end and the risk of burn-in is increased by removing a battery through dismantling a machine.
In one aspect, an embodiment of the present invention provides a CMOS data clearing circuit, including:
the device comprises a reset signal output circuit, a first delay module, a second delay module, an embedded controller and a CMOS data clearing module;
the reset signal output circuit is used for outputting a reset signal to the first delay module;
the first delay module is used for receiving the reset signal, delaying a first preset time length and then sending a restart signal to the embedded controller and the second delay module;
the second delay module is used for receiving the restart signal, delaying a second preset time length and then sending a clearing signal to the CMOS data clearing module;
the CMOS data clearing module is used for clearing data in the CMOS chip when receiving the clearing signal.
Optionally, the reset signal output circuit comprises a reset key;
when the reset key is closed, the reset signal output circuit outputs a reset signal, and the reset signal is at a low level.
Optionally, the first delay module includes a first switch, a first resistor, a second resistor, and a first capacitor;
the first end of the first switch is connected with the reset signal output circuit, the second end of the first switch is connected with the first resistor, and the third end of the first switch is grounded;
one end of the second resistor is connected with a first power supply, the other end of the second resistor is connected with a first node, and the first node is a node between the first resistor and the first capacitor;
one end of the first capacitor is connected with the first node, and the other end of the first capacitor is grounded;
the first node is respectively connected with the embedded controller and the second delay module.
Optionally, the second delay module includes a second switch, a third resistor, a fourth resistor, and a second capacitor;
the first end of the second switch is connected with the first delay module, the second end of the second switch is connected with a third resistor, and the third end of the second switch is grounded;
one end of the fourth resistor is connected with a second power supply, the other end of the fourth resistor is connected with a second node, and the second node is a node between the third resistor and the second capacitor;
one end of the second capacitor is connected with the second node, and the other end of the second capacitor is grounded;
the second node is connected with the CMOS data clearing module.
Optionally, the second delay module further includes a third capacitor;
one end of the third capacitor is connected with the first end of the second switch, and the other end of the third capacitor is grounded.
Optionally, the first switch is a first MOS field effect transistor, a gate of the first MOS field effect transistor is connected to the reset signal output circuit, a drain of the first MOS field effect transistor is connected to the first resistor, and a source of the first MOS field effect transistor is grounded;
the second switch is a second MOS type field effect transistor, the grid electrode of the second MOS type field effect transistor is connected with the first time delay module, the drain electrode of the second MOS type field effect transistor is connected with a third resistor, and the source electrode of the second MOS type field effect transistor is grounded.
Optionally, the first preset time period is determined according to the second resistance and the first capacitance;
the second preset time is determined according to the fourth resistor and the second capacitor.
Optionally, the CMOS data clear module includes a third switch;
the first end of the third switch is connected with the second delay module, the second end of the third switch is connected with the CMOS chip, and the third end of the third switch is grounded.
Optionally, the third switch is a third MOS field effect transistor, a gate of the third MOS field effect transistor is connected to the second delay module, a drain of the third MOS field effect transistor is connected to the CMOS chip, and a source of the third MOS field effect transistor is grounded.
In one aspect, an embodiment of the present invention provides a computer device, including the CMOS data clearing circuit described above.
In the embodiment of the invention, the CMOS data clearing circuit comprises a reset signal output circuit, a first delay module, a second delay module, an embedded controller and a CMOS data clearing module, wherein the reset signal output circuit is used for outputting a reset signal to the first delay module. The first time delay module is used for receiving the reset signal and delaying for a first preset time length, and then sending a restart signal to the embedded controller and the second time delay module. The second delay module is used for receiving the restart signal and delaying a second preset time length and then sending a clearing signal to the CMOS data clearing module so that the CMOS data clearing module clears data in the CMOS chip. When the embedded controller is restarted by using the reset key, the restart signal of the embedded controller is used for triggering and clearing the data in the CMOS chip, and the CMOS function is cleared only by using the existing key, so that the disassembly action is avoided, and the maintenance or after-sale operation flow is simplified.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic structural diagram of a CMOS data clearing circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a CMOS data clearing circuit according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a CMOS data clearing circuit according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a CMOS data clearing circuit according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a CMOS data clearing circuit according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a CMOS data clearing circuit according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a CMOS data clearing circuit according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a CMOS data clearing circuit according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram of a CMOS data clearing circuit according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram of a computer device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clearly apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The CMOS data clearing circuit in the embodiment of the invention can be applied to various computer equipment and is used for clearing data in a CMOS chip in the computer equipment, wherein the computer equipment can be a smart phone, a tablet personal computer or a portable personal computer.
Fig. 1 schematically shows a CMOS data clearing circuit provided by an embodiment of the present invention, including: the circuit comprises a reset signal output circuit 101, a first delay module 102, a second delay module 103, an embedded controller 104 and a CMOS data clearing module 105. The reset signal output circuit 101 is configured to output a reset signal to the first delay module 102, the first delay module 102 is configured to receive the reset signal and delay for a first preset duration, and then send a restart signal to the embedded controller 104 and the second delay module 103, the second delay module 103 is configured to receive the restart signal and delay for a second preset duration, and then send a clear signal to the CMOS data clear module 105, and the CMOS data clear module 105 is configured to clear data in a CMOS chip when receiving the clear signal. Optionally, the embedded controller 104 forces a reboot upon receiving a reboot signal.
When the embedded controller is restarted by using the reset key, the restart signal of the embedded controller is used for triggering and clearing the data in the CMOS chip, and the CMOS function is cleared only by using the existing key, so that the disassembly action is avoided, and the maintenance or after-sale operation flow is simplified.
In one possible implementation, as shown in fig. 2, the reset signal output circuit 101 includes a reset key 201, and when the reset key 201 is closed, the reset signal output circuit 101 outputs a reset signal, which is at a low level.
In a specific implementation, the reset key 201 may be a reset key of a computer device, the time of the reset signal output by the reset signal output circuit 101 may be determined according to the time when a user presses the reset key to make the reset key in a closed state, and when the time of outputting the reset signal is different, the functions corresponding to the reset signal are different. For example, when the user presses the reset key 1s, the reset signal is used for power off, and when the user presses the reset key 4s, the reset signal may be used for forced power off of the computer. When the user presses the reset key 15s, the embedded controller 104 may be restarted when the embedded controller 104 is abnormal. When the user presses the reset key 30s, the embedded controller 104 may be restarted and the data in the CMOS chip may be cleared when the embedded controller 104 is abnormal. The existing reset key of the computer equipment is adopted to realize the CMOS data clearing, the computer equipment does not need to be greatly changed, and the integrity of the computer equipment is ensured.
In a possible implementation manner, as shown in fig. 3, the first delay module 102 includes a first switch 301, a first resistor 302, a second resistor 303, and a first capacitor 304, a first end of the first switch 301 is connected to the reset signal output circuit 101, a second end of the first switch 301 is connected to the first resistor 302, and a third end of the first switch 301 is grounded; one end of the second resistor 303 is connected to the first power source 305, the other end of the second resistor 303 is connected to a first node 306, and the first node 306 is a node between the first resistor 302 and the first capacitor 304; one end of the first capacitor 304 is connected to the first node 306, and the other end of the first capacitor 304 is grounded; the first node 306 is connected to the embedded controller 104 and the second delay module 103, respectively.
In a specific implementation, the first terminal of the first switch 301 is an enable terminal of the first switch 301, when the reset signal output circuit 101 does not output the reset signal, the first terminal of the first switch 301 is set to a high level, the second terminal of the first switch 301 and the third terminal of the first switch 301 are disconnected, the first capacitor 304 is charged through a loop formed by the first power source 305 and the second resistor 303, the first node 306 is set to a high level, and the first delay module 102 does not output the restart signal to the embedded controller 104 and the second delay module 103.
When the reset signal output circuit 101 outputs a reset signal, the first terminal of the first switch 301 is set to a low level, the second terminal of the first switch 301 is connected to the third terminal of the first switch 301, the first capacitor 304 discharges through a loop formed by the first switch 301 and the first resistor 302, the first node 306 is set to a low level, and the first delay module 102 outputs a restart signal to the embedded controller 104 and the second delay module 103.
In one possible implementation, as shown in fig. 4, the second delay module 103 includes a second switch 401, a third resistor 402, a fourth resistor 403, and a second capacitor 404; a first end of the second switch 401 is connected to the first delay module 102, a second end of the second switch 401 is connected to the third resistor 402, and a third end of the second switch 401 is grounded; one end of the fourth resistor 403 is connected to the second power source 405, the other end of the fourth resistor 403 is connected to a second node 406, and the second node 406 is a node between the third resistor 402 and the second capacitor 404; one end of the second capacitor 404 is connected to the second node 406, and the other end of the second capacitor 404 is grounded; the second node 406 is connected to the CMOS data clear block 105.
In a specific implementation, the first terminal of the second switch 401 is an enable terminal of the second switch 401, when the first delay module 102 does not output the restart signal, the first terminal of the second switch 401 is set to a high level, the second terminal of the second switch 401 is communicated with the third terminal of the second switch 401, the second capacitor 404 discharges through a loop formed by the third resistor 402, the second terminal of the second switch 401, and the third terminal of the second switch 401, the second node 406 is set to a low level, and the second delay module 103 does not output the clear signal to the CMOS data clear module 105.
When the first delay module 102 outputs the restart signal, the first terminal of the second switch 401 is set to the low level, the second terminal of the second switch 401 and the third terminal of the second switch 401 are disconnected, the second capacitor 404 is charged through a loop formed by the second power source 405 and the fourth resistor 403, the second node 406 is set to the high level, and the second delay module 103 outputs the clear signal to the CMOS data clear module 105.
In one possible implementation, as shown in fig. 5, the second delay module 103 further includes a third capacitor 501; one end of the third capacitor 501 is connected to the first end of the second switch 401, and the other end of the third capacitor 501 is grounded. The third capacitor 501 may filter a noise signal in the restart signal output by the first delay module 102, so as to avoid oscillation of the restart signal.
In one possible embodiment, as shown in fig. 6, the first switch 301 is a first MOS fet 601, a gate G of the first MOS fet 601 is connected to the reset signal output circuit 101, a drain D of the first MOS fet 601 is connected to the first resistor 302, and a source S of the first MOS fet 601 is grounded; the second switch 401 is a second MOS field effect transistor 602, a gate of the second MOS field effect transistor 602 is connected to the first delay module 102, a drain of the second MOS field effect transistor 602 is connected to the third resistor 402, and a source of the second MOS field effect transistor 602 is grounded.
In a specific implementation, the first MOS fet 601 is a P-channel fet, when the gate of the first MOS fet 601 is at a high level, the drain and the source of the first MOS fet 601 are disconnected, and when the gate of the first MOS fet 601 is at a low level, the drain and the source of the first MOS fet 601 are connected. The second MOS fet 602 is an N-channel fet, and when the gate of the second MOS fet 602 is at a low level, the drain and the source of the second MOS fet 602 are disconnected, and when the gate of the second MOS fet 602 is at a high level, the drain and the source of the second MOS fet 602 are connected.
In a possible embodiment, the first preset time period is determined according to the second resistor 303 and the first capacitor 304, and the following formula (1) is specifically satisfied:
T1＝-R2*C1*ln((Va-Vb)/Va)………………………………(1)
where T1 is a first preset time period, R2 is a resistance value of the second resistor 303, C1 is a capacitance value of the first capacitor 304, Va is a voltage value of the first power source 305, Vb is a threshold voltage value of the restart signal, and Va and Vb are constants, for example, Va is 3.5V, and Vb is 1V.
The first preset time period may be adjusted by adjusting the sizes of the second resistor 303 and the first capacitor 304, for example, by increasing the resistance of the second resistor 303 and/or increasing the capacitance of the first capacitor 304, and by decreasing the resistance of the second resistor 303 and/or decreasing the capacitance of the first capacitor 304, the first preset time period may be decreased.
The second preset time period is determined according to the fourth resistor 403 and the second capacitor 404, and specifically satisfies the following formula (2):
T2＝-R4*C2*ln((Vc-Vd)/Vc)………………………………(2)
where T2 is a second preset time period, R4 is a resistance value of the fourth resistor 403, C2 is a capacitance value of the second capacitor 404, Vc is a voltage value of the second power source 405, Vd is a threshold voltage value of the clearing signal, and Vc and Vd are constants, for example, Vc equals 3.5V, and Vd equals 0.7V.
The second preset time period may be adjusted by adjusting the sizes of the fourth resistor 403 and the second capacitor 404, for example, by increasing the resistance of the fourth resistor 403 and/or increasing the capacitance of the second capacitor 404, and by decreasing the resistance of the fourth resistor 403 and/or decreasing the capacitance of the second capacitor 404, the second preset time period is decreased.
In one possible implementation, as shown in fig. 7, the CMOS data clearing module 105 includes a third switch 701, a first terminal of the third switch 701 is connected to the second delay module 103, a second terminal of the third switch 701 is connected to the CMOS chip, and a third terminal of the third switch 701 is grounded.
In a specific implementation, when the second delay module 103 does not output the clear signal, the first terminal of the third switch 701 is set to a low level, the second terminal of the third switch 701 and the third terminal of the third switch 701 are disconnected, and the second terminal of the third switch 701 is set to a high level, so that data in the CMOS chip is not cleared. When the second delay module 103 outputs the clear signal, the first terminal of the third switch 701 is set to a high level, the second terminal of the third switch 701 and the third terminal of the third switch 701 are turned on, and the second terminal of the third switch 701 is set to a low level, so as to clear data in the CMOS chip.
In a possible implementation manner, as shown in fig. 8, the third switch 701 is a third MOS fet 801, a gate of the third MOS fet 801 is connected to the second delay module 103, a drain of the third MOS fet 801 is connected to the CMOS chip, and a source of the third MOS fet 801 is grounded.
Specifically, the third MOS field effect transistor 801 is an N-channel field effect transistor, when the gate of the third MOS field effect transistor 801 is at a low level, the drain and the source of the third MOS field effect transistor 801 are disconnected, and when the gate of the third MOS field effect transistor 801 is at a high level, the drain and the source of the third MOS field effect transistor 801 are connected.
Fig. 9 schematically shows a CMOS data clearing circuit provided by an embodiment of the present invention, including:
the circuit comprises a reset signal output circuit 101, a first delay module 102, a second delay module 103, an embedded controller 104 and a CMOS data clearing module 105.
The reset signal output circuit 101 includes a reset key 201.
The first delay module 102 includes a first MOS fet 601, a first resistor 302, a second resistor 303, and a first capacitor 304, a gate G of the first MOS fet 601 is connected to the reset signal output circuit 101, a drain D of the first MOS fet 601 is connected to the first resistor 302, and a source S of the first MOS fet 601 is grounded; one end of the second resistor 303 is connected to the first power source 305, the other end of the second resistor 303 is connected to a first node 306, and the first node 306 is a node between the first resistor 302 and the first capacitor 304; one end of the first capacitor 304 is connected to the first node 306, and the other end of the first capacitor 304 is grounded; the first node 306 is connected to the embedded controller 104 and the second delay module 103, respectively.
The second delay module 103 comprises a second MOS field effect transistor 602, a third resistor 402, a fourth resistor 403, and a second capacitor 404; the gate of the second MOS fet 602 is connected to the first delay module 102, the drain of the second MOS fet 602 is connected to the third resistor 402, and the source of the second MOS fet 602 is grounded. One end of the fourth resistor 403 is connected to the second power source 405, the other end of the fourth resistor 403 is connected to a second node 406, and the second node 406 is a node between the third resistor 402 and the second capacitor 404; one end of the second capacitor 404 is connected to the second node 406, and the other end of the second capacitor 404 is grounded; the second node 406 is connected to the CMOS data clear block 105. The second delay module 103 further comprises a third capacitor 501; one end of the third capacitor 501 is connected to the gate of the second MOS fet 602, and the other end of the third capacitor 501 is grounded.
The CMOS data removing module 105 includes a gate of a third MOS field effect transistor 801 connected to the second delay module 103, a drain of the third MOS field effect transistor 801 connected to the CMOS chip, a source of the third MOS field effect transistor 801 grounded, and the third MOS field effect transistor 801 is an N-channel field effect transistor.
When the embedded controller is restarted by using the reset key, the restart signal of the embedded controller is used for triggering and clearing the data in the CMOS chip, and the CMOS function is cleared only by using the existing key, so that the disassembly action is avoided, and the maintenance or after-sale operation flow is simplified.
Fig. 10 illustrates a computer device provided by an embodiment of the present invention, which includes a CMOS data clearing circuit 1001 and a CMOS chip 1002.
It should be apparent to those skilled in the art that embodiments of the present invention may be provided as a method, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (7)
1. A CMOS data clear circuit, comprising:
the device comprises a reset signal output circuit, a first delay module, a second delay module, an embedded controller and a CMOS data clearing module;
the reset signal output circuit is used for outputting a reset signal to the first delay module;
the first delay module comprises a first switch, a first resistor, a second resistor and a first capacitor;
the first end of the first switch is connected with the reset signal output circuit, the second end of the first switch is connected with the first resistor, and the third end of the first switch is grounded;
one end of the second resistor is connected with a first power supply, the other end of the second resistor is connected with a first node, and the first node is a node between the first resistor and the first capacitor;
one end of the first capacitor is connected with the first node, and the other end of the first capacitor is grounded;
the first node is respectively connected with the embedded controller and the second delay module;
the first delay module is used for receiving the reset signal and delaying for a first preset time length, and then sending a restart signal to the embedded controller and the second delay module, wherein the first preset time length is determined according to the second resistor and the first capacitor;
the second delay module comprises a second switch, a third resistor, a fourth resistor and a second capacitor;
the first end of the second switch is connected with the first delay module, the second end of the second switch is connected with a third resistor, and the third end of the second switch is grounded;
one end of the fourth resistor is connected with a second power supply, the other end of the fourth resistor is connected with a second node, and the second node is a node between the third resistor and the second capacitor;
one end of the second capacitor is connected with the second node, and the other end of the second capacitor is grounded;
the second node is connected with the CMOS data clearing module;
the second delay module is configured to receive the restart signal and delay a second preset time period, and then send a clearing signal to the CMOS data clearing module, where the second preset time period is determined according to the fourth resistor and the second capacitor;
the CMOS data clearing module is used for clearing data in the CMOS chip when receiving the clearing signal.
2. The circuit of claim 1, wherein the reset signal output circuit comprises a reset key;
when the reset key is closed, the reset signal output circuit outputs a reset signal, and the reset signal is at a low level.
3. The circuit of claim 1, wherein the second delay module further comprises a third capacitance;
one end of the third capacitor is connected with the first end of the second switch, and the other end of the third capacitor is grounded.
4. The circuit of claim 1, wherein the first switch is a first MOS field effect transistor, a gate of the first MOS field effect transistor is connected to the reset signal output circuit, a drain of the first MOS field effect transistor is connected to a first resistor, and a source of the first MOS field effect transistor is grounded;
the second switch is a second MOS type field effect transistor, the grid electrode of the second MOS type field effect transistor is connected with the first time delay module, the drain electrode of the second MOS type field effect transistor is connected with a third resistor, and the source electrode of the second MOS type field effect transistor is grounded.
5. The circuit of claim 1, wherein the CMOS data clear module includes a third switch;
the first end of the third switch is connected with the second delay module, the second end of the third switch is connected with the CMOS chip, and the third end of the third switch is grounded.
6. The circuit of claim 5, wherein the third switch is a third MOSFET, a gate of the third MOSFET is connected to the second delay module, a drain of the third MOSFET is connected to the CMOS chip, and a source of the third MOSFET is grounded.
7. A computer device, comprising: the CMOS data clearing circuit of any of claims 1-6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910566363.4A CN110262647B (en) | 2019-06-27 | 2019-06-27 | CMOS data clearing circuit and computer equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910566363.4A CN110262647B (en) | 2019-06-27 | 2019-06-27 | CMOS data clearing circuit and computer equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110262647A CN110262647A (en) | 2019-09-20 |
| CN110262647B true CN110262647B (en) | 2021-05-25 |
Family
ID=67922234
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910566363.4A Active CN110262647B (en) | 2019-06-27 | 2019-06-27 | CMOS data clearing circuit and computer equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110262647B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110884448B (en) * | 2019-10-17 | 2021-06-08 | 上海汽车工业(集团)总公司 | Power-off control module of communication unit |
| TWI749728B (en) | 2020-08-24 | 2021-12-11 | 和碩聯合科技股份有限公司 | Portable electronic device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6085327A (en) * | 1998-04-10 | 2000-07-04 | Tritech Microelectronics, Ltd. | Area-efficient integrated self-timing power start-up reset circuit with delay of the start-up reset until the system clock is stabilized |
| CN101470615A (en) * | 2007-12-28 | 2009-07-01 | 技嘉科技股份有限公司 | Single-key controlled method for automatically repairing system configuration |
| CN104932653A (en) * | 2015-06-18 | 2015-09-23 | 常州工学院 | Computer startup management control system |
| CN206270863U (en) * | 2016-08-29 | 2017-06-20 | 广东虹勤通讯技术有限公司 | Cmos data remove device and computer |
| CN208580396U (en) * | 2018-08-06 | 2019-03-05 | 浙江宇视科技有限公司 | Data dump device and computer |
-
2019
- 2019-06-27 CN CN201910566363.4A patent/CN110262647B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6085327A (en) * | 1998-04-10 | 2000-07-04 | Tritech Microelectronics, Ltd. | Area-efficient integrated self-timing power start-up reset circuit with delay of the start-up reset until the system clock is stabilized |
| CN101470615A (en) * | 2007-12-28 | 2009-07-01 | 技嘉科技股份有限公司 | Single-key controlled method for automatically repairing system configuration |
| CN104932653A (en) * | 2015-06-18 | 2015-09-23 | 常州工学院 | Computer startup management control system |
| CN206270863U (en) * | 2016-08-29 | 2017-06-20 | 广东虹勤通讯技术有限公司 | Cmos data remove device and computer |
| CN208580396U (en) * | 2018-08-06 | 2019-03-05 | 浙江宇视科技有限公司 | Data dump device and computer |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110262647A (en) | 2019-09-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110262647B (en) | CMOS data clearing circuit and computer equipment | |
| US7427882B2 (en) | Method and apparatus for switching on a voltage supply of a semiconductor circuit and corresponding semiconductor circuit | |
| US9356554B2 (en) | Relaxation oscillator with current and voltage offset cancellation | |
| CN102870162A (en) | Circuit for verifying the write enable of a one time programmable memory | |
| CN101082833A (en) | Computer system reset device | |
| US20150130502A1 (en) | Circuit and method for detecting a fault attack | |
| CN110829540B (en) | Load access identification method, charging control method and device | |
| JP2010028424A (en) | Reset signal generating circuit | |
| US20060109036A1 (en) | Power-low reset circuit | |
| CN104536551A (en) | Method and device for clearing away information on complementary metal oxide semiconductor (CMOS) | |
| US20140025969A1 (en) | Control circuit for computer | |
| US9438165B2 (en) | RC oscillator | |
| JP2006166305A5 (en) | ||
| US9270121B2 (en) | Control circuit for controlling devices to boot sequentially | |
| WO2003073616A1 (en) | Semiconductor integrated circuit and its reset method | |
| US20140300400A1 (en) | Comparator and clock signal generation circuit | |
| CN107516542B (en) | IO circuit and memory | |
| CN206270863U (en) | Cmos data remove device and computer | |
| US9165661B2 (en) | Systems and methods for switching between voltages | |
| US9866015B2 (en) | Discharge circuit and motherboard utilizing the same | |
| CN114325481B (en) | Power-off duration detection method and device, electronic equipment and storage medium | |
| US20140157010A1 (en) | Power on and off test circuit | |
| CN212063521U (en) | Load access recognition device and charging device | |
| US20130099568A1 (en) | Power supply circuit for memory slots | |
| US10389228B1 (en) | Power supply circuit with surge-supression |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |