CN105633027B - Fan-out wafer grade chip-packaging structure and its manufacturing method - Google Patents

Fan-out wafer grade chip-packaging structure and its manufacturing method Download PDF

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Publication number
CN105633027B
CN105633027B CN201410617786.1A CN201410617786A CN105633027B CN 105633027 B CN105633027 B CN 105633027B CN 201410617786 A CN201410617786 A CN 201410617786A CN 105633027 B CN105633027 B CN 105633027B
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Prior art keywords
chip
power transistor
electrically connected
accommodating area
conductive cover
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CN201410617786.1A
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CN105633027A (en
Inventor
谢智正
许修文
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Wuxi Super Gem Semiconductor Co Ltd
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Wuxi Super Gem Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/24247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A kind of fan-out wafer grade chip-packaging structure and its manufacturing method, including providing a loading plate with peelable glue-line；Multiple chips are attached on peelable glue-line；Coating engagement glue is in the back side of each chip；Conductive cover is provided and covers all chips, and these chips are spaced apart from each other respectively with multiple demarcation plates in conductive cover；Inject molding colloid in conductive cover and execute one solidification manufacturing process, to form moulding bodies；Moulding bodies and loading plate are separated, and forms connection layer in the active surface of chip, to connect these chips；Later, a cutting step is executed, moulding bodies are separated into multiple encapsulating structures.In the manufacturing method of chip-packaging structure of the present invention, after covering chip using conductive cover, then by the gap between molding colloid injection chip and conductive cover and solidifies, can control the size of encapsulating structure, therefore do not need again to carry out moulding bodies thinned.

Description

Fan-out wafer grade chip-packaging structure and its manufacturing method
Technical field
The present invention relates to a kind of semiconductor packages manufacturing process more particularly to a kind of fan-out wafer grade chip-packaging structure and Its manufacturing method.
Background technique
With portable and wearable electronic product development, exploitation has high-effect, small in size, high speed, high quality And multi-functional product becomes trend.In order to make the outer dimension of consumer electronic product towards miniaturization, wafer scale Chip size packages (Wafer Level Chip Scale Package, WLCSP) manufacturing process, which becomes, is carrying out chip package Shi Jing frequently with technological means.
Crystal wafer chip dimension encapsulation manufacturing process and previous technology are maximum the difference lies in that crystal wafer chip dimension Encapsulation manufacturing process is manufacturing process to be directly packaged on wafer, and complete to seal to IC chip (IC chip) together Dress, rather than after first cutting crystal wafer, then IC chip is assembled individually.After carrying out crystal wafer chip dimension encapsulation manufacturing process, The size of finished product is completely equivalent or less times greater than chip size.However, crystal wafer chip dimension encapsulation manufacturing process but limits Configuration (layout) is fanned out to the changeability of (Fan-Out).Therefore, industry also develops the encapsulation of fan-out wafer grade now (Fan-Out WLP) manufacturing process makes circuit board surface adhesion operation simpler to provide more various and elastic routing patterns It is single, improve yield.
In Patent No.: in the U. S. application of US7759163, disclosing a kind of semiconductor module manufacturing method.It provides first Two or more the semiconductor chips being placed on carrier, then moulding material is covered to form molding body.Then, molding body need to be thinned It is detached from the carrier until exposing semiconductor chip, then by semiconductor chip.However, be shaped moulding bodies carries out thinned, appearance again Easily residue glue is left in semiconductor chip surface.Also, if the height of semiconductor chip is inconsistent, and in thinning molding body, having can Semiconductor chip surface can be caused to damage.In addition, outputing channel in moulding bodies using drilling technique, it is then filled with conduction material Material, the rear electrode of semiconductor chip is guided to active surface, manufacturing process is too complicated.
Summary of the invention
Technical problem to be solved by the present invention lies in provide a kind of fan-out wafer grade chip in view of the deficiencies of the prior art Encapsulating structure and its manufacturing method encapsulate the chip being inverted on loading plate by means of conductive cover, and it is subsequent right to remove from Moulding bodies carry out thinned manufacturing process.In addition, multiple chips can be by means of conductive cap in encapsulating structure provided by the invention Body cooperates route articulamentum to be electrically connected.
The technical problem to be solved by the present invention is to what is be achieved through the following technical solutions:
A kind of manufacturing method of chip-packaging structure, includes the following steps；Firstly, providing a loading plate, loading plate has Loading end is formed with peelable glue-line on loading end；Multiple chips are set on the peelable glue-line, wherein each chip has One active surface and a back side, the active surface of these chips are attached on peelable glue-line；Coating engagement glue is in the back side of chip；It mentions For conductive cover, there is conductive cover bottom plate and multiple demarcation plates on bottom plate, these demarcation plates to form multiple accommodating areas； Conductive cover is attached in, to cover these chips, wherein these chips are located in accommodating area and with demarcation plate phase on loading end Mutually interval；Then, injection molding colloid is in conductive cover, to fill the gap between demarcation plate and chip；Execute a solidification Manufacturing process, to form moulding bodies；Moulding bodies and loading plate are separated, wherein the active surface of each chip is located at the first table of moulding bodies Face；Connection layer is formed in the first surface of moulding bodies to connect these chips；Later, a cutting step is executed, by mould Plastomer is separated into multiple encapsulating structures, wherein each encapsulating structure, which has, is formed by conduction rack and by route by conductive cover cutting Articulamentum cutting is formed by line layer.
The present invention provides a kind of encapsulating structure, is suitable for a voltage conversion circuit, including a conduction rack, one first power crystalline substance Body pipe, one second power transistor and a line layer；Conduction rack there is bottom and the first demarcation plate with formed the first accommodating area with Second accommodating area, the first demarcation plate is between the first accommodating area and the second accommodating area, and bottom is divided into the first of mutually insulated Conduction region and the second conduction region, wherein the first demarcation plate and the second conduction region are electrically connected；First power transistor packages are in In one accommodating area, and the drain electrode of the first power transistor is electrically connected to the first conduction region；Second power transistor packages are in In two accommodating areas, and the drain electrode of the second power transistor is electrically connected to the second conduction region；Line layer is electrically connected the first power First active surface of transistor and the second active surface of the second power transistor, wherein the end face of the first demarcation plate, the first power First active surface of transistor and the second active surface of the second power transistor are coplanar, the source electrode of the first power transistor via First demarcation plate and the second conduction region are electrically connected to the drain electrode of the second power transistor.
The present invention also provides a kind of encapsulating structures, are suitable for a voltage conversion circuit, and the encapsulating structure includes: a conduction Frame has a bottom and one first demarcation plate to form one first accommodating area and one second accommodating area, which is located at Between first accommodating area and second accommodating area, the bottom portion is one first conduction region and one second conduction of mutually insulated Area, wherein first demarcation plate and second conduction region are electrically connected；One first power transistor is packaged in first accommodating area In, the drain electrode of first power transistor is electrically connected to first conduction region；One control chip, is packaged in first accommodating area In, which is electrically insulated from first conduction region；One second power transistor is packaged in second accommodating area, should The drain electrode of first power transistor is electrically connected to second conduction region；And a line layer, be formed in the control chip, this To be electrically connected the control on one first active surface of one power transistor and one second active surface of second power transistor Chip, first power transistor and second power transistor；Wherein, the end face of first demarcation plate, first power are brilliant First active surface of body pipe and the second active surface of second power transistor are coplanar, which is located at first function Between rate transistor and second power transistor, the source electrode of first power transistor via first demarcation plate and this second Conduction region is electrically connected to the drain electrode of second power transistor.
In the manufacturing method of the chip-packaging structure provided by the embodiment of the present invention, chip is covered using conductive cover Afterwards, then by the gap between molding colloid injection chip and conductive cover and solidify, can control the size of encapsulating structure, because This does not need again to carry out moulding bodies thinned.In addition, when executing cutting step to moulding bodies, it can be by means of changing the position cut It sets from depth of cut and forms different encapsulating structures.
In order to being further understood that feature and technology contents of the invention, please refer to below in connection with it is of the invention specifically Bright and attached drawing, however, the drawings only provide reference and explanation, is not intended to limit the present invention.
Detailed description of the invention
Fig. 1 is the flow chart of the manufacturing method of the fan-out wafer grade chip-packaging structure of the embodiment of the present invention；
Fig. 2 is the partial cutaway schematic of the loading plate of the embodiment of the present invention；
Fig. 3 A is schematic top plan view of the chip-packaging structure of the embodiment of the present invention in the step S101 of Fig. 1；
Fig. 3 B is diagrammatic cross-section of Fig. 3 A along H-H hatching；
Fig. 4 be the embodiment of the present invention encapsulating structure Fig. 1 the step of in partial cutaway schematic；
Fig. 5 A be the embodiment of the present invention encapsulating structure Fig. 1 the step of in schematic top plan view；
Fig. 5 B is diagrammatic cross-section of Fig. 5 A along I-I hatching；
Fig. 5 C be the embodiment of the present invention encapsulating structure Fig. 1 the step of in partial cutaway schematic；
Fig. 6 be the embodiment of the present invention encapsulating structure Fig. 1 the step of in partial cutaway schematic；
Fig. 7 be the embodiment of the present invention encapsulating structure Fig. 1 the step of in partial cutaway schematic；
Fig. 8 is the encapsulating structure of the embodiment of the present invention in the part section signal formed in the step before connection layer Figure；
Fig. 9 is the encapsulating structure of the embodiment of the present invention in the part section signal formed in the step before connection layer Figure；
Figure 10 is partial cutaway schematic of the encapsulating structure of the embodiment of the present invention in the step of forming connection layer；
Figure 11 is partial cutaway schematic of the encapsulating structure of the embodiment of the present invention in the step of forming connection layer；
Figure 12 A be the embodiment of the present invention encapsulating structure Fig. 1 the step of in schematic top plan view；
Figure 12 B is that part section of the chip-packaging structure of the embodiment of the present invention before the step S109 cutting of Fig. 1 is intended to；
Figure 13 is the section signal after the step S109 cutting in Fig. 1 of the wherein encapsulating structure of an embodiment of the invention Figure；
Figure 14 A is that the encapsulating structure of the embodiment of the present invention is applied to the schematic diagram in circuit；
Figure 14 B is the schematic top plan view of the encapsulating structure of the embodiment of the present invention；
Figure 15 A is that the encapsulating structure of another embodiment of the present invention is applied to the schematic diagram in circuit；
Figure 15 B is the schematic top plan view of the encapsulating structure of another embodiment of the present invention；
Figure 16 A is that the encapsulating structure of the embodiment of the present invention is applied to the schematic diagram in circuit；
Figure 16 B is the schematic top plan view of the encapsulating structure of the embodiment of the present invention；
Figure 17 A be another embodiment of the present invention encapsulating structure Fig. 1 the step of in schematic top plan view；
Figure 17 B is the schematic top plan view of the encapsulating structure of another embodiment of the present invention；
Figure 18 A be further embodiment of this invention encapsulating structure Fig. 1 the step of in schematic top plan view；
Figure 18 B is the schematic top plan view of the encapsulating structure of further embodiment of this invention.
[description of symbols]
Loading plate 1
Loading end 1a
Peelable glue-line 2
First chip 3
First active surface 3a
Second active surface 4a
First back side 3b
Second back side 4b
Second chip 4,41
Third chip 42
Control chip 30
Engage glue 5
Conductive cover 6
Bottom plate 60
Hole for injecting glue 600
First surface 60a
Second surface 60b
First conduction region 60c
Second conduction region 60d
Cut mark 601
Cutting groove 602
Insulation tank 603
Demarcation plate 61
End face 610
First demarcation plate 61a
Second demarcation plate 61b
Third demarcation plate 61c
Accommodating area 620
First accommodating area 620a
Second accommodating area 620b
Frame 62
Molding colloid 7
First molding body 7a
Second molding body 7b
Moulding bodies M1
First encapsulating structure M1 '
Encapsulating structure M2, M3, M4, M5
Substrate 8
Pattern protective layer 9
Be open 9a~9f
Convex block underlying metal pads 10a~10f
Conductor layer 11
Weld pad 12a~12f, 42a
First cutting line 20a, 21a, 22a
Second cutting line 20b, 21b, 22b
Process step S100~S109
Specific embodiment
Be below illustrated recorded in the present invention by means of specific specific example " fan-out wafer grade chip-packaging structure and The embodiment of its manufacturing method ", those of ordinary skill in the art can the content as documented by this specification will readily appreciate that this hair Bright advantage and effect.The present invention also can be implemented or be applied by means of other different specific embodiments, in this specification Every details also can based on different viewpoints and application, carry out without departing from the spirit of the present invention it is various modification and modification.Separately Outside, attached drawing of the invention is only to briefly describe, and is not described according to actual size, that is, unreacted goes out the related practical ruler constituted It is very little, hereby give notice that.The relevant technologies content of the invention, but documented content will be explained in further detail in the following embodiments and the accompanying drawings The technology scope being not intended to limit the invention.
Referring to Fig. 1, its process for the manufacturing method of the fan-out wafer grade chip-packaging structure of one embodiment of the invention Figure.The manufacturing method of fan-out wafer grade chip-packaging structure provided by the embodiment of the present invention can be applied to the encapsulation of chip.
In the step s 100, a loading plate is provided.Loading plate has a loading end, is formed with adhesive on loading end Layer.In step s101, multiple chips are set on peelable glue-line, wherein each chip has active surface and the back side, these The active surface of chip is attached on peelable glue-line.In step s 102, coating engagement glue is in the back side of each chip.In step In S103, conductive cover is provided, there is conductive cover bottom plate and multiple demarcation plates on bottom plate, these demarcation plates to be formed more A accommodating area.
In step S104, conductive cover is attached in, to cover all chips, wherein these chips are difference on loading end It is spaced apart from each other in accommodating area, and with these demarcation plates.In step s105, injection molding colloid is in conductive cover, with Fill the gap between these demarcation plates and chip.In step s 106, solidification manufacturing process is executed, a moulding bodies are formed.? In step S107, moulding bodies and loading plate are separated, wherein the active surface of each chip is positioned at the upper surface of moulding bodies.
Connection layer is formed in step S108 in the upper surface of moulding bodies, to connect these chips and outside line. In step S109, cutting step is executed, moulding bodies are separated into multiple encapsulating structures, wherein each encapsulating structure has by leading Electric lid cutting is formed by conduction rack and is formed by line layer with by the cutting of connection layer.
The details of each step in Fig. 1 will be hereinafter further illustrated with example.It please cooperate referring to Fig. 2, show this hair The partial cutaway schematic of the loading plate of bright embodiment.The loading plate 1 has to be formed on loading end a 1a, the loading end 1a There is a peelable glue-line 2.
The material for constituting loading plate 1 can be conductive or insulation material, such as metal, metal alloy, plastics or stone The materials such as English glass.In addition, peelable glue-line 2 can be laminated on loading plate 1.In one embodiment, peelable glue-line 2 is double Face all has sticking adhesive tape.In embodiments of the present invention, the shape with size of loading plate 1 can be consistent with wafer, e.g. 6 English It is very little, 8 inches or 12 inches.In other embodiments, the shape of loading plate 1 is rectangular.
It please cooperate the vertical view signal that the encapsulating structure of the embodiment of the present invention is shown referring to Fig. 3 A in the step S101 of Fig. 1 Figure.It in the present embodiment, is that a variety of identical or different chips are reconfigured in advance.That is, these chips can basis The needs of practical application, and the multiple predetermined positions being fixed on peelable glue-line 2 respectively.
These chips can be identical or be different semiconductor element, and e.g. power transistor, integrated circuit is first Part or diode etc..Power transistor is, for example, rectilinear power transistor, insulation lock bipolar junction transistor (Insulated Gate Bipolar Transistor, IGBT) or bottom source transverse direction double diffusion OH crystal It manages (bottom-source lateral diffusion MOSFET).Each chip has active surface and the back side, and these cores Piece is attached on peelable glue-line 2 with active surface.
In the present embodiment, by taking one first chip 3 and one second chip 4 adjacent in multiple chips as an example, to be said It is bright.The diagrammatic cross-section of B referring to figure 3., display Fig. 3 A along H-H hatching.First chip 3 have one first active surface 3a and with The first first active surface 3a opposite back side 3b.It can be seen that by Fig. 3 B, the first chip 3 is with the first active surface 3a towards peelable Glue-line 2 and be arranged.Second chip 4 similarly has the second active surface 4a and the second back side 4b, and being attached at active surface 4a can It removes on glue-line 2.
In one example, the first chip 3 and the second chip 4 respectively the first power transistor and the second power transistor, And first chip 3 grid (not shown) and source electrode (not shown) be formed at the first active surface 3a, and the (not shown) that drains is Form the first back side 3b of the first chip 3.Similarly, the grid (not shown) of the second chip 4 and source electrode (not shown) are to be formed In the second active surface 4a, and the (not shown) that drains is the second back side 4b to form the second chip 4.
Referring to figure 4., part section of the chip-packaging structure of the embodiment of the present invention in the step S102 of Fig. 1 is shown Schematic diagram.In Fig. 4, engagement glue 5 is applied to the back side of each chip.It in one embodiment, is to utilize dispensing either halftone Suitable engagement glue 5 is placed in the back side of each chip by the mode of coating.Engage glue 5 can according to the type of chip and Route design needs to select conducting resinl or insulating cement, and wherein conducting resinl is, for example, elargol, and tin cream or copper cream etc. have electric conductivity Grafting material.Insulating cement can be the high thermal paste of insulation.
In the fig. 4 embodiment, the first chip 3 and the second chip 4 are rectilinear power transistor, therefore are coated on first The engagement glue 5 of the back side 4b of the back side 3b of chip 3 and the second chip 4 is conducting resinl.But in other embodiments, when chip is control When coremaking piece, engagement glue is insulating cement.
A and Fig. 5 B referring to figure 5., wherein Fig. 5 A shows the encapsulating structure of the embodiment of the present invention in the step S103 of Fig. 1 Schematic top plan view, Fig. 5 B show Fig. 5 A along the diagrammatic cross-section of I-I hatching.The material for constituting conductive cover 6 can be copper, iron Nickel alloy or other alloys.In the present embodiment, the material for constituting conductive cover 6 is copper alloy, and the thickness of conductive cover is situated between In 25 to 100 μm.In addition, conductive cover can be made by technological means such as etching, punching press or coinings, the present invention is not with this It is limited.
In Fig. 5 A embodiment, conductive cover 6 has a bottom plate 60, a frame 62 and multiple demarcation plates 61, wherein frame 62 define an accommodating space with bottom plate 60, and multiple demarcation plates 61 are to separate multiple be interconnected for accommodating space Accommodating area 620.
The shape of bottom plate 60 can cooperate loading plate 1 shape or chip configuration region and it is rounded, rectangular or other Geometry, the present invention is not limited thereto.Specifically, bottom plate 60 have a first surface 60a and with first surface 60a phase Pair a second surface 60b, wherein first surface 60a be conductive cover 6 the back side.In one embodiment, conductive cover 6 has One is formed in the hole for injecting glue 600 on bottom plate 60.It should be particularly noted that, in the present embodiment, hole for injecting glue 600 is formed at bottom On plate 60, but in other embodiments, hole for injecting glue 600 can also be opened on frame 62, the embodiment of the present invention not as Limit.
In addition, in the present embodiment, can correspond to accommodating area 620 on the first surface 60a of bottom plate 60 and be pre-formed multiple Cut mark 601 (for one marked in figure) and multiple cutting grooves 602 (for one marked in figure).Multiple cutting notes Numbers 601 are staggered with the position of multiple cutting grooves 602 and the position of demarcation plate 61.In the present embodiment, cutting mark 601 is one scarce Mouthful, to define in subsequent cutting step, the position of insulation tank will be formed.Cutting groove 602 is then to define each encapsulation The boundary of structure.Cutting mark 601 and the effect of cutting groove 602 will be described in detail later in this article.In one embodiment, cutting groove 602 width is about 50 μm.
Frame 62 protrudes from the second surface 60b of bottom plate 60, and is located on the neighboring area of bottom plate 60.In addition, frame 62 All chips can be accommodated with the accommodating space that bottom plate 60 is defined.Multiple demarcation plates 61 protrude from the second surface of bottom plate 60 60b separates accommodating space for multiple accommodating areas 620 being interconnected.These accommodating areas 620 are multiple to accommodate respectively Chip, and the size of accommodating area 620 can be designed according to the size of chip.
In one embodiment, multiple demarcation plates 61 are distributed on bottom plate 60 in array, and between two adjacent separator plates Spacing size can be slightly larger than the width of chip, and the height of frame and each demarcation plate 61 is greater than the thickness of chip.
In the embodiment of Fig. 5 B, be by taking the first demarcation plate 61a, the second demarcation plate 61b and third demarcation plate 61c as an example into Row explanation.Specifically, one is defined between the first demarcation plate 61a, the second demarcation plate 61b, third demarcation plate 61c and bottom plate 60 First accommodating area 620a and one second accommodating area 620b, wherein the first demarcation plate 61a is located at the first accommodating area 620a and second Between the 620b of accommodating area.
In addition, wherein Fig. 5 C shows the chip-packaging structure of the embodiment of the present invention in Fig. 1 please continue to refer to Fig. 5 A and Fig. 5 C Step S104 in partial cutaway schematic.In step S104, conductive cover 6 is attached in all to cover on loading end 1a Chip.It is shown in Fig. 5 C, cover when on loading end 1a when attaching conductive cover 6, the first chip 3 and the second chip 4 distinguish position In in the first accommodating area 620a and the second accommodating area 620b.That is, the first demarcation plate 61a is positioned at the first chip 3 and the Between two chips 4.
In addition, in one embodiment, when attaching conductive cover 6 when on loading end 1a, frame 62 and each demarcation plate 61 End face 610 also attach on peelable glue-line 2, thus make the first chip 3 the first active surface 3a and the second chip 4 The end face 610 of two active surface 4a and demarcation plate 61 are coplanar.In addition, the accommodating space of conductive cover 6 only passes through 600 He of hole for injecting glue External world's connection.
First chip 3 is attached at conductive cover 6 by means of the engagement glue 5 of the first back side 3b.In the present embodiment, if first Chip 3 is rectilinear power transistor, and engagement glue 5 is conducting resinl, makes the drain electrode of the first chip 3 can be by means of engaging glue 5 and leading Electric lid 6 is electrically connected.Similarly, the drain electrode of the second chip 4 can also be electrically connected by means of engagement glue 5 and conductive cover 6.? In other embodiments, when chip is control chip, engagement glue 5 is insulating cement, make chip and conductive cover 6 each other electrically every Absolutely.
Then, Fig. 6 is please referred to, shows step S105 and S106 of the chip-packaging structure in Fig. 1 of the embodiment of the present invention In partial cutaway schematic.In step s105, one molding colloid 7 of injection is in conductive cover 6, to fill these demarcation plates Gap between chip.Molding colloid 7 can be any suitable thermoplasticity or thermosetting material, e.g. epoxy substrate The resins such as material, silica gel or photoresist.In one embodiment, the technologies such as molding molding or injection molding can be used to make molding colloid 7 Cover the chip in each accommodating area 620.
In the present embodiment, before injecting molding colloid 7, the hole for injecting glue 600 for first passing through bottom plate 60 takes out accommodating space Vacuum, then molding colloid 7 is injected by hole for injecting glue 600.In the present embodiment, molding colloid 7 is liquid-state silicon gel.
It should be particularly noted that, being in vacuum state inside accommodating space, help to suck molding colloid 7 and flow to each In a accommodating area 620, and stomata generation can be reduced.In one embodiment, during injecting molding colloid 7, can continue or Loading plate 1 is rotated intermittently, to drive conductive cover 6 to rotate, it helps molding colloid 7 quickly inserts each accommodating area 620 It is interior.
Then, in step s 106, a solidification manufacturing process is executed, to form a moulding bodies.In embodiments of the present invention, It is to be solidified molding colloid 7 by means of a heating manufacturing process.In the embodiment in fig 6, first accommodating of the filling of molding colloid 7 By the first chip 3 and the second chip 4 cladding completely in area 620a and the second accommodating area 620b, and by solidification and respectively at first The first molding body 7a and the second molding body 7b is formed in the 620a of accommodating area.
Fig. 7 is please referred to, shows part section of the chip-packaging structure of the embodiment of the present invention in the step S107 of Fig. 1 Schematic diagram.In step s 107, separation moulding bodies M1 and loading plate 1.
First active surface 3a of the first chip 3 and the second active surface 4a of the second chip 4 and the first demarcation plate 61a, The end face 610 of two compartment plate 61b and third demarcation plate 61c is located at the first surface of moulding bodies M1, and (Fig. 7 conductive cover 6 is directed downwardly The side).In addition, in the present embodiment, the second surface (side of Fig. 7 conductive cover 6 upward) of moulding bodies M1 is to lead The first surface 60a of the bottom plate 60 of electric lid 6.In Fig. 7 and display is separated moulding bodies M1 by loading plate 1.By above-mentioned production The upper surface that process is formed by moulding bodies M1 has a more smooth structure, for example, the first demarcation plate 61a and the first chip 3 the One active surface 3a is coplanar, and moulding bodies M1 less easily generates warpage issues, need not also carry out that manufacturing process is thinned.
In step S108, connection layer is formed in the first surface of moulding bodies to connect multiple chips.Implement one In example, before forming connection layer, first moulding bodies overturning (as shown in Figure 8 can be turned the first surface of moulding bodies M1 Turn downward in upward, and by the second surface of moulding bodies M1) it is placed on substrate 8, make the second surface and substrate 8 of moulding bodies M1 In conjunction with, and selectively protective layer is formed in the first surface of moulding bodies M1.Fig. 8 to Fig. 9 is please referred to, is shown respectively of the invention real The chip-packaging structure of example is applied in the partial cutaway schematic formed in each step before connection layer.In Fig. 8 the step of, Moulding bodies M1 is set on substrate 8, and the second surface of moulding bodies M1 is directed towards the setting of substrate 8.Substrate 8 is mainly to carry Moulding bodies M1 can be glass substrate, plastic base either any other material, the embodiment of the present invention and be not intended to limit.
Please continue to refer to Fig. 9.In Fig. 9, the first surface that patterning protective layer 9 covers moulding bodies M1 is formed.Patterning Protective layer 9 can protect the active surface of chip not contaminated position and ruler with formulation connection layer in subsequent fabrication process It is very little.In addition, patterning protective layer 9 has multiple opening 9a~9f, with grid and the source of exposure the first chip 3 and the second chip 4 Pole and the end face 610 of the first demarcation plate 61a and the second demarcation plate 61b.
The means for forming patterning protective layer 9 can be by any known technological means, such as passes through deposition, lithographic and erosion It the manufacturing process such as carves and forms patterning protective layer.In one embodiment, patterning protective layer 9 is dielectric layer, can be phosphorus silicon Glass (phosphosilicate glass), polyimides (polyimide) either nitride (nitride).However, In other embodiments, if the active surface of chip has had passivation layer or protective layer, then the step of can omitting Fig. 9.
In one embodiment, connection layer may include multiple convex block underlying metal pads, conductor layer and multiple weld pads.Please Referring to Fig.1 0 to Figure 11, show the chip-packaging structure of the embodiment of the present invention in each step for forming connection layer respectively Partial cutaway schematic.
Figure 10 is please referred to, forms multiple convex block underlying metal pad 10a~10f in each opening 9a~9f.These convex blocks Underlying metal pad 10a~10f contacts the end face 610 of the second demarcation plate 61b, the grid of the first chip 3 and source electrode, first point respectively The grid and source electrode of the end face 610 of partition 61a and the second chip 4.In addition, forming a conductor layer on patterning protective layer 9 11, connection convex block underlying metal pad 10c and convex block underlying metal pad 10d.
It should be particularly noted that, convex block underlying metal pad 10c is electrically coupled to the source electrode of the first chip 3, and it is another convex Block underlying metal pad 10d is the drain electrode for being electrically connected the second chip 4.That is, being connected to convex block bottom forming conductor layer 11 When between layer metal gasket 10c and 10d, the drain electrode of the source electrode and the second chip 4 of the first chip 3 can be made to be electrically connected.
Then, Figure 11 is please referred to, is padded in each convex block underlying metal and is respectively formed a weld pad 12a~12f on 10a~10f, Using the contact as connection outside line.Specifically, in the embodiment in figure 11, positioned at the end face 610 of the second demarcation plate 61b On weld pad 12a the drain electrode of the first chip 3 can be electrically connected to by means of the second demarcation plate 61b and bottom plate 60.Therefore, weld pad 12a can be used as voltage input (VIN) weld pad.In addition, the weld pad 12b that is located on the grid of the first chip 3 and being located at the Weld pad 12e on the grid of two chips 4, can be respectively as upper gate pad and lower gate pad.
As previously mentioned, the drain electrode of the source electrode of the first chip 3 and the second chip 4 by conductor layer 11, the first demarcation plate 61a with And bottom plate 60 is electrically connected.Therefore, the weld pad 12c on the source electrode of the first chip 3 and in the end face of the first demarcation plate 61a Weld pad 12d on 610 all can be used as switching node weld pad.
In addition, the weld pad 12f being located on the source electrode of the second chip 4 can be used as ground pad.In the present embodiment, the second core Piece 4 has multiple source electrodes.In this case, multiple source electrodes of the second chip 4 can be respectively formed multiple weld pad 12f, and these Weld pad 12f is all as ground pad.
In the above-described embodiment, assume that the first chip 3 is said with the second chip 4 for rectilinear power transistor It is bright.When chip is other semiconductor elements, the mode that can be routed according to the needs change of application circuit, and the shape on active surface At different connection layers.Therefore, in the present invention, it is not intended to limit the state sample implementation of connection layer.
After the production for completing connection layer, substrate 8 is removed by moulding bodies M1 second surface.At this point it is possible to core Piece is tested, and with manufacturing process such as laser labels.
Then, Figure 12 A and Figure 12 B are please referred to, wherein Figure 12 A shows the chip-packaging structure of the embodiment of the present invention in Fig. 1 Step S109 in schematic top plan view, Figure 12 B show the embodiment of the present invention chip-packaging structure cut in the step S109 of Fig. 1 Part section before cutting is intended to.Please refer to Figure 13, the display present invention wherein the encapsulating structure of an embodiment Fig. 1 the step of Diagrammatic cross-section after S109 cutting.
In step S109, a cutting step is executed, moulding bodies M1 is separated into multiple encapsulating structures.Each encapsulating structure A line layer is formed by with by the cutting of connection layer with a conduction rack is formed by by the cutting of conductive cover 6.It is executing It when cutting step, is cut by the second surface of moulding bodies M1.It, can be by means of mechanical knife when executing cutting step Have (such as: diamond cutter) or is completed using wet etching.
In embodiments of the present invention, can according to chip by function mode in circuit, come change the position of cutting with And depth, to form different encapsulating structures.In the embodiment of Figure 12 A, after moulding bodies M1 is cut, the first chip 3 with Second chip 4 is encapsulated in jointly in one first encapsulating structure M1 ', as shown in figure 13.
As previously mentioned, in embodiments of the present invention, cutting note has been formed on the bottom plate 60 of conductive cover 6 as shown in figure 12 The mark of number 601 depths of cut different from 602 two kinds of cutting groove can be along cutting mark 601 to mould so as in cutting step Plastomer M1 carries out shallow cutting step (the first cutting line 20a of such as Figure 12 A), and cut through step (as schemed along cutting groove 602 The second cutting line 20b of 12A).
Specifically, Figure 12 A is please referred to, it, can be according to the position of cutting mark 601, along first when executing cutting step Cutting line 20a executes shallow cutting step by the second surface of moulding bodies M1.It is only that will connect the first chip in shallow cutting step 3 and the bottom plate 60 of the second conductive cover 6 between chip 4 cut so that the drain electrode and the drain electrode of the second chip 4 of the first chip 3 It electrically isolates, and does not cut the first molding body 7a.Also, it, will be at the back side of the first encapsulating structure M1 ' after executing shallow cutting step An at least insulation tank 603 is formed, as shown in figure 13.
In addition, further including the position according to cutting groove 602 in cutting step, executing all along the second cutting line 20b Step is worn, to form multiple encapsulating structures being separated from each other.It cuts through step and is included in X-direction along the second cutting line 20b and in X It is cut along the second cutting line 20b in direction.
In the present embodiment, the first encapsulating structure M1 ' of Figure 13 is applicable to voltage conversion circuit, including the first conduction rack, First chip 3, the second chip 4 and first line layer.
Specifically, the first conduction rack at least has bottom and the first demarcation plate 61a, and insole board 60 is cut by above-mentioned After cutting step, bottom plate 60 forms bottom by cutting.It include the first conduction region 60c and the second conduction region 60d in the bottom of Figure 13. The first accommodating area 620a (Figure 13 right-hand component, with reference to 5B figure pair is collectively formed in second conduction region 60d and the first demarcation plate 61a Answer position), and the first accommodating area 620a (Figure 13 left-hand component, ginseng is collectively formed in the first conduction region 60c and the second demarcation plate 61b Examine 5B figure corresponding position).In other words, the first demarcation plate 61a be located at the first accommodating area 620a and the second accommodating area 620b it Between.
After above-mentioned shallow cutting step, bottom plate 60 forms bottom by cutting, and bottom by insulation tank 603 separate for The the first conduction region 60c and the second conduction region 60d of mutually insulated.That is, insulation tank 603 is to be located at the first conduction region 60c Between one second conduction region 60d.However, the first above-mentioned demarcation plate 61a is still electrically connected with the second conduction region 60d.
First chip 3 is packaged in the first accommodating area 620a by the first molding body 7a, and the drain electrode of the first chip 3 be by The first conduction region 60c is electrically connected in conducting resinl.Second chip 4 is then packaged in the second accommodating area 620b by the second molding body 7b It is interior, and the drain electrode of the second chip 4 is electrically connected to the second conduction region 60d by means of conducting resinl.First envelope of the embodiment of the present invention In assembling structure M1 ', one second demarcation plate 61b is further included.Second demarcation plate 61b is formed in the side of the first conduction rack, and with The first accommodating area 620a is collectively formed in one demarcation plate 61a.
First line layer is formed on the active surface 3a of the first chip 3 and the active surface 4a of the second chip 4, to be electrically connected First chip 3 and the second chip 4.Specifically, as described above, first line layer may include formed in Figure 10 into Figure 11 it is more A convex block underlying metal pad 10a~10f, conductor layer 11 and multiple weld pad 12a~12f.First line layer is directed to the first core Connection layer cutting above first active surface 3a of piece 3 and the second active surface 4a of the second chip 4 is formed by a route Layer.Such as Figure 12 B, after being cut through along the second cutting line 20b, connection layer forms line layer above Figure 13.
In addition, at least with gate pad, once grid weldering on a voltage input weld pad, one in these weld pads 12a~12f Pad, at least a switching node weld pad and an at least ground pad.Voltage input weld pad is conductive by the second demarcation plate 61b and first Area 60c is electrically connected at the drain electrode of the first chip 3, such as weld pad 12a.Upper gate pad is electrically connected to the grid of first chip 3 Pole, such as weld pad 12b.Lower gate pad is electrically connected to the grid of the second chip 4, such as weld pad 12e.Switching node weld pad electrically connects It is connected to the drain electrode of the source electrode and the second chip 4 of the first chip 3, such as weld pad 12c and 12d.Ground pad is then electrically connected the second core The source electrode of piece 4, such as weld pad 12f.In the present embodiment, the second chip 4 is that there are two ground pads for tool.
In the above-described embodiment, the first chip 3 and the second chip 4 are common cooperations in same circuit, such as in voltage It is operated in conversion circuit, therefore, the first chip 3 and the second chip 4 are to be encapsulated in the first encapsulating structure M1 ' jointly.At it In his embodiment, two adjacent the first chips 3 and the second chip 4 can also be operated on individually in circuit.In this case, may be used In cutting step, the first chip 3 and the second chip 4 are cut open to form encapsulating structure independent.
Please refer to Figure 14 A and Figure 14 B.Figure 14 A shows that the encapsulating structure of the embodiment of the present invention is applied to the signal in circuit Figure.Figure 14 B shows the schematic top plan view of the encapsulating structure of the embodiment of the present invention.It can be seen that by Figure 14 A and Figure 14 B, in Figure 14 B Each weld pad of first encapsulating structure M1 ' can be directly as the contact of external circuit.For example, control element (not shown) VIN pin can be electrically connected to weld pad 12a, and GH pin, which can be electrically connected to weld pad 12b, SW pin, can be electrically connected to weld pad 12c, GL pin can be electrically connected to weld pad 12d and GND pin can be electrically connected to weld pad 12f.
That is, envelope made by manufacturing method using the fan-out wafer grade chip-packaging structure of the embodiment of the present invention Assembling structure has established the electric connection between chip by means of conduction rack and line layer.Therefore, the encapsulation of the embodiment of the present invention Structure is actually the semi-finished product of circuit element, and may be directly applied in circuit.
Please refer to Figure 15 A and Figure 15 B.Figure 15 A shows that the encapsulating structure of another embodiment of the present invention is applied in circuit Schematic diagram.Figure 15 B shows the schematic top plan view of the encapsulating structure of another embodiment of the present invention.
Figure 15 A shows another voltage conversion circuit.Compared to the voltage conversion circuit of Figure 14 A, in the circuit diagram of Figure 15 A In, three power transistors have been used, one of them is the power transistor (high-side MOSFET) of high side, and other two A power transistor (low-side MOSFET) for downside.
In the present embodiment, it can be formed by means of design cutting position appropriate and depth of cut applied in Figure 15 A Encapsulating structure M2.Encapsulating structure M2 has first chip 3 and two the second chips 41, all positions of the second chip of two of them 41 In the second accommodating area 620b (refer to Fig. 5 B corresponding position), and the drain electrode of two the second chips 41 all with the second conduction region 60d It is electrically connected and (refers to Figure 13).In the present embodiment, cutting step is executed to form the cutting mode of encapsulating structure M2 and previous Embodiment is identical.
In addition, a third chip 42 can be further included other than the first chip 3 and the second chip 41 in encapsulating structure, In the first chip 3 and the second chip 41 be active member, third chip 42 is passive device, such as diode, display such as the following figure 16A and Figure 16 B.
Specifically, Figure 16 A and Figure 16 B are please referred to.Figure 16 A shows that the encapsulating structure of another embodiment of the present invention is applied to Schematic diagram in circuit.Figure 16 B shows the schematic top plan view of the encapsulating structure of another embodiment of the present invention.Shown in Figure 16 A In voltage conversion circuit, other than application high side power transistor and low side power transistor, the power transistor of downside is simultaneously Join a diode.
In encapsulating structure M3 shown in Figure 16 B other than the first chip 3 and the second chip 41, a third chip is further included 42, wherein the first chip 3 is packaged in the first accommodating area 620a, and the second chip 41 is packaged in second with third chip 42 In the 620b of accommodating area.In the present embodiment, the first chip 3 and the second chip 41 are all power transistor, and third chip 42 is Diode.In addition, the first chip 3, the second chip 4 can be by lead frames and line layer according to shown in Figure 16 A with third chip 42 Circuit diagram be electrically connected.In the present embodiment, cutting step is executed to form the cutting mode of encapsulating structure M2 with before One embodiment is identical.
In other embodiments, another encapsulating structure can be formed by means of changing cutting position and depth of cut.It please refers to Figure 17 A and Figure 17 B.Figure 17 A shows schematic top plan view of the encapsulating structure of another embodiment of the present invention in cutting step.Figure 17 B Show the schematic top plan view of the encapsulating structure of another embodiment of the present invention.
In the embodiment of Figure 12 A, shallow cutting step only is executed along the first cutting line 20a in the Y direction.In Figure 17 A Embodiment in, when executing cutting step, other than executing shallow cutting step along the first cutting line 21a in the Y direction, also exist Shallow cutting step is executed along the first cutting line 21a in the side X.In addition, all being executed along the second cutting line 21b in X-direction and Y-direction Step is cut through to form multiple encapsulating structure M4.Figure 17 B is please referred to, the encapsulating structure M4 after cutting includes two adjacent but be located at First chip 3 of different accommodating areas and two the second chips 4 that are adjacent but being located at different accommodating areas.
In an alternative embodiment of the invention, can convert the voltage into control chip in circuit, high side power transistor with it is low Side power transistor is mutually encapsulated into an encapsulating structure.Please refer to Figure 18 A and Figure 18 B.Figure 18 A shows the another implementation of the present invention Schematic top plan view of the encapsulating structure of example in cutting step.Figure 18 B shows bowing for the encapsulating structure of further embodiment of this invention Depending on schematic diagram.
Encapsulating structure M5 includes control chip 30, the first chip 3 and the second chip 4.Wherein control chip 30 is by means of leading Coil holder and line layer can be electrically connected to the control terminal of the first chip 3 and the second chip 4.In the present embodiment, chip 30 is controlled It is neighbouring from the first chip 3 but be placed in different accommodating areas, and then correspondence is placed in two accommodating areas to the second chip 4 In.
As shown in Figure 18 A, when executing cutting step, shallow cutting step only is executed along the first cutting line 22a in the Y direction Suddenly, with the drain electrode of electrically isolation the first chip 3 and the second chip 4.In addition, all along the second cutting line in X-direction and Y-direction 21b execution cuts through step to form multiple encapsulating structure M5.
In conclusion beneficial effects of the present invention can be, the chip-packaging structure provided by the embodiment of the present invention Manufacturing method in, after covering chip using conductive cover, then molding colloid injected into the gap between chip and conductive cover And solidified, the size thinning of encapsulating structure can be made, and do not need to grind moulding bodies.In addition, to moulding bodies When executing cutting step, different encapsulating structures can be formed from depth of cut by means of changing the position of cutting.
In addition, encapsulating structure provided by the embodiment of the present invention, directly being formed on the electrode may be directly connected to circuit board Weld pad, dead resistance and parasitic inductance can be reduced.When the package module of the present embodiment is applied in circuit element, can be promoted The efficiency of element running.The encapsulating structure of the embodiment of the present invention simultaneously has conduction rack, it is possible to provide preferable heat dissipation effect.
The foregoing is merely preferable possible embodiments of the invention, claim non-therefore that limitation is of the invention protects model It encloses, therefore all equivalence techniques variations done with description of the invention and accompanying drawing content, it is both contained in claim of the invention In protection scope.

Claims (13)

1. a kind of manufacturing method of fan-out wafer grade chip-packaging structure, which is characterized in that the fan-out wafer grade chip package The manufacturing method of structure includes:
One loading plate is provided, there is a loading end, be formed with a peelable glue-line on the loading end；
Multiple chips are set on the peelable glue-line, wherein each chip has an active surface and a back side, multiple cores Multiple active surfaces of piece are attached on the peelable glue-line；Coating engagement glue is in the back side of multiple chips；
One conductive cover is provided, there are a bottom plate and multiple demarcation plates on the bottom plate, multiple demarcation plates form more A accommodating area；The conductive cover has a frame, and the height of multiple demarcation plates and the frame is greater than multiple chips Thickness,
The conductive cover is attached in, to cover multiple chips, the plurality of chip is located at multiple on the loading end Be spaced apart from each other in the accommodating area and with multiple demarcation plates, and the conductive cover be connected to by the engagement glue connection it is multiple described The back side of chip；And in the step of attaching the conductive cover to the loading end, the end face of the frame and demarcation plate is pasted to On peelable glue-line,
A molding colloid is injected in the conductive cover, between filling between multiple demarcation plates and multiple chips Gap；
A solidification manufacturing process is executed, to form a moulding bodies；
The moulding bodies and the loading plate are separated, wherein the active surface of each chip is located at a first surface of the moulding bodies；
A connection layer is formed in the first surface of the moulding bodies to connect multiple chips；And execute a cutting step Suddenly, which is separated into multiple encapsulating structures, wherein each encapsulating structure, which has, cuts institute's shape by the conductive cover At a conduction rack with by the connection layer cutting be formed by a line layer；
One first encapsulating structure of multiple encapsulating structures include one first chip and one second chip, one first conduction rack and One first line layer, which has one first demarcation plate, and between first chip and second chip, this One chip and second chip are electrically connected by first conduction rack and the first line layer.
2. the manufacturing method of fan-out wafer grade chip-packaging structure as described in claim 1, which is characterized in that first chip For one first power transistor, which is one second power transistor, the first line layer have gate pad on one, Once gate pad, a switching node weld pad and an at least ground pad, wherein on this gate pad be electrically connected to this first The grid of power transistor, the lower gate pad are electrically connected to the grid of second power transistor, the switching node weld pad The source electrode of first power transistor and the drain electrode of second power transistor are electrically connected to by first conduction rack.
3. the manufacturing method of fan-out wafer grade chip-packaging structure as described in claim 1, which is characterized in that the conductive cover The back side there are multiple cutting grooves to define the boundaries of multiple encapsulating structures.
4. the manufacturing method of fan-out wafer grade chip-packaging structure as described in claim 1, which is characterized in that the conductive cover The back side include multiple cutting marks, and the cutting step further includes:
The bottom plate of the conductive cover is cut according to the cutting mark to be formed at least in the back side of each encapsulating structure One insulation tank, at least an insulation tank makes the conduction rack be divided at least two conduction regions for this.
5. the manufacturing method of fan-out wafer grade chip-packaging structure as described in claim 1, which is characterized in that first encapsulation Structure further includes a third chip, and wherein first chip and second chip are active member, which is passive member Part, first chip, second chip and the third chip are mutually electrically connected by first conduction rack and the first line layer It connects.
6. the manufacturing method of fan-out wafer grade chip-packaging structure as claimed in claim 5, which is characterized in that first chip It is power transistor with second chip, which is diode.
7. the manufacturing method of fan-out wafer grade chip-packaging structure as described in claim 1, which is characterized in that first encapsulation Structure further includes a control chip, by first conduction rack and the first line layer be electrically connected to first chip and this The control terminal of two chips.
8. the manufacturing method of fan-out wafer grade chip-packaging structure as claimed in claim 7, which is characterized in that be bonded the control The engagement glue of the back side of chip and first conduction rack is insulating cement.
9. a kind of encapsulating structure that the manufacturing method using fan-out wafer grade chip-packaging structure described in claim 1 manufactures, Suitable for a voltage conversion circuit, which is characterized in that the encapsulating structure includes:
One conduction rack has a bottom and one first demarcation plate to form one first accommodating area and one second accommodating area, this first Demarcation plate is located between first accommodating area and second accommodating area, and the bottom portion is one first conduction region and one of mutually insulated Second conduction region, wherein first demarcation plate and second conduction region are electrically connected；
One first power transistor is packaged in first accommodating area, and the drain electrode of first power transistor is electrically connected to this First conduction region, first conduction region are connected to the back side of first power transistor via a conducting resinl；
One second power transistor is packaged in second accommodating area, and the drain electrode of second power transistor is electrically connected to this Second conduction region, second conduction region are connected to the back side of second power transistor via the conducting resinl；And
One line layer is electrically connected the second active of the first active surface and second power transistor of first power transistor Face；
Wherein, the end face of first demarcation plate, first power transistor the first active surface and second power transistor Second active surface is coplanar, and the source electrode of first power transistor is electrically connected via first demarcation plate and second conduction region To the drain electrode of second power transistor.
10. encapsulating structure as claimed in claim 9, which is characterized in that the line layer has gate pad, once grid on one Weld pad, a switching node weld pad and an at least ground pad, wherein gate pad is electrically connected to first power crystal on this The grid of pipe, the lower gate pad are electrically connected to the grid of second power transistor, the switching node weld pad by this One demarcation plate and second conduction region are electrically connected to the source electrode of first power transistor and the leakage of second power transistor Pole.
11. encapsulating structure as claimed in claim 9, which is characterized in that the bottom is formed with an insulation tank, and it is conductive to be located at first Between the second conduction region of Qu Yuyi.
12. encapsulating structure as claimed in claim 9, which is characterized in that further include one second demarcation plate, positioned at the conduction rack Side, wherein second demarcation plate and first demarcation plate form first accommodating area.
13. a kind of encapsulating structure that the manufacturing method using fan-out wafer grade chip-packaging structure described in claim 1 manufactures, Suitable for a voltage conversion circuit, which is characterized in that the encapsulating structure includes:
One conduction rack has a bottom and one first demarcation plate to form one first accommodating area and one second accommodating area, this first Demarcation plate is located between first accommodating area and second accommodating area, and the bottom portion is one first conduction region and one of mutually insulated Second conduction region, wherein first demarcation plate and second conduction region are electrically connected；
One first power transistor is packaged in first accommodating area, and the drain electrode of first power transistor is electrically connected to this First conduction region；
One control chip, is packaged in first accommodating area, which is electrically insulated from first conduction region；
One second power transistor is packaged in second accommodating area, and the drain electrode of first power transistor is electrically connected to this Second conduction region；And
One line layer is formed in one first active surface and second power crystal of the control chip, first power transistor To be electrically connected the control chip, first power transistor and second power transistor on one second active surface of pipe；
Wherein, the end face of first demarcation plate, first power transistor the first active surface and second power transistor Second active surface is coplanar, which is located between first power transistor and second power transistor, this The source electrode of one power transistor is electrically connected to second power transistor via first demarcation plate and second conduction region Drain electrode.
CN201410617786.1A 2014-11-05 2014-11-05 Fan-out wafer grade chip-packaging structure and its manufacturing method Active CN105633027B (en)

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