CN116207062A - Packaging structure of semiconductor device and packaging method thereof - Google Patents

Packaging structure of semiconductor device and packaging method thereof Download PDF

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Publication number
CN116207062A
CN116207062A CN202111455893.5A CN202111455893A CN116207062A CN 116207062 A CN116207062 A CN 116207062A CN 202111455893 A CN202111455893 A CN 202111455893A CN 116207062 A CN116207062 A CN 116207062A
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chip
tsv
active region
holes
conductive layer
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Chinese (zh)
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杨洋
邱松
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Wuxi China Resources Huajing Microelectronics Co Ltd
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Wuxi China Resources Huajing Microelectronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Abstract

The invention provides a packaging structure and a packaging method of a semiconductor device, which are applied to the technical field of semiconductors. The packaging structure specifically comprises a chip, a plurality of TSV through holes manufactured on the front side and the back side of the chip and a protective layer on the back side of the chip; the first TSV semi-through holes are formed in the back of the chip corresponding to the active area, the second TSV through holes are formed in the chip corresponding to the non-active area, the back of the chip corresponding to the non-active area is communicated with the front of the chip through the second TSV through holes, then the conducting layer is filled in the chip through holes, so that the electrodes arranged on the back of the chip corresponding to the active area are electrically connected to the first conducting column and the second conducting column of the non-active area on the front of the chip, the electrodes on the back of the chip are led to the front of the chip from the inside of the chip through the conducting columns, a traditional wire bonding process is not needed, packaging resistance and parasitic inductance of a packaging structure are reduced, and heat dissipation capacity of the packaging structure is improved.

Description

Packaging structure of semiconductor device and packaging method thereof
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a semiconductor device packaging structure and a semiconductor device packaging method.
Background
With the continuous development of the semiconductor industry, the requirements of semiconductors are higher and higher, and it is expected that the electrical properties of semiconductors are better and the manufacturing cost is lower and lower. The power semiconductor is a core device for power electronic power conversion and circuit control, the low-voltage MOSFET power device rapidly develops to high power density and miniaturization in recent years, and the low-voltage MOSFET device has wide application places, but the packaging volume requirement is smaller and smaller, and the requirement accelerates the development of the low-voltage MOSFET miniaturization and high-density packaging technology.
At present, the specific process of the existing miniaturized packaging technology of the low-voltage MOSFET power device comprises the following steps: the method comprises the steps of taking a lead frame as a base, then sealing a chip (formed with a low-voltage MOSFET power device) on the lead frame through a conductive film sealing piece made of a material such as solder paste, then leading out electrodes of the chip through copper wire solder (wire bonding), and finally plastic packaging the chip and the outside of the lead frame through a plastic packaging material made of a material such as epoxy resin so as to isolate the chip from external pollution.
However, since the electrodes of the chip are led out by adopting a wire bonding mode in the miniaturization packaging process of the existing low-voltage MOSFET power device, the problem of high packaging resistance and parasitic inductance (or mutual inductance) is likely to be caused; in addition, in the prior art, an insulating material is used as a plastic packaging material to isolate the chip from external pollution, and the problem of poor heat dissipation of a product can be caused by the problems of low heat conduction and the like of the plastic packaging material, so that the heat dissipation requirement of a high-power device cannot be met.
Disclosure of Invention
The invention aims to provide a packaging structure and a packaging method of a semiconductor device, which are used for reducing the packaging resistance and parasitic inductance of the packaging structure and improving the heat dissipation capacity of the packaging structure.
In order to achieve the above and other related objects, a first aspect of the present invention provides a package structure of a semiconductor device, comprising:
the semiconductor device comprises a plurality of chips, a plurality of first TSV semi-through holes and a plurality of second TSV through holes, wherein each chip comprises an active region and a non-active region, the back of the chip corresponding to the active region is provided with the plurality of first TSV semi-through holes, and the chip corresponding to the non-active region is provided with the plurality of second TSV through holes so as to communicate the back and the front of the chip corresponding to the non-active region through the second TSV through holes;
a conductive layer filling each of the first and second TSV semi-through holes to form first and second conductive pillars, and electrically connecting an electrode disposed on a back surface of a chip corresponding to the active region to a non-active region on a front surface of the chip through the first and second conductive pillars, the conductive layer extending over an entire surface of the back surface of the chip and a portion of a surface of the front surface of the chip;
and the protective layer is arranged on the surface of the conductive layer covered on the back surface of the chip.
Further, the front surface of the active region of each of the chips may be provided with a source electrode and a gate electrode, and the back surface thereof may be provided with a drain electrode.
Further, the depth of the first TSV semi-via may be less than the depth of the second TSV via.
Further, the depth of the first TSV half-via may be less than half the thickness of the chip.
Further, the material of the protective layer may be an insulating material, and the insulating material may include silicon nitride or silicon oxide.
Further, the chip may include a power MOSFET chip.
Further, the material of the conductive layer may be metallic copper.
The second aspect of the invention also provides a packaging method based on the same inventive concept, which specifically comprises the following steps:
providing a plurality of chips, wherein each chip comprises an active area and a non-active area, the front side of each chip is provided with a source electrode and a grid electrode, and the back side of each chip is provided with a drain electrode;
performing a first etching process on the chip to form a plurality of first TSV semi-through holes on the back surface of the chip corresponding to the active region, and forming a plurality of second TSV through holes in the chip corresponding to the non-active region, wherein the second TSV through holes communicate the back surface and the front surface of the chip corresponding to the non-active region;
forming a conductive layer, wherein the conductive layer fills each first TSV semi-through hole and each second TSV through hole to form a first conductive column body and a second conductive column body, so that a drain electrode arranged on the back surface of a chip corresponding to the active region is electrically connected to a non-active region on the front surface of the chip through the first conductive column body and the second conductive column body, and the conductive layer extends to cover the whole surface of the back surface of the chip and the whole surface of the front surface of the chip;
performing a second etching process on the conductive layer covered on the front surface of the chip to remove part of the conductive layer, and simultaneously, reserving the conductive layer covered on the top surfaces of the source electrode and the grid electrode in the active region and the conductive layer covered on the top surface of the second TSV through hole in the non-active region and between the second TSV through hole and other adjacent second TSV through holes to separate three electrodes on the front surface of the chip;
and forming a protective layer on the surface of the conductive layer covered on the back surface of the chip.
Further, after performing the first etching process on the chip and before forming the conductive layer, the packaging method may further include;
and forming a seed layer on the surfaces of the first TSV semi-through hole, the second TSV through hole and the front surface and the back surface of the chip.
Further, the packaging method may further include performing a lapping thinning process on the chip before performing the first etching process on the chip.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
the invention provides a novel packaging structure of a semiconductor device, which comprises a chip, a plurality of TSV through holes manufactured on the front side and the back side of the chip and a protective layer on the back side of the chip; the first conductive column and the second conductive column are formed by electrically connecting the electrode arranged on the back surface of the chip corresponding to the active region to the non-active region on the front surface of the chip, so that the electrode on the back surface of the chip is led to the front surface of the chip from the inside of the chip through the conductive column, a traditional wire bonding process is not needed, the packaging resistance and parasitic inductance of the packaging structure are reduced, and the heat dissipation capability of the packaging structure is improved.
Furthermore, in practical application, a groove structure is arranged in the chip active region, so that after the chip is thinned, the problem of warping occurs due to different structures of two surfaces of the chip exists. In the packaging structure provided by the invention, the back surface of each chip active region is provided with the plurality of first TSV semi-through holes similar to the groove structure, so that the groove matching of the front surface and the back surface of the chip active region is realized, and the problems of other process circulation and use failure caused by the stress problem after the chip is thinned due to different structures are further improved.
In addition, in the packaging structure provided by the invention, the two sides of the chip are both provided with thick copper, and the protective layer with the isolation function is directly stuck on the surface of the conductive layer covered on the back of the chip, so that the chip is not required to be wrapped by plastic packaging materials like the prior art, and the heat dissipation capacity of the packaging structure is improved.
Drawings
Fig. 1 is a schematic structural diagram of a package structure of a semiconductor device according to an embodiment of the present invention;
fig. 2 is a flow chart of a packaging method of a packaging structure of a semiconductor device according to an embodiment of the present invention;
fig. 3a to 3e are schematic structural views of a package structure of a semiconductor device according to an embodiment of the present invention in a manufacturing process;
wherein, the reference numerals are as follows:
1-chip, A-active region, B-non-active region, 2/2 c-2 f-conductive layer, 3-protective layer, G-grid, D-drain, S-source, 101-first TSV semi-through hole, 102-second TSV through hole, 2 a-first conductive column and 2B-second conductive column.
Detailed Description
As described in the background art, the specific process of the existing miniaturized packaging technology of the low-voltage MOSFET power device at present includes: the method comprises the steps of taking a lead frame as a base, then sealing a chip (formed with a low-voltage MOSFET power device) on the lead frame through a conductive film sealing piece made of a material such as solder paste, then leading out electrodes of the chip through copper wire solder (wire bonding), and finally plastic packaging the chip and the outside of the lead frame through a plastic packaging material made of a material such as epoxy resin so as to isolate the chip from external pollution.
However, since the electrodes of the chip are led out by adopting a wire bonding mode in the miniaturization packaging process of the existing low-voltage MOSFET power device, the problem of high packaging resistance and parasitic inductance (or mutual inductance) is likely to be caused; in addition, in the prior art, an insulating material is used as a plastic packaging material to isolate the chip from external pollution, and the problem of poor heat dissipation of a product can be caused by the problems of low heat conduction and the like of the plastic packaging material, so that the heat dissipation requirement of a high-power device cannot be met.
Therefore, the invention provides the packaging structure and the packaging method of the semiconductor device, so that the heat dissipation capacity of the packaging structure is improved while the packaging resistance and parasitic inductance of the packaging structure are reduced.
The following describes the package structure and the package method of the semiconductor device according to the present invention in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
The following first describes a package structure of a semiconductor device provided by the present invention.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a package structure of a semiconductor device according to an embodiment of the invention. As shown in fig. 1, in the package structure provided by the present invention, it may include:
the chip comprises a plurality of chips 1, wherein each chip 1 comprises an active area A and a non-active area B, a plurality of first TSV semi-through holes are formed in the back of the chip corresponding to the active area A, a plurality of second TSV through holes are formed in the chip corresponding to the non-active area B, and the back and the front of the chip corresponding to the non-active area B are communicated through the second TSV through holes;
a conductive layer 2, wherein the conductive layer 2 fills each of the first and second TSV semi-through holes to form a first conductive pillar 2a and a second conductive pillar 2B, and electrodes arranged on the back surface of the chip corresponding to the active region a are electrically connected to the non-active region B on the front surface of the chip through the first and second conductive pillars 2a and 2B, and the conductive layer 2 extends to cover the whole surface of the back surface of the chip 1 and part of the surface of the front surface of the chip 1;
and a protective layer 3, wherein the protective layer 3 is arranged on the surface of the conductive layer covered on the back surface of the chip 1.
The chips 1 may be power MOSFET chips, and the front surface of the active area a of each chip 1 may be provided with a source S and a gate G, and the back surface thereof may be provided with a drain D. The depth of the first TSV half-via may be smaller than the depth of the second TSV half-via, and illustratively, the depth of the first TSV half-via may be several micrometers smaller than the thickness of the chip 1 to half of the total thickness of the chip 1.
It is to be understood that the depth of the first TSV half-through hole provided in the embodiment of the present invention may be specifically defined according to the actual thickness of the chip, and the present invention only gives a possible case, but it is determined that the depth of the first TSV half-through hole formed in the package structure provided in the present invention must not exceed the thickness of the chip, that is, the first TSV half-through hole is a half-through hole, not a full-through hole like the second TSV half-through hole.
Further, the material of the protective layer 3 may be an insulating material for isolating the package structure, and the insulating material may be silicon nitride or silicon oxide, for example. The material of the conductive layer 2 (specifically including 2 a-2 f) may be metallic copper.
In the embodiment of the present invention, a wafer may be provided first, where the wafer includes a plurality of chips, and each chip is formed with a power MOSFET chip including a source/drain/gate or other high-current power chips (at this time, the wafer including the plurality of chips is not diced yet), and then the plurality of chips that are not diced yet are subjected to thinning, photolithography and etching processes, so as to form a plurality of first TSV half-through holes on the back of the chip corresponding to the active area a, that is, a structure before 2a in the structure shown in fig. 1 is not filled with the conductive layer; and a plurality of second TSV through holes are formed in the chip corresponding to the non-active region B, namely, the structure in which 2B in the structure shown in fig. 1 is not filled with the conductive layer. As can be seen from fig. 1, the second TSV through hole may connect the back side and the front side of the chip corresponding to the non-active region B, so that after the conductive layer 2 is filled, the drain D disposed on the back side of the chip corresponding to the active region a is electrically connected to the non-active region a on the front side of the chip through the formed first conductive pillar 2a and the second conductive pillar 2B, and thus all three electrodes of the chip may be electrically connected to other devices through the front side of the chip.
In summary, according to the package structure provided by the present invention shown in fig. 1, the package structure provided by the present invention may have the following advantages:
(1) In the packaging structure provided by the invention, the two sides of the chip are both provided with thick copper, and the surface of the conducting layer covered on the back of the chip is directly stuck with the protective layer for protecting the back copper from the problem of water vapor oxidation and back insulation, so that the failure caused by interconnection with external devices can be prevented.
(2) Because the electrodes of the existing MOSFET device are distributed on two sides of the chip, all the electrodes of the existing MOSFET device must be led to one side (one side of the chip) when in use, in the embodiment of the invention, the drain electrode on the back of the chip is led to the front of the chip from the inside of the chip through the conductive column body, the traditional wire bonding process is not needed, and therefore the packaging resistance and parasitic inductance of the packaging structure are reduced, and the traditional packaging wire bonding is completely cancelled.
(3) Because the SGT MOSFET is used in a large scale at present, the active area of the chip is provided with grooves, the back of the chip is provided with similar open areas, and in the packaging structure provided by the invention, through forming the TSV through holes in the chip and then plating copper in the TSV through holes, the heat conduction of copper is far higher than that of silicon, so that the heat in the active area of the chip can be rapidly transferred out, the heat dissipation problem can be greatly improved, and the other important reason is that the active area of the chip is provided with grooves, the chip is thinned, the two sides of the chip are provided with warpage due to different structures, the back of the chip is provided with similar groove areas, and the front and back groove matching is carried out, so that the problems of other technological circulation and use failure caused by stress problems after the chip is thinned due to different structures can be improved.
Based on the packaging structure of the semiconductor device, as shown in fig. 2, the invention also provides a packaging method, which specifically comprises the following steps:
step S100, a plurality of chips are provided, each chip comprises an active area and a non-active area, a source electrode and a grid electrode are arranged on the front surface of each chip, and a drain electrode is arranged on the back surface of each chip.
Step 200, performing a first etching process on the chip to open a plurality of first TSV semi-through holes on the back surface of the chip corresponding to the active region, and open a plurality of second TSV through holes in the chip corresponding to the non-active region, where the second TSV through holes communicate the back surface and the front surface of the chip corresponding to the non-active region.
And step S300, forming a conductive layer, wherein the conductive layer fills each of the first TSV semi-through hole and the second TSV through hole to form a first conductive column and a second conductive column, so that the drain electrode arranged on the back surface of the chip corresponding to the active region is electrically connected to the non-active region on the front surface of the chip through the first conductive column and the second conductive column, and the conductive layer extends to cover the whole surface of the back surface of the chip and the whole surface of the front surface of the chip.
And step S400, performing a second etching process on the conductive layer covered on the front surface of the chip to remove part of the conductive layer, and simultaneously, reserving the conductive layer covered on the top surfaces of the source electrode and the grid electrode in the active region and the conductive layer covered on the top surface of the second TSV through hole in the non-active region and between the second TSV through hole and other adjacent second TSV through holes to separate three electrodes on the front surface of the chip.
And S500, forming a protective layer on the surface of the conductive layer covered on the back surface of the chip.
The packaging method according to the present invention will be described in further detail with reference to fig. 3a to 3e and the specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
In step S100, referring specifically to fig. 3a, a plurality of chips 1 are provided, each chip 1 includes an active area a and an inactive area B, and a source S and a gate G are disposed on the front surface of each chip 1, and a drain D is disposed on the back surface of each chip.
In step S200, referring to fig. 3B specifically, a first etching process is performed on the chip 1, so as to open a plurality of first TSV half-through holes 101 on the back surface of the chip corresponding to the active area a, and open a plurality of second TSV through holes 102 in the chip corresponding to the inactive area B, where the second TSV through holes 102 connect the back surface and the front surface of the chip corresponding to the inactive area B.
In this embodiment, after step S100, the chip may be thinned to make the thickness of the chip to be packaged meet the design requirement, and then step S200 is performed.
In step S300, referring specifically to fig. 3c, a conductive layer 2 is formed, the conductive layer 2 fills each of the first TSV half-via 101 and the second TSV half-via 102 to form a first conductive pillar 2a and a second conductive pillar 2B, so that the drain D disposed on the back surface of the chip corresponding to the active area a is electrically connected to the non-active area B on the front surface of the chip through the first conductive pillar 2a and the second conductive pillar 2B, and the conductive layer 2 extends to cover the entire surface of the back surface of the chip and the entire surface of the front surface of the chip. The conductive layer 2 is illustratively a copper layer of a certain thickness.
In this embodiment, a seed layer (not shown) may be formed on the surfaces of the first TSV half-through hole 101, the second TSV half-through hole 102, and the front and back surfaces of the chip 1 after step S200 and before step S300, so as to provide nucleation points, so that the copper layer deposited in step S300 is well adhered to the surfaces of the first TSV half-through hole 101, the second TSV half-through hole 102, and the front and back surfaces of the chip 1.
In step S400, referring specifically to fig. 3d, a second etching process is performed on the conductive layer 2 covered on the front surface of the chip 1, so as to separate the three electrodes on the front surface of the chip while removing part of the conductive layer, and keeping the conductive layers 2d and 2e covered on the top surfaces of the source electrode and the gate electrode in the active area a, and the conductive layer 2f covered on the top surface of the second TSV hole in the inactive area B and between the second TSV hole and other adjacent second TSV holes.
In step S500, a protective layer 3 is formed on the surface of the conductive layer 2c covered on the back side of the chip 1, as shown with specific reference to fig. 3 e.
Since the drawings provided in the embodiments of the present invention are exemplary drawings, only a single chip packaging process is illustrated, and when a wafer includes a plurality of chips, the plurality of chips may be packaged in batch and then diced. Finally, packaging after performing the product FT test on each packaging structure.
In summary, the invention provides a novel packaging structure of a semiconductor device, which specifically comprises a chip, a plurality of TSV through holes manufactured on the front side and the back side of the chip and a protective layer on the back side of the chip; the first conductive column and the second conductive column are formed by electrically connecting the electrode arranged on the back surface of the chip corresponding to the active region to the non-active region on the front surface of the chip, so that the electrode on the back surface of the chip is led to the front surface of the chip from the inside of the chip through the conductive column, a traditional wire bonding process is not needed, the packaging resistance and parasitic inductance of the packaging structure are reduced, and the heat dissipation capability of the packaging structure is improved.
Furthermore, in practical application, a groove structure is arranged in the chip active region, so that after the chip is thinned, the problem of warping occurs due to different structures of two surfaces of the chip exists. In the packaging structure provided by the invention, the back surface of each chip active region is provided with the plurality of first TSV semi-through holes similar to the groove structure, so that the groove matching of the front surface and the back surface of the chip active region is realized, and the problems of other process circulation and use failure caused by the stress problem after the chip is thinned due to different structures are further improved.
In addition, in the packaging structure provided by the invention, the two sides of the chip are both provided with thick copper, and the protective layer with the isolation function is directly stuck on the surface of the conductive layer covered on the back of the chip, so that the chip is not required to be wrapped by plastic packaging materials like the prior art, and the heat dissipation capacity of the packaging structure is improved.
In addition, it will be understood that while the invention has been described in terms of preferred embodiments, the above embodiments are not intended to limit the invention. Many possible variations and modifications of the disclosed technology can be made by anyone skilled in the art without departing from the scope of the technology, or the technology can be modified to be equivalent. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.
It is also to be understood that this invention is not limited to the particular methodology, compounds, materials, manufacturing techniques, uses, and applications described herein, as such may vary. It should also be understood that the terminology described herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a step" means a reference to one or more steps, and may include sub-steps. All conjunctions used should be understood in the broadest sense. Thus, the word "or" should be understood as having the definition of a logical "or" rather than a logical exclusive or "unless the context clearly indicates the contrary. Structures described herein will be understood to also refer to the functional equivalents of such structures. Language that may be construed as approximate should be construed unless the context clearly indicates the contrary.

Claims (10)

1. A package structure of a semiconductor device, comprising:
the semiconductor device comprises a plurality of chips, a plurality of first TSV semi-through holes and a plurality of second TSV through holes, wherein each chip comprises an active region and a non-active region, the back of the chip corresponding to the active region is provided with the plurality of first TSV semi-through holes, and the chip corresponding to the non-active region is provided with the plurality of second TSV through holes so as to communicate the back and the front of the chip corresponding to the non-active region through the second TSV through holes;
a conductive layer filling each of the first and second TSV semi-through holes to form first and second conductive pillars, and electrically connecting an electrode disposed on a back surface of a chip corresponding to the active region to a non-active region on a front surface of the chip through the first and second conductive pillars, the conductive layer extending over an entire surface of the back surface of the chip and a portion of a surface of the front surface of the chip;
and the protective layer is arranged on the surface of the conductive layer covered on the back surface of the chip.
2. The semiconductor device package according to claim 1, wherein a source and a gate are provided on a front surface of the active region of each of the chips, and a drain is provided on a back surface thereof.
3. The semiconductor device package structure of claim 1, wherein a depth of the first TSV semi-via is less than a depth of the second TSV via.
4. The semiconductor device package according to claim 3, wherein a depth of the first TSV half-via is less than half a thickness of the chip.
5. The package structure of a semiconductor device according to claim 1, wherein a material of the protective layer is an insulating material, and the insulating material includes silicon nitride or silicon oxide.
6. The semiconductor device package of claim 1, wherein the die comprises a power MOSFET die.
7. The package structure of a semiconductor device according to claim 1, wherein a material of the conductive layer is metallic copper.
8. A packaging method for the packaging structure according to any one of claims 1 to 7, characterized by comprising the steps of:
providing a plurality of chips, wherein each chip comprises an active area and a non-active area, the front side of each chip is provided with a source electrode and a grid electrode, and the back side of each chip is provided with a drain electrode;
performing a first etching process on the chip to form a plurality of first TSV semi-through holes on the back surface of the chip corresponding to the active region, and forming a plurality of second TSV through holes in the chip corresponding to the non-active region, wherein the second TSV through holes communicate the back surface and the front surface of the chip corresponding to the non-active region;
forming a conductive layer, wherein the conductive layer fills each first TSV semi-through hole and each second TSV through hole to form a first conductive column body and a second conductive column body, so that a drain electrode arranged on the back surface of a chip corresponding to the active region is electrically connected to a non-active region on the front surface of the chip through the first conductive column body and the second conductive column body, and the conductive layer extends to cover the whole surface of the back surface of the chip and the whole surface of the front surface of the chip;
performing a second etching process on the conductive layer covered on the front surface of the chip to remove part of the conductive layer, and simultaneously, reserving the conductive layer covered on the top surfaces of the source electrode and the grid electrode in the active region and the conductive layer covered on the top surface of the second TSV through hole in the non-active region and between the second TSV through hole and other adjacent second TSV through holes to separate three electrodes on the front surface of the chip;
and forming a protective layer on the surface of the conductive layer covered on the back surface of the chip.
9. The packaging method of claim 8, wherein after performing a first etching process on the chip and before forming a conductive layer, the packaging method further comprises:
and forming a seed layer on the surfaces of the first TSV semi-through hole, the second TSV through hole and the front surface and the back surface of the chip.
10. The packaging method of claim 8, wherein prior to performing the first etching process on the chip, the packaging method further comprises performing a lapping thinning process on the chip.
CN202111455893.5A 2021-12-01 2021-12-01 Packaging structure of semiconductor device and packaging method thereof Pending CN116207062A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116435258A (en) * 2023-06-13 2023-07-14 中诚华隆计算机技术有限公司 Packaging method and packaging structure of chip

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116435258A (en) * 2023-06-13 2023-07-14 中诚华隆计算机技术有限公司 Packaging method and packaging structure of chip
CN116435258B (en) * 2023-06-13 2023-09-26 中诚华隆计算机技术有限公司 Packaging method and packaging structure of chip

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