CN104332464B - A kind of integrated technique of power device and control device - Google Patents
A kind of integrated technique of power device and control device Download PDFInfo
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- CN104332464B CN104332464B CN201410432745.5A CN201410432745A CN104332464B CN 104332464 B CN104332464 B CN 104332464B CN 201410432745 A CN201410432745 A CN 201410432745A CN 104332464 B CN104332464 B CN 104332464B
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Abstract
The present invention relates to ic manufacturing technology field, more particularly to the integrated technique of a kind of power device and control device, by technique of the invention, power chip and control chip separate design and making can be made, ensure its performance, the advantage of cost, while not using line and conventional encapsulation just to complete the interconnection of control circuit and chip device.And by shared thinning and back metal technique, further reduction manufacturing cost while improve the performance of power device, and is prepared in the deielectric-coating as bonded layer and has radiator structure, further increases the stability of device.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of power device and control device integrated work
Skill.
Background technology
Field-effect transistor (FET) is widely used in various electronic circuits.It belongs to voltage controlled semiconductor device
Part.With input resistance (107~1015 Ω) high, noise is small, low in energy consumption, dynamic range is big, be easily integrated, do not have second breakdown
The advantages of phenomenon, safety operation area field width, the powerful competitor as bipolar transistor and power transistor.And field is imitated
Should pipe control circuit preparation technology it is but completely different with FET, however, the work of FET depend on control electricity
The connection on road.So, while obtain FET controls a technological difficulties of the circuit as this area with it.
At present, main solution has three classes：Discrete device solution, multi-chip module solution and single-chip
Solution.
Discrete device solution is by separately designing and making vertical MOS FET power devices and control circuit core
Piece, is packaged and is connected with device pad using metal lead wire afterwards, to form input, the output pin of each chip, and is welded
It is connected on pcb board.But because each device, chip are required to encapsulation, scheme takes up room greatly, and due to using lead, brings
Larger stray inductance, increased power consumption, and reduce the anti-electromagnetic interference capability of device and bring larger voltage
Overshoot etc., so as to have impact on the reliability of device, and due to employing lead more long between discrete device, increased parasitic electricity
Appearance, power consumption and current over pulse.
Multi-chip module solution (MCM) is by separately designing according to special applications demand and making vertical-type power
Device and control circuit chip, take the different chip packages that special encapsulation scheme will not encapsulated together afterwards.But should
Scheme needs that the source region of device is placed in the back side of silicon chip, and the source region with device in conventional vertical-type power device is placed in silicon chip
Front is inconsistent, therefore existing vertical-type power device is not applied for the program.And multiple chips are spread out connect in the plane,
The area of occupancy is larger.
Single chip solution is, by carrying out special chip design and making, power device and control circuit to be integrated in same
In chip, whole technique is two kinds of summations of the technique of device, and device have passed through unwanted technique, high cost.And power device
The compatibility of the performance of part and control device is not strong, have impact on the optimization of both sides' device performance.
Therefore, the integrated technique of a kind of power MOSFET device and control device how is found, effectively to evade above-mentioned asking
Inscribe the direction that research is endeavoured as those skilled in the art.
The content of the invention
For above-mentioned problem, the present invention discloses the integrated technique of a kind of power device and control device.
A kind of integrated technique of power device and control device, wherein, comprise the following steps：
Offer is provided with the power chip of power device and is provided with the control chip of control circuit；
In deielectric-coating is prepared on the front of the power chip and on the front of the control chip, and in the medium
Radiator structure is prepared in film；
The power chip is vertically bonded to using front bonding technology a bonding chip is formed on the control chip
Afterwards, the back side to the power chip carries out reduction process；
Etch the bonding chip and form some silicon holes, and metal is filled in some silicon holes, with formed by
The interconnection line that the power device is electrically connected with the control circuit, and the power device, the control circuit are distinguished
The metal lead wire electrically connected with the bonding chip external structure.
Above-mentioned power device and the integrated technique of control device, wherein, on the front of the power chip and described
The step of preparing deielectric-coating on the front of control chip, and prepare radiator structure in the deielectric-coating includes：
After first medium film is formed on the front of the power chip, technique is patterned to the first medium film
Some first grooves are formed, and Heat Conduction Material is deposited in some first grooves and form the first radiator structure；
After second medium film is formed on the front of the control chip, technique is patterned to the second medium film
Some second grooves are formed, and Heat Conduction Material is deposited in some second grooves and form the second radiator structure.
Above-mentioned power device and the integrated technique of control device, wherein, the Heat Conduction Material is silver, copper or aluminium.
Above-mentioned power device and the integrated technique of control device, wherein, the power device includes source region electrode and grid
Pole electrode, the control circuit includes the first coordination electrode and the second coordination electrode；
The technique also includes：
In forming the first silicon hole, the second silicon hole and the 3rd silicon hole using etching technics on the bonding chip, and
First silicon hole is exposed the part surface of the part surface of the gate electrode and the first coordination electrode, described
Second silicon hole is exposed the part surface of the source region electrode, and the 3rd silicon hole is by second coordination electrode
Part surface is exposed；
The interconnection line is formed after filling metal in first silicon hole, the second silicon hole and the 3rd silicon hole
With the metal lead wire, the metal lead wire include the first metal lead wire and the second metal lead wire；
Wherein, the gate electrode and first coordination electrode are electrically connected by the interconnection line, by described the
One metal lead wire electrically connects the source region electrode with the bonding chip external structure, by second metal lead wire by institute
The second coordination electrode is stated to be electrically connected with the bonding chip external structure.
Above-mentioned power device and the integrated technique of control device, wherein, the technique also includes：
Metal electrode is formed respectively in the upper surface of the interconnection line, the first metal lead wire, the second metal lead wire.
Above-mentioned power device and the integrated technique of control device, wherein, the technique also includes
After forming the interconnection line, the first metal lead wire, the second metal lead wire, deposited metal layer is with by the power chip
The back side covered；
Continue depositing electrode metal film to be covered with by the upper surface of the metal level；
Partial etching is located at the electrode metal film and metal level above the interconnection line and the metal lead wire, with
Interconnection line top formed the first metal electrode, form above second metal lead wire the second metal electrode, described
3rd metal lead wire top forms the 3rd metal electrode.
Above-mentioned power device and the integrated technique of control device, wherein, the power device is vertical-type power
MOSFET element.
Above-mentioned power device and the integrated technique of control device, wherein, the power chip includes：
Substrate；
Positioned at the epitaxial layer of the substrate top surface；
Positioned at the p-well substrate of the epitaxial layer upper surface；
It is arranged in the p-well substrate and extends to the gate trench in the epitaxial layer；
Grid structure in the gate trench, the grid structure includes groove gate oxidation films and the covering ditch
Groove gate oxidation films bottom and its trench polysilicon Si-gate of side wall.
It is arranged at the grid structure top and the gate electrode electrically connected with the trench polysilicon Si-gate；And
It is arranged at the grid structure top and the source region electrode isolated with the grid structure by dielectric layer.
Above-mentioned power device and the integrated technique of control device, wherein, the technique also includes：
After carrying out reduction process to the back side of the power chip, in one layer of the 3rd Jie of backside deposition of the power chip
Plasma membrane, technique is patterned to the 3rd deielectric-coating, and the part surface of the power chip is exposed；
Power chip described in the 3rd deielectric-coating as mask etching, to form some silicon holes.
Above-mentioned power device and the integrated technique of control device, wherein, the technique also includes：
If power chip to the dielectric layer surface described in the 3rd deielectric-coating as mask etching stops forming hondo
Groove；
Buffer layer is respectively formed in the sidewall surfaces of some grooves；
Continue etching some grooves and form some silicon holes.
Above-mentioned power device and the integrated technique of control device, wherein, the technique is applied to some power chips
Interconnection is realized with a control chip or a power chip and some control chips are realized into interconnection.
Foregoing invention has the following advantages that or beneficial effect：
Power device disclosed by the invention and the integrated technique of control device, can make power chip and control chip mutual
Independent design and making, it is ensured that its performance, the advantage of cost, while not using line, does not use conventional encapsulation just to complete to control
The interconnection of circuit processed and chip device.And by shared thinning and back metal technique, further reduction manufacturing cost, while
The performance of power device is improve, and preparation has radiator structure in the deielectric-coating as bonded layer, further increases device
Stability.
Specific brief description of the drawings
By the detailed description made to non-limiting example with reference to the following drawings of reading, the present invention and its feature, outward
Shape and advantage will become more apparent.Identical mark indicates identical part in whole accompanying drawings.Not can according to than
Example draws accompanying drawing, it is preferred that emphasis is show purport of the invention.
Fig. 1-10 is the flowage structure schematic diagram of the integrated technique of power device and control device in the embodiment of the present invention；
Figure 11 is the flow chart of the integrated technique of power device and control device in the embodiment of the present invention.
Specific embodiment
The present invention is further illustrated with specific embodiment below in conjunction with the accompanying drawings, but not as limit of the invention
It is fixed.
As shown in figure 11, the invention provides a kind of power device and the integrated technique of control device, comprise the following steps：
Offer is provided with the power chip of power device and is provided with the control chip of control circuit；
In preparing deielectric-coating on the front of power chip and on the front of control chip, and radiating is prepared in deielectric-coating
Structure；
Power chip is vertically bonded to using front bonding technology after forming a bonding chip on control chip, to power
The back side of chip carries out reduction process；
Etching bonding chip forms some silicon holes, and fills metal in some silicon holes, to be formed power device
The interconnection line electrically connected with control circuit, and power device, control circuit are electrically connected with bonding chip external structure respectively
Metal lead wire.
Specifically, as Figure 1-10 shows, the present embodiment is related to the integrated technique of a kind of power device and control device, the work
Skill can be applied to for some power chips and control chip to realize interconnection or by a power chip and some control chips
Realize interconnection.Specifically, the technique comprises the following steps：
Step S1, there is provided the power chip for being provided with power device and the control chip for being provided with control circuit, the power
Device includes source region electrode 201 and gate electrode 202, and control circuit includes the first coordination electrode 51 and the second coordination electrode 52；
In an embodiment of the present invention, the power device is vertical-type power MOSFET element, and the power chip and control chip set
Meter and making are separate such that it is able to ensure power device and the control respective performance of circuit and cost advantage.
Further, the structure of the power chip as shown in Figure 1a, specifically includes substrate 12, covers the upper surface of substrate 12
Epitaxial layer 13, the p-well region 16 of covering epitaxial layer 13 upper surface, it is arranged in p-well region 16 and extends to epitaxial layer 13
(grid structure includes the ditch of covering groove bottom and its side wall for gate trench, the grid structure being arranged in the gate trench
The trench polysilicon Si-gate 151 of groove gate oxidation films 141 and the bottom of covering groove gate oxidation films 141 and its side wall), be arranged at adjacent gate
The N source regions 17 in p-well region 16 between the structure of pole, the p-well contact zone 18 between N source regions 17, it is arranged at trench polysilicon
The top of Si-gate 151 and gate electrode 202, the setting realizing electrically connecting by polysilicon line 152 with the trench polysilicon Si-gate 151
The oxide-film 142 for being isolated polysilicon line 152 and p-well region 16 between polysilicon line 152 and p-well region 16 with
And it is arranged at the top of trench polysilicon Si-gate 151 and the source region electrode 201 isolated with trench polysilicon Si-gate 151 by dielectric layer 19,
And isolate also through dielectric layer 19 between gate electrode 202 and source region electrode 201.
Preferably, the thickness of power device bears at least thick 0.2 μm (such as 0.2 μ of thickness of the epitaxial layer of voltage than device
M, 0.3 μm, 0.5 μm or 1 μm etc.).
The structure of control chip as shown in Figure 1 b, specifically includes silicon substrate 2, the control circuit on silicon substrate 2 and is situated between
Plasma membrane 6, the active and passive device 3 being arranged in control circuit media film 6, the control being arranged in control circuit media film 6
Electric circuit metal layer 4 and it is arranged at some coordination electrodes in control circuit media film 6 and on control electric circuit metal layer 4
And metal connecting line, wherein some coordination electrodes include the first coordination electrode 51 and the second coordination electrode 52 and other coordination electrodes
5。
Step S2, in deielectric-coating is prepared on the front of power chip and on the front of control chip, and in deielectric-coating
Radiator structure is prepared, following steps are specifically included：
Step one, in deposition first medium film 311 on the front of power chip, after forming the structure as shown in Fig. 2 a (1),
Technique is patterned to first medium film 311 and forms some first grooves, the structure as shown in Fig. 2 a (2) is continued at some
Heat Conduction Material is deposited in first groove and carries out after flatening process removes unnecessary Heat Conduction Material, forming the first radiator structure
411, the structure as shown in Fig. 2 a (3).
Step 2, after second medium film 312 is formed on the front of control chip, forms the structure as shown in Fig. 2 b (1)
Afterwards, technique is patterned to second medium film 312 and forms some second grooves, the structure as shown in Fig. 2 b (2), if continuing at
Heat Conduction Material is deposited in dry second groove and carry out after flatening process removes unnecessary Heat Conduction Material, forming the second radiating knot
Structure 412, the structure as shown in Fig. 2 b (3).
Preferably, the Heat Conduction Material in step 1 and step 2 is the stronger materials of the capacity of heat transmission such as silver, copper or aluminium.
In an embodiment of the present invention, the position of the first radiator structure 411 and the second radiator structure 412 can correspond to and set
Put, so that in follow-up bonding, the first radiator structure 411 and the second radiator structure 412 are mutually aligned and to form radiator structure, and on
The order for stating step one and step 2 can be exchanged according to process requirements, and this has no effect on the purpose of the present invention.
Additionally, in the present embodiment, first medium film 311 is identical with the material of second medium film 312, the present invention other
Embodiment in, first medium film 311 and second medium film 312 can also use different materials, as long as the present invention can be realized
Purpose.
, vertically be bonded to power chip using front bonding technology a bonding chip formed on control chip by step S3,
Will power chip be bonded face-to-face with control chip together with (bonding)；Specifically, then use front bonding technology will
By the first medium film 311 and second medium film 312, vertical being bonded together to be formed power chip face-to-face with control chip
Bonding chip, in an embodiment of the present invention, after bonding, the first radiator structure 411 in first medium film 311 and is located at
The alignment of the second radiator structure 412 in second medium film 312 forms radiator structure 41, to reach preferable radiating effect, and then
Improve the stability of device；Simultaneously because first medium film 311 is identical with the material of second medium film 312 in the present embodiment,
After bonding, first medium film 311 and second medium film 312 form bonding medium film 31, structure as shown in Figure 3.
Step S4, by the use of the silicon chip (i.e. silicon substrate 2) of control chip as support, is carried out thinning to the back side of power chip
Technique, substrate 12 is thinned to the most minimal thickness of power device needs, so as to the performance for further increasing device (is reduced and led
Be powered resistance, improves radiating effect), and thinning and its technique afterwards production yields is improve, form knot as shown in Figure 4
Structure.
Step S5, one layer of the 3rd deielectric-coating is deposited in the back side (i.e. the upper surface of substrate 12) of power chip, in bonding core
The interconnection area and lead areas of piece are patterned technique (photoetching and etching) to the 3rd deielectric-coating, to be formed substrate 12
Part surface give exposed 3rd deielectric-coating 32, forming the 3rd deielectric-coating 32 can use well known to those skilled in the art
Technology, just it will not go into details herein, structure as shown in Figure 5.
Step S6, if being that mask etching power chip stops to the upper surface of dielectric layer 19 to be formed with the 3rd deielectric-coating 32
Hondo groove (is not entirely shown) in figure, in an embodiment of the present invention, for clearer elaboration technical scheme, only
Follow-up elaboration is carried out by taking part of trench (first groove, second groove and the 3rd groove) as an example；In first groove side wall,
Two trenched side-walls and the 3rd trench sidewall surface are respectively formed buffer layer, after follow-up filling metal, to realize metal and silicon
Isolation, while can also further control to be subsequently formed the CD of silicon hole by the buffer layer.In implementation of the invention
In example, during etching forms first groove, oxide-film 142 is partly or entirely etched away, structure as shown in Figure 6.
Step S7, continues to form (the i.e. first control of the first silicon hole 351 in etching first groove to the first coordination electrode 51
Electrode 51 is partially etched), the second silicon hole 352 (i.e. source region electrode is formed in etching second trenches to the source region electrode 201
201 are partially etched), form (i.e. the second coordination electrode of the 3rd silicon hole 352 in etching the 3rd groove to the second coordination electrode 52
52 are partially etched), and the first silicon hole 351 is by the part surface of gate electrode 202 and the part table of the first coordination electrode 51
Face is exposed, it is preferred that the exposed part surface of gate electrode 202 is the side wall of the gate electrode 202, and the second silicon leads to
Hole 352 is exposed the part surface of source region electrode 201, and the 3rd silicon hole 353 is by the part surface of the second coordination electrode 52
Exposed；Further, after the first silicon hole 351, the second silicon hole 352 and the 3rd silicon hole 352 is formed, by light
Carve, etching removes the second medium film 32 at the drain region back side of power device, structure as shown in Figure 7.
Step S8, metal is filled in the first silicon hole 351, the second silicon hole 352 and the 3rd silicon hole 353, and first
The interconnection line that power device is electrically connected with control circuit is formed after metal is filled in silicon hole 351, is filled out in the second silicon hole 352
The first metal lead wire that power device is electrically connected with bonding chip external structure is formed after filling metal, in the 3rd silicon hole 353
The second metal lead wire that circuit will be controlled to be electrically connected with bonding chip external structure is formed after filling metal；In other words, that is, lead to
Cross interconnection line to electrically connect the coordination electrode 51 of gate electrode 202 and first, by the first metal lead wire by source region electrode 201 and key
The electrical connection of chip exterior structure is closed, the second coordination electrode 52 and bonding chip external structure are electrically connected by the second metal lead wire
Connect.Afterwards, formed the back side of power chip (including upper surface, the upper surface of the first metal lead wire, second metal of interconnection line
The upper surface of lead, the upper surface of the 3rd deielectric-coating 32 and the exposed upper surface of substrate 12) metal level 36 that is covered；
In embodiments of the invention, it is also possible to form interconnection line, the first metal lead wire, the second metal lead wire and gold by other techniques
Category layer 36, however it is not limited to the method described in the present invention, such as after may be in filling metal in silicon hole, be pointed to power chip
The metal of back side form the metal level 36, structure as shown in Figure 8 using CMP and etching technics.
Step S9, continues the upper surface that depositing electrode metal film 37 covers the metal level 36, structure as shown in Figure 9.
Step S10, partial etching is located at electrode metal film 37 and metal level 36 on the 3rd deielectric-coating 32, to cause position
Electrode metal film 37 on interconnection line and metal level 36 form the first metal electrode 374, on the first metal lead wire
Electrode metal film 37 and metal level 36 formed the second metal electrode 372, the electrode metal film on the second metal lead wire
37 and metal level 36 formed the 3rd metal electrode 371, electrode metal film 37 and metal level 36 above grid structure are formed
It is mutually isolated between 4th metal electrode 373, and the first metal electrode 374, the second metal electrode 372, the 3rd metal electrode 371
And the 4th mutually isolated, as shown in Figure 10 structure between metal electrode 373.
Wherein, first coordination electrode 51 and power device of circuit will be controlled by the first metal electrode 374 and interconnection line
Gate electrode 202 electrically connect and draw, by the second metal electrode 372 and the second metal lead wire by the source region electricity of power device
Pole 201 is drawn, and by the 3rd metal electrode 371 and the 3rd metal lead wire the coordination electrode 52 of circuit will be controlled to draw, so that logical
Cross using silicon hole technology, realize the interconnection of two difference in functionality chips, eliminate the line between device, reduce the electricity of parasitism
Sense and electric capacity.
In sum, the present invention is bonded and through hole interconnection using the superposition of chip, reduces line, parasitic capacitance and electricity
Sense, improves the performance of device and the reliability of technical scheme, and instead of conventional encapsulation, reduces volume and area, improves
Reliability and performance, and the present invention is smaller than MCM mode areas, and shared thinning and back metal technique, further reduce
Manufacturing cost.
It should be appreciated by those skilled in the art that those skilled in the art combine prior art and above-described embodiment can be with
The change case is realized, be will not be described here.Such change case has no effect on substance of the invention, not superfluous herein
State.
Presently preferred embodiments of the present invention is described above.It is to be appreciated that the invention is not limited in above-mentioned
Particular implementation, wherein the equipment and structure that do not describe in detail to the greatest extent are construed as giving reality with the common mode in this area
Apply；Any those of ordinary skill in the art, in the case where technical solution of the present invention ambit is not departed from, all using the disclosure above
Methods and techniques content make many possible variations and modification to technical solution of the present invention, or be revised as equivalent variations etc.
Effect embodiment, this has no effect on substance of the invention.Therefore, every content without departing from technical solution of the present invention, foundation
Technical spirit of the invention still falls within the present invention to any simple modification, equivalent variation and modification made for any of the above embodiments
In the range of technical scheme protection.
Claims (10)
1. the integrated technique of a kind of power device and control device, it is characterised in that comprise the following steps：
Offer is provided with the power chip of power device and is provided with the control chip of control circuit；
In deielectric-coating is prepared on the front of the power chip and on the front of the control chip, and in the deielectric-coating
Prepare radiator structure；
The power chip is vertically bonded to using front bonding technology after forming a bonding chip on the control chip, it is right
The back side of the power chip carries out reduction process；
Etch the bonding chip and form some silicon holes, and metal is filled in some silicon holes, so that formed will be described
Power device and the control interconnection line that electrically connects of circuit, and by the power device, the control circuit respectively with institute
State the metal lead wire of bonding chip external structure electrical connection；
Wherein, the power device includes source region electrode and gate electrode, and the control circuit includes the first coordination electrode and the
Two coordination electrodes；
The technique also includes：
It is in forming the first silicon hole, the second silicon hole and the 3rd silicon hole using etching technics on the bonding chip and described
First silicon hole is exposed the part surface of the part surface of the gate electrode and the first coordination electrode, and described second
Silicon hole is exposed the part surface of the source region electrode, and the 3rd silicon hole is by the part of second coordination electrode
Surface is exposed；
The interconnection line and institute are formed after filling metal in first silicon hole, the second silicon hole and the 3rd silicon hole
Metal lead wire is stated, the metal lead wire includes the first metal lead wire and the second metal lead wire；
Wherein, the gate electrode and first coordination electrode are electrically connected by the interconnection line, by first gold medal
Category lead electrically connects the source region electrode with the bonding chip external structure, by second metal lead wire by described the
Two coordination electrodes are electrically connected with the bonding chip external structure.
2. the integrated technique of power device as claimed in claim 1 and control device, it is characterised in that in the power chip
Front on and the front of the control chip on prepare deielectric-coating, and the step of prepare radiator structure in the deielectric-coating
Including：
After first medium film is formed on the front of the power chip, technique is patterned to the first medium film and is formed
Some first grooves, and Heat Conduction Material the first radiator structure of formation is deposited in some first grooves；
After second medium film is formed on the front of the control chip, technique is patterned to the second medium film and is formed
Some second grooves, and Heat Conduction Material the second radiator structure of formation is deposited in some second grooves.
3. the integrated technique of power device as claimed in claim 2 and control device, it is characterised in that the Heat Conduction Material is
Silver, copper or aluminium.
4. the integrated technique of power device as claimed in claim 1 and control device, it is characterised in that the technique is also wrapped
Include：
Metal electrode is formed respectively in the upper surface of the interconnection line, the first metal lead wire, the second metal lead wire.
5. the integrated technique of power device as claimed in claim 4 and control device, it is characterised in that the technique is also wrapped
Include：
After forming the interconnection line, the first metal lead wire, the second metal lead wire, deposited metal layer is with by the back of the body of the power chip
Face is covered；
Continue depositing electrode metal film to be covered with by the upper surface of the metal level；
Partial etching is located at the electrode metal film and metal level above the interconnection line and the metal lead wire, with described
Interconnection line top formed the first metal electrode, form above first metal lead wire the second metal electrode, described second
Metal lead wire top forms the 3rd metal electrode.
6. the integrated technique of power device as claimed in claim 1 and control device, it is characterised in that the power device is
Vertical-type power MOSFET element.
7. the integrated technique of power device as claimed in claim 6 and control device, it is characterised in that the power chip bag
Include：
Substrate；
Positioned at the epitaxial layer of the substrate top surface；
Positioned at the p-well substrate of the epitaxial layer upper surface；
It is arranged in the p-well substrate and extends to the gate trench in the epitaxial layer；
Grid structure in the gate trench, the grid structure includes groove gate oxidation films and the covering trench gate
Oxide-film bottom and its trench polysilicon Si-gate of side wall；
It is arranged at the grid structure top and the gate electrode electrically connected with the trench polysilicon Si-gate；And
It is arranged at the grid structure top and the source region electrode isolated with the grid structure by dielectric layer.
8. the integrated technique of power device as claimed in claim 7 and control device, it is characterised in that the technique is also wrapped
Include：
After carrying out reduction process to the back side of the power chip, in one layer of the 3rd medium of backside deposition of the power chip
Film, technique is patterned to the 3rd deielectric-coating, and the part surface of the power chip is exposed；
Power chip described in the 3rd deielectric-coating as mask etching, to form some silicon holes.
9. the integrated technique of power device as claimed in claim 8 and control device, it is characterised in that the technique is also wrapped
Include：
Power chip described in the 3rd deielectric-coating as mask etching stops forming some grooves to the dielectric layer surface；
Buffer layer is respectively formed in the sidewall surfaces of some grooves；
Continue etching some grooves and form some silicon holes.
10. the integrated technique of power device as claimed in claim 1 and control device, it is characterised in that the technique application
Realize interconnecting in by some power chips and a control chip realization interconnection or by a power chip and some control chips.
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| DE102022210833A1 (en) | 2022-10-14 | 2024-04-25 | Robert Bosch Gesellschaft mit beschränkter Haftung | Vertical semiconductor device based on gallium nitride with integrated control in carrier material |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102024782A (en) * | 2010-10-12 | 2011-04-20 | 北京大学 | Three-dimensional vertical interconnecting structure and manufacturing method thereof |
| EP2575174A2 (en) * | 2011-09-30 | 2013-04-03 | Sony Corporation | Semiconductor device and semiconductor-device manufacturing method |
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