CN105630713A - Method for realizing storage of logic waveform data - Google Patents

Abstract

The invention belongs to the technical field of sampling and measuring of electronic signals. A method for realizing storage of logic waveform data disclosed by the invention comprises a counting process, a triggering control process and a FIFO write-in control process, wherein the counting process comprises the following steps: (1), judging whether a reset signal is valid or not, continuously judging if the reset signal is valid, and performing the next step if the reset signal is invalid; (2), judging whether preset number enabling is valid or not, returning to the step (1) if the preset number enabling is valid, and performing the next step if the preset number enabling is invalid; (3), judging whether a counting enabling signal is valid or not, returning to the step (1) if the counting enabling signal is invalid, and performing the next step if the counting enabling signal is valid; (4), adding 1 to a count value; and (5), storing deep judgement, and setting a counter mould. By means of designs, such as selection of a storage, a counter, a FIFO control circuit, an SRAM control circuit, data output selection, reading and writing of a register and address decoding, storage of logic waveform data is realized.

Description

The method realizing the storage of logical waveform data

Technical field

The invention belongs to electronic signal sampled measurements technical field, particularly relate to a kind of method for designing realizing the storage of logical waveform data.

Background technology

Along with the development of electronic technology, the design of digital display circuit direction just high towards complexity, that operating rate is fast is developed, and test instrunment is had higher requirement. The traditional method of testing grown up by the time and frequency domain analysis of analog systems and test instrunment are often difficult to prove effective, it is necessary to develop the data-domain test instrument being exclusively used in digital display circuit. Logic analyser is as the universal tester being most widely used in data-domain test instrument, logic analyser is a kind of instrument analyzing digitizer hardware and software, there is the function of data capture, storage, process, it it is one of most important data-domain test instrument, its storage depth determine obtain data number, storage depth is more deep, it was shown that under same analysis frequency it is observed that time range more big.

Summary of the invention

The technique effect of the present invention can overcome drawbacks described above, it is provided that a kind of method realizing the storage of logical waveform data, and it realizes the storage of logical waveform data.

For achieving the above object, the present invention adopts the following technical scheme that it comprises the steps: that counting flow process, triggering control flow, FIFO write control flow,

Wherein, counting flow process comprises the steps:

(1) judge that whether reset signal is effective, effectively, continue to judge; Invalid, carry out next step;

(2) judge that whether preset number enables effective, effectively, returns step (1); Invalid, carry out next step;

(3) whether effective judge that counting enables signal, invalid return step (1); Effectively, next step is carried out;

(4) count value adds 1;

(5) storage depth judges, sets enumerator mould;

(6) judge whether enumerator is counted full, no, return step (1); It is carry out next step;

(7) count value resets, counter overflow, and returns step (1);

Wherein, trigger control flow to comprise the steps:

(1) initial value of write pre-trigger enumerator, delay counter, triggers to enable and closes;

(2) pre-trigger enumerator, address produce rolling counters forward, and storage controls to enable;

(3) judge that whether PCNF is equal to 1, no, continue; It is carry out next step;

(4) open triggering to enable, wait trigger flag TF;

(5) judge that whether TF is equal to 1, no, continue; It is carry out next step;

(6) delay counter counting;

(7) judge that whether DCNF is equal to 1, no, continue; It is carry out next step;

(8) stop data storage, terminate;

Wherein, FIFO write control flow comprises the steps:

(1) initialize;

(2) judge whether to write enable equal to 1, no, continue; It is carry out next step;

(3) judge that whether pre-trigger mark is equal to 1, be carry out next step; No, it is judged that whether FIFO full, FIFO less than, write FIFO; FIFO is full, terminates;

(4) judge that whether trigger flag is equal to 1, no, synchronize to read FIFO; It is read enable invalid.

This method is designed with address decoding etc. by the selection of memorizer, Counter Design, fifo control circuit, SRAM control circuit, data output selection, depositor read-write, it is achieved logical waveform data store.

Accompanying drawing explanation

Fig. 1 is enumerator flow chart;

Fig. 2 is enumerator analogous diagram;

Fig. 3 is trigger word address latch circuit;

Fig. 4 is for triggering control flow chart;

Fig. 5 is fifo circuit connection figure;

Fig. 6 is that FIFO writes control flow chart;

Fig. 7 is bus selector;

Fig. 8 is depositor read/write circuit;

Fig. 9 is the address decoding circuitry of the present invention.

Detailed description of the invention

The method realizing the storage of logical waveform data of the present invention, comprises the steps: that counting flow process, triggering control flow, FIFO write control flow,

Wherein, counting flow process comprises the steps:

(1) judge that whether reset signal is effective, effectively, continue to judge; Invalid, carry out next step;

(2) judge that whether preset number enables effective, effectively, returns step (1); Invalid, carry out next step;

(3) whether effective judge that counting enables signal, invalid return step (1); Effectively, next step is carried out;

(4) count value adds 1;

(5) storage depth judges, sets enumerator mould;

(6) judge whether enumerator is counted full, no, return step (1); It is carry out next step;

(7) count value resets, counter overflow, and returns step (1);

Wherein, trigger control flow to comprise the steps:

(1) initial value of write pre-trigger enumerator, delay counter, triggers to enable and closes;

(2) pre-trigger enumerator, address produce rolling counters forward, and storage controls to enable;

(3) judge that whether PCNF is equal to 1, no, continue; It is carry out next step;

(4) open triggering to enable, wait trigger flag TF;

(5) judge that whether TF is equal to 1, no, continue; It is carry out next step;

(6) delay counter counting;

(7) judge that whether DCNF is equal to 1, no, continue; It is carry out next step;

(8) stop data storage, terminate;

Wherein, FIFO write control flow comprises the steps:

(1) initialize;

(2) judge whether to write enable equal to 1, no, continue; It is carry out next step;

(3) judge that whether pre-trigger mark is equal to 1, be carry out next step; No, it is judged that whether FIFO full, FIFO less than, write FIFO; FIFO is full, terminates;

(4) judge that whether trigger flag is equal to 1, no, synchronize to read FIFO; It is read enable invalid.

1, memorizer selects

This method has been sampled two kinds of memorizeies, a kind of is realize 8 FIFO inside FPGA to store data during 500MHz sampling, additionally have selected the sram chip IS61LV25616AL-10 of 4 ISSI companies to store the data of other sample rate, the memory capacity of this chip is 256K �� 16, accesses time 10ns. The reason not adopting external SRAM storage 500MHz sampled data is: 1, and needs are further added by 4 SRAM by sampling external memory storage, strengthening while hardware cost, too increase the needs to the common I/O mouth of FPGA, cause pin resource nervous. 2, adopt internal storage, it is possible to achieve " high-speed sampling " function, namely when below 500MHz timing sampling, the data of the 400MHz sampling of the 16K degree of depth near trigger point can be preserved simultaneously in internal storage, provide the user with a careful watch window. The following is the maximum storage degree of depth under each sample rate.

The storage depth of timing analysis:

1,500MHz sampling depth capacity 16K stores with 8 FIFO

2,200MHz/100MHz sampling depth capacity 1M store with 4 SRAM

4,50MHz and following depth capacity 256K store with 1 SRAM

The storage depth of state analysis:

All sample rate depth capacity 256K store with 1 SRAM

When timing analysis 50MHz and following sample rate, when burr sampling functions selects, preserve burr data with a SRAM.

2, Counter Design

Counter circuit completes initial, the termination counting that the address of SRAM produces and triggers, and it includes two SRAM addresses and produces enumerator, a pre-trigger enumerator and a delay counter, and these four counter structures are identical. Timer VHDL writes, the function such as have clearing, enable, preset number, mould able to programme, system is always set to the mould of enumerator the storage depth of data, also the mould of enumerator is just have selected when user selects storage depth time, after counter counts is full, output overflow indicator, starts the cycle over counting from 0 again simultaneously. Enumerator VHDL writes, and flow chart is as shown in Figure 1

It will be seen that enumerator starts counting up from 0 or preset number from flow chart, after meter is full (namely meter arrives storage depth-1), produces spill over, start meter from 0 again, constantly repeat, until enabling signal is 0. Fig. 2 is the wave simulation figure of enumerator.

Trigger and control to be realized by pre-trigger enumerator and delay counter. Application program is according to the time delay ratio of user setup and storage depth, calculate initial value the preset number of pre-trigger enumerator and time-delay trigger, wherein the computing formula of pre-trigger enumerator initial value is: postpone number % �� storage depth, its count maximum is storage depth, delay counter initial value computing formula is: storage depth-delay number % �� storage depth, and its counting maximum count value is storage depth.

After system starts to adopt number, pre-trigger enumerator starts counting up, simultaneously data write SRAM under system clock drives, and at this moment triggers identification circuit and does not enable. When the spilling of pre-trigger enumerator, data volume=storage depth-delay number % �� the storage depth having been written in SRAM is described, now enable and trigger identification circuit, wait trigger flag produces, data constantly write SRAM simultaneously, when the number of the data in SRAM is equal to after storage depth, will start to write from 0 address of SRAM again, newly written data will cover the data that first write, and allowing what preserve in SRAM is up-to-date data all the time.

When trigger flag produces just to enable delay counter, the output valve of current address enumerator is latched in buffer simultaneously, is used for recording trigger word physical address in memory. Thus can determine in SRAM, which address is to store significant figure according to this physical address and pre-trigger and storage depth. Address latch circuit is as shown in Figure 3. Trigf is trigger flag signal, and cn_/clrn triggers reset signal, and ACH_AD [17..0] is the output that address produces enumerator, and trig_site is the trigger word recorded address in sram.

After time delay counting overflows, stop writing number in SRAM, adopt number and terminate. Trigger control flow as shown in Figure 4.

SRAM address produces enumerator and pre-trigger enumerator starts simultaneously at work, and when triggering generation, trigger flag is latched into the output valve of current address enumerator in buffer, is used for recording trigger word physical address in memory. Thus can determine in SRAM, which address is to store valid data according to this physical address and pre-trigger and storage depth.

3, fifo control circuit

FIFO directly realizes with the IP kernel of altera corp, is the doubleclocking FIFO with asynchronous resetting. The control of 8 FIFO is similar, and Fig. 5 is the circuit connection diagram of one of them FIFO, and other FIFO is similar.

The clock (not past frequency dividing) of serioparallel exchange output is as the clock of writing of FIFO, and write enable signal and system acquisition enable signal and connect, and one in 8 parallel-by-bit outputs of 16 respectively with 16 passages of bit data port adjacent. The same with SRAM, FIFO is also required to the setting according to user, preserves a certain amount of data before and after trigger point. Owing to FIFO does not have address wire, control method and SRAM different yet, so can not go to control FIFO by the method controlling SRAM above said. The scheme that we adopt is: adopts and starts toward write data in FIFO after number enables, when the data volume in write FIFO is the same with the data volume of pre-trigger, and trigger flag is not when producing, often one data of write, just abandon previously written data, to keep the data volume in FIFO the same with pre-trigger value, when trigger flag produces, then it is normally written FIFO, no longer abandons the data first write, until FIFO writes full, terminate to adopt several process.

We adopt to change and read clock and read ruing well of enable to realize this scheme, when pre-trigger counter overflow is masked as 0, it is normally written FIFO, now reads to enable and read clock all by read through model control, when pre-trigger counter overflow is masked as 1, and trigger flag is when being 0, it is assigned to reading clock writing clock, reads to enable effectively, at this moment simultaneously, often write data toward FIFO, also read data. Maintain data volume in FIFO constant, and the data always finally adopted that FIFO preserves. After trigger flag is effective, reads clock and reading enables and switches to again by read through model control. This circuit module VHDL is write as, its flow chart as shown in Figure 6:

The reading of FIFO is fairly simple, USB controller directly control, and software produces to read clock. First set reading and enable effectively, after reading rising edge clock, judge whether empty mark is 1, be not that 1 output port data is effective, be that 1 output port data is invalid, continue to reading clock. 8 FIFO share and read clock, so controlling to read to enable with a 3-8 decoder.

4, SRAM control circuit

SRAM adopts IS61LV25616AL-10, and its main pin is in Table 1.

In the design, chip selection signal/CE, high byte control/UB, low byte control/LB ground connection, keep chip select and high low byte Chang Youxiao, output enables/OE when write be the address of 1, SRAM by counter controls said before, count output and link in address wire. Write enable signal/WE is by system clock control. Also being system clock owing to producing the drive clock of the enumerator of address, so the address change of SRAM and system clock synchronize, rising edge address adds 1, the low level write data of system clock. Each data in order to ensure write SRAM are valid data, it is necessary to the trailing edge at system clock enables data storage, it is ensured that after writing the first number, address just adds 1, it is to avoid address is the situation of just first data of write after adding 1. The reading of SRAM is by USB controller control, and now the drive clock of address counter switches to the clock that microcontroller software produces.

Table 1

A0�CA17	Address inputs
		I/O0�CI/O15	Bidirectional data port
/CE	Chip select
		/OE	Output enables
/WE	Write enable
		/LB	Low byte controls

/UB	High byte controls
		VDD	Power supply
GND	Ground

5, data output selects

4 SRAM and 8 FIFO pass to USB chip by the FPDP of same 16, then are passed to display in PC by USB chip. So the output of a memorizer and FPDP can only be had to connect in some moment, this method have employed bus selector to carry out the switching of data/address bus, as shown in Figure 7.

6, depositor read-write and address decoding

In the design, having a lot of depositor to need USB controller to configure inside FPGA, USB controller is also required to read the state of some depositors inside FPGA and carries out the control being correlated with. Register write latch cicuit is formed by 74374, reads data buffering and is formed by 74244. Fig. 8 is one and writes latch and a circuit reading buffering.

In figure, D0��D7 is the external data bus of USB control chip. AR7 and AW5 is equivalent to read/write address. 74374 rising edge clocks are latched into outfan data, and 74244 is the triple gate of 2 group of 4 passage in fact, when Enable Pin is 0, data is exported.

Each read-write register and reading buffering have address, the address bus of USB decode and obtain. Decoding circuit is made up of multiple 74154 and gate circuit, always has 132 and write latch register and 11 reading bufferings in the design. Fig. 9 is the decoding of part read/write address.

In figure, A0-A7 is the least-significant byte address of the address bus of USB control chip, by figure it can be seen that address corresponding to AA0-AA15 is 0x00-0x0F. / WR and/RD is the reading write enable signal of USB control chip respectively. The address after decoding respectively and/WR ,/RD phase or obtain read/write address. The rising edge of utilization/WR signal latches valid data, and the low level of utilization/RD reads data.

Claims (1)

1. the method realizing the storage of logical waveform data, it is characterised in that comprise the steps: that counting flow process, triggering control flow, FIFO write control flow,

Wherein, counting flow process comprises the steps:

(1) judge that whether reset signal is effective, effectively, continue to judge; Invalid, carry out next step;

(2) judge that whether preset number enables effective, effectively, returns step (1); Invalid, carry out next step;

(3) whether effective judge that counting enables signal, invalid return step (1); Effectively, next step is carried out;

(4) count value adds 1;

(5) storage depth judges, sets enumerator mould;

(6) judge whether enumerator is counted full, no, return step (1); It is carry out next step;

(7) count value resets, counter overflow, and returns step (1);

Wherein, trigger control flow to comprise the steps:

(1) initial value of write pre-trigger enumerator, delay counter, triggers to enable and closes;

(2) pre-trigger enumerator, address produce rolling counters forward, and storage controls to enable;

(3) judge that whether PCNF is equal to 1, no, continue; It is carry out next step;

(4) open triggering to enable, wait trigger flag TF;

(5) judge that whether TF is equal to 1, no, continue; It is carry out next step;

(6) delay counter counting;

(7) judge that whether DCNF is equal to 1, no, continue; It is carry out next step;

(8) stop data storage, terminate;

Wherein, FIFO write control flow comprises the steps:

(1) initialize;

(2) judge whether to write enable equal to 1, no, continue; It is carry out next step;

(3) judge that whether pre-trigger mark is equal to 1, be carry out next step; No, it is judged that whether FIFO full, FIFO less than, write FIFO; FIFO is full, terminates;

(4) judge that whether trigger flag is equal to 1, no, synchronize to read FIFO; It is read enable invalid.