CN105610429A - Configurable logic element based on NAND OR structure - Google Patents
Configurable logic element based on NAND OR structure Download PDFInfo
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- CN105610429A CN105610429A CN201510991996.1A CN201510991996A CN105610429A CN 105610429 A CN105610429 A CN 105610429A CN 201510991996 A CN201510991996 A CN 201510991996A CN 105610429 A CN105610429 A CN 105610429A
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- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
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Abstract
The invention discloses a configurable logic element based on an NAND OR structure. The unit comprises an NAND OR basic element; the NAND OR basic element realizes NAND or NOR function of first input data and second input data under the control of the output control signals of an SRAM storage element; the NAND OR basic element comprises a pull-up network pFET logic circuit module and a pull-down network nFET logic circuit module; the pull-up network pFET logic circuit module comprises at least one first to at least one fifth pFET transistors; and the pull-down network nFET logic circuit module comprises at least one first to at least one fifth nFET transistors. According to the configurable logic element disclosed by the invention, the configurable NAND OR is taken as the basic logic cone element; the number of the demanded transistors is less than that of an And-Inverter Cone structure; the area is smaller; the circuit series to be passed by the signals are few; the speed is good; the delay difference is little; and the delay for realizing different functions is approximately the same through adjusting the parameters of the transistors.
Description
Technical field
The invention belongs to computer programmable logic technology field, relate in particular to a kind of based on AOI (NANDOR) structureProgrammable logic cells.
Background technology
PLD is developed so far, and has become the requisite medium of realizing of digital circuit. Programming device spiritThe programmability of living makes it configurablely realize different logic functions, meets the functional requirement of different user. Along with workerThe progress of skill, the performance of PLD constantly promotes. In addition, PLD also has shorter product developmentTime. Above-mentioned advantage makes PLD be widely used in different application field.
PLD mainly by programmed logical module (ConfigurableLogicBlock, CLB) with canProgramming interconnecting modules composition. CLB realizes the sub-logic function in application circuit, and programmable interconnect module connects each sub-logicConnect to form complete application circuit logic function.
The programmable logic cells (LogicElement, LE) of the fpga chip of main flow is tied by look-up table conventionally at presentStructure is realized, and is illustrated in figure 1 a kind of implementation of programmable logic cells 100 of typical 4 input look-up table configuration. Can compileJourney logical block LUT4 is made up of 110 and 16 SRAM memory cell 121 of 1 MUX MUX16S1 (16 select 1), whereinMUX MUX16S1110 is made up of 5 MUX4S1 (4 select 1) 120. Input access signal, as memory cell SRAM121 while being configured to different value, can realize different programmable functions. The programmable logic cells of this structure has powerfulProgrammability, but the flexibility of its height has also brought the performance cost such as corresponding area, time delay. Simultaneously due to this canProgrammed logic cellular construction only has an output, in the time there is redundancy in the programmable functions of look-up table, and cannot be multiplexing configurableResource.
Therefore, the people such as the HadiParandeh of the federal Polytechnics of Lausanne, SUI first proposed a kind of based on non-coneThe fpga logic unit (US Patent No. 8,836,368B2) of (And-InverterCone, AIC) structure. As shown in Figure 2,Taking the AIC logic cone AIC3200 of 3 grades as example, AIC3 is by 4 bottom AIC unit (BottomAICElement, EAE)210 and 3 basic AIC unit (BasicAICElement, BAE), 220 compositions. Wherein, basic AIC unit 220 is by one two222, one of input nand gates 221, phase inverter two input selectors 223, a SRAM dispensing unit 224 form; BottomIn fact AIC unit 210 has comprised a basic AIC unit 220, and remainder circuit is by two two input selectors 211, twoEach and every one phase inverter 212, two SRAM dispensing units 213 form. An AIC3200 has 8 input i0～i7, when storage listWhen the SRAM of unit is configured as different value, AIC3 can realize different logic functions. In example, AIC3 is from least one second layerStart output, the operation result of at least one the first level is not exported. Because any function can both change by logical operationWrite the combined expression becoming with non-unit. Thereby can be by Function Mapping arbitrarily on AIC combining structure. This logical blockThere are the features how output is inputted more, can meet on the one hand the calculation function of the wide input of multidigit, easily land productivity of whileEffectively utilize programmable resource with middle Output rusults.
Wherein the way of realization of basic AIC unit B AE220 is conventionally as shown in Fig. 3 300, corresponding two input nand gates221, the circuit way of realization of 222, one of phase inverters, two input selectors 223, a SRAM dispensing unit 224 as 310,320, shown in 330,340. Whole AIC unit B AE220 needs 12 transistors to realize.
This when being configured as nonidentity operation function with the programmable logic cells of non-wimble structure, basic AIC unitTo there is different Path selection, whether pass through phase inverter. By phase inverter, basic AIC has realized unit NAND gateFunction; Select by phase inverter path, basic AIC has realized unit the function with door. On time delay path, two kinds are disposedDifferent delay performances, this temporal constraint of realizing the later stage to application circuit has brought inconvenience.
Summary of the invention
In view of this, the present invention proposes a kind of programmable logic cells based on AOI wimble structure, adopt and can compileJourney AND OR NOT gate (NANDOR) is as basic logic cone unit.
The programmable logic cells based on AOI structure that the present invention proposes, it comprises AOI elementary cell, described inAOI elementary cell realizes the first input data and the second input under the control of the output control signal of SRAM memory cellThe function of data NAND or nondisjunction, by multistage interconnected, can realize any logic function and express formula;
Wherein, described AOI elementary cell comprises: upper pull-up network pFET application of logic circuit module and pulldown network nFET patrolCollect circuit module; Described upper pull-up network pFET application of logic circuit module comprise at least one pFET pipe at least one the 5thPFET pipe;
The source electrode of described at least one pFET pipe and at least one the 4th pFET pipe connects power supply, described at least one theThe drain electrode of one pFET pipe connects the source electrode of at least one the 2nd pFET pipe, described in the drain electrode of described at least one the 4th pFET pipe connects extremelyThe source electrode of few a 5th pFET pipe, the drain electrode of described at least one the 2nd pFET connects the source of described at least one the 3rd pFET pipeThe utmost point, the drain electrode of described at least one the 3rd pFET pipe and described at least one the 5th pFET pipe connects holding wire y end; Wherein, described inThe drain electrode interconnection of at least one the 4th pFET pipe drain electrode and described at least one pFET pipe or described at least one the 4thThe drain electrode interconnection of the drain electrode of pFET pipe and at least one the 2nd pFET pipe, to divide described upper pull-up network pFET application of logic circuit moduleBecome two parts of series connection up and down; Described in described at least one pFET pipe connects respectively to the grid of at least one the 3rd pFET pipeIn the output control signal of first input data and SRAM memory cell one, described at least one the 4th pFET pipe is at leastThe grid of a 5th pFET pipe meets in the output control signal of described second input data and SRAM memory cell.
Than of the prior art and non-wimble structure, in circuit of the present invention, the required circuit progression passing through of signal is few,Area can be accomplished less, can be faster by regulating the speed of pipe parameter, and simultaneously in the time realizing difference in functionality, its delay differenceLess, and time delay that can be when adjusting pipe parameter and make to realize difference in functionality is identical.
Brief description of the drawings
Fig. 1 is the programmable logic unit structure schematic diagram of a kind of typical 4 input look-up table configuration in prior art;
Fig. 2 be in prior art a kind of based on the fpga logic list of non-cone (And-InverterCone, AIC) structureMeta structure schematic diagram;
Fig. 3 be in prior art based on non-cone (And-InverterCone, AIC) structure in the reality of basic AIC unitExisting structure chart;
Fig. 4 be in the present invention in the first embodiment AOI unit (NANDOR) by the electricity of COMS standard compound logic doorFigure is realized on road;
Fig. 5 be in the present invention in the second embodiment AOI unit (NANDOR) by the electricity of COMS standard compound logic doorFigure is realized on road;
Fig. 6 be in the present invention in the 3rd embodiment AOI unit (NANDOR) by the electricity of COMS standard compound logic doorFigure is realized on road;
Fig. 7 be in the present invention in the 4th embodiment AOI unit (NANDOR) by the electricity of COMS standard compound logic doorFigure is realized on road;
Fig. 8 be in the present invention in the 5th embodiment AOI unit (NANDOR) by the electricity of COMS standard compound logic doorFigure is realized on road;
Fig. 9 be in the present invention in the 6th embodiment AOI unit (NANDOR) by the electricity of COMS standard compound logic doorFigure is realized on road.
Detailed description of the invention
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and referenceAccompanying drawing, the present invention is described in further detail.
The present invention proposes a kind of programmable logic cells based on AOI (NANDOR) structure, shown in alternate figures 3300 AIC basic unit module BAE. The basic functional principle of BAE is that it can depositing by programming Control sram cellStored Value, realizes the logic function of NAND or "AND", by the multistage connection of framework as shown in Figure 2, can realize complexityLogic function. And according to Demogan theorem, any function can both be rewritten the combination table becoming with non-unit by logical operationReach formula, therefore can pass through AIC structure practical function.
The AOI able to programme unit (NANDOR) that the present invention proposes, can pass through to control SRAM memory cell equally, canSo that this unit module functional configuration is become to NAND or nondisjunction function, can realize equally any patrolling by multistage interconnectedCollect functional representation.
The AOI unit (NANDOR) that the present invention proposes is realized by COMS standard compound logic door, whole AOI listUnit's (NANDOR) module comprises two parts: upper pull-up network pFET application of logic circuit module and pulldown network nFET logic circuit mouldPiece.
A kind of programmable logic cells based on AOI structure has been proposed in first embodiment of the invention, it comprise with orNon-elementary cell, described AOI elementary cell realizes the first input under the control of the output control signal of SRAM memory cellThe function of data and the second input data NAND or nondisjunction, by multistage interconnected, can realize any logic function and expressFormula;
Wherein, described AOI elementary cell comprises: upper pull-up network pFET application of logic circuit module and pulldown network nFET patrolCollect circuit module; Described upper pull-up network pFET application of logic circuit module comprise at least one pFET pipe at least one the 5thPFET pipe;
The source electrode of described at least one pFET pipe and at least one the 4th pFET pipe connects power supply, described at least one theThe drain electrode of one pFET pipe connects the source electrode of at least one the 2nd pFET pipe, described in the drain electrode of described at least one the 4th pFET pipe connects extremelyThe source electrode of few a 5th pFET pipe, the drain electrode of described at least one the 2nd pFET connects the source of described at least one the 3rd pFET pipeThe utmost point, the drain electrode of described at least one the 3rd pFET pipe and described at least one the 5th pFET pipe connects holding wire y end; Wherein, described inThe drain electrode interconnection of at least one the 4th pFET pipe drain electrode and described at least one pFET pipe or described at least one the 4thThe drain electrode interconnection of the drain electrode of pFET pipe and at least one the 2nd pFET pipe, to divide described upper pull-up network pFET application of logic circuit moduleBecome two parts of series connection up and down; Described in described at least one pFET pipe connects respectively to the grid of at least one the 3rd pFET pipeIn the output control signal of first input data and SRAM memory cell one, described at least one the 4th pFET pipe is at leastThe grid of a 5th pFET pipe meets in the output control signal of described second input data and SRAM memory cell.
Described pulldown network nFET application of logic circuit module comprises that at least one nFET pipe is at least one the 5th nFETPipe;
The drain electrode of described at least one nFET pipe and at least one the 4th nFET pipe connects holding wire y end, at least describedThe source electrode of an one nFET pipe connects the drain electrode of at least one the 2nd nFET pipe, and the source electrode of described at least one the 4th nFET pipe connectsThe drain electrode of described at least one the 5th nFET pipe, the source electrode of described at least one the 2nd nFET meets described at least one the 3rd nFETThe drain electrode of pipe, the source ground of described at least one the 3rd nFET pipe and described at least one the 5th nFET pipe; Wherein, extremely describedFew a 4th nFET pipe source electrode interconnect with the source electrode of described at least one nFET pipe or described at least one the 4thThe source electrode interconnection of the source electrode of nFET pipe and at least one the 2nd nFET pipe, to divide described pulldown network nFET application of logic circuit moduleBecome two parts of series connection up and down; Described in described at least one nFET pipe connects respectively to the grid of at least one the 3rd nFET pipeIn the output control signal of first input data and SRAM memory cell one, described at least one the 4th nFET pipe is at leastThe grid of a 5th nFET pipe meets in the output control signal of described second input data and SRAM memory cell.
Circuit structure shown in Fig. 4-Fig. 6 is patrolling based on the able to programme of AOI structure of first embodiment of the invention propositionCollect several typical circuit structural representations of unit.
As shown in Figure 4, wherein on this, draw pFET application of logic circuit module 410 by 411,412,413,414,415 5 pFETPipe and a sram cell 416 form. Wherein, the source electrode of pipe 411 connects power supply, join two pipes together 412 source electrode of drain electrode, grid bySram cell output s controls; Join two pipes together 411 the drain electrode of the source electrode of pipe 412, join two pipes together 413,415 source electrode of drain electrode connects simultaneouslyThe drain electrode of pipe 414, grid is controlled by signal a; The source electrode of pipe 413 connects 412 drain electrode, and drain electrode connects holding wire y end, grid bySignal a controls; Pipe 414 source electrodes connect power supply, join two pipes together 415 source electrode of drain electrode, and grid is controlled by signal b; Pipe 415 source electrodes connectThe drain electrode of pipe 412,414, drain electrode connects holding wire y end, and grid is controlled by sram cell output s.
In the time that in sram cell 416, storing value is configured to high level 1,411,415 cut-offs of pFET pipe, pipe 413 and 414Series connection, a and b signal are controlled respectively pipe 413 and 414, have realized the pFET circuit logic function of NOR operation; Work as sram cellWhen in 416, storing value is configured to low level 0, pFET manages 411,415 conductings, pipe 412 and 414 parallel connections, and a and b signal are respectivelyControl pipe 412 and 414,413 and 415 parallel connections, the two is connected again, has realized the pFET circuit logic function of NAND operation. ?Storing value in sram cell 416 has determined the logic function of NANDORpFET circuit.
Equally, 420 modules in Fig. 4 are nFET application of logic circuit module, are managed by 421,422,423,424,425 5 nFETComposition, with pFET logic circuit part symmetry in Fig. 4.
Wherein, the drain electrode of pipe 421 connects holding wire y end, join two pipes together 422 drain electrode of source electrode, and grid is exported s by sram cellControl; Join two pipes together 421 source electrode of the drain electrode of pipe 422, join two pipes together 423,425 drain electrode of source electrode, 424 the source of simultaneously joining two pipes togetherThe utmost point, grid is controlled by signal a; The drain electrode of pipe 423 connects 422 source electrode, source ground, and grid is controlled by signal a; Pipe 424The drain electrode utmost point connects holding wire y end, join two pipes together 425 drain electrode of source electrode, and grid is controlled by signal b; Pipe 425 drain the utmost point join two pipes together 422,424 source electrode, source ground, grid is controlled by sram cell output s. It is mono-that its s signal comes from the shared SRAM of 410 modulesUnit.
In the time that in sram cell, storing value is configured to high level 1, nFET manages 421,425 conductings, and pipe 422 and 424 alsoConnection, a and b signal are controlled respectively pipe 422 and 424,423 and 425 parallel connections, and the two is connected again, has realized the nFET electricity of NOR operationRoad logic function; In the time that in sram cell, storing value is configured to low level 0,421,425 cut-offs of nFET pipe, pipe 423 and 424Series connection, a and b signal are controlled respectively pipe 423 and 424, have realized the nFET circuit logic function of NAND operation.
Module 410 is connected by y holding wire with module 420 and draws port output from y holding wire, can be somebody's turn to do by configurationSram cell can be realized complete NAND or NOR logic function.
Similarly, the pFET logic circuit of NANDOR elementary cell also can be by 610 modules in Fig. 5 510, in Fig. 6 etc.Shown in circuit structure realize.
Wherein, the s signal and a data that in the module 410 shown in Fig. 4, on first-, tri-pFET pipes, connect are interchangeable, same,The s signal and a data that on first-, tri-nFET pipes in module 420, connect are interchangeable.
As shown in Figure 5, in 510 modules, the source electrode of pipe 511 connects power supply, and join two pipes together 512 source electrode of drain electrode is joined two pipes together simultaneously514 drain electrode, grid is controlled by signal a; Join two pipes together 511,514 the drain electrode of the source electrode of pipe 512, join two pipes together 513 source of drain electrodeThe utmost point, 515 the source electrode of simultaneously joining two pipes together, grid is controlled by signal a; The source electrode of pipe 513 connects 512 drain electrode, and drain electrode meets holding wire yEnd, grid is controlled by sram cell output s; Pipe 514 source electrodes connect power supply, join two pipes together 512,515 source electrode of drain electrode, grid bySram cell output s controls; Join two pipes together 511,514 the drain electrode of pipe 515 source electrodes, drain electrode connects holding wire y end, and grid is by signal bControl.
As shown in Figure 6, in 610 modules, the source electrode of pipe 611 connects power supply, drain electrode joins two pipes together 612, source electrode, take over simultaneouslyThe drain electrode of son 614, grid is controlled by signal a; Join two pipes together 611,614 the drain electrode of the source electrode of pipe 612 connects 615 source electrode simultaneously,Join two pipes together 613 source electrode of drain electrode, grid is controlled by sram cell output s; The source electrode of pipe 613 connects 612 drain electrode, and drain electrode connects letterNumber line y end, grid is controlled by signal a; Pipe 614 source electrodes connect power supply, join two pipes together 612,615 source electrode of drain electrode, and grid is by SRAMUnit output s controls; Join two pipes together 611,614 the drain electrode of pipe 615 source electrodes, drain electrode connects holding wire y end, and grid is controlled by signal b.
The nFET logic circuit of NANDOR elementary cell also can be by circuit shown in 611 modules in Fig. 5 511, in Fig. 6 etc.Structure realizes.
As shown in Figure 5, in 520 modules, the drain electrode of pipe 521 connects holding wire y end, join two pipes together 522 drain electrode of source electrode, simultaneouslyJoin two pipes together 524 source electrode, grid is controlled by signal a; Join two pipes together 521,524 source electrode of the drain electrode of pipe 522, source electrode is joined two pipes together523 drain electrode, grid is controlled by signal a; The drain electrode of pipe 523 connects 522 source electrode, source ground, and grid is defeated by sram cellGoing out s controls; Pipe 524 drain electrode connects holding wire y end, and join two pipes together 522,525 drain electrode of source electrode connects 521 source electrode simultaneously, grid bySram cell output s controls; Pipe 525 join two pipes together 521,524 the source electrode of the utmost point that drains, 522 the drain electrode of simultaneously joining two pipes together, source electrode connectsGround, grid is controlled by signal b.
As shown in Figure 6, in 620 modules, the drain electrode of pipe 621 connects holding wire y end, join two pipes together 622 drain electrode of source electrode, simultaneouslyJoin two pipes together 624 source electrode, grid is controlled by signal a; Join two pipes together 621,624 source electrode of the drain electrode of pipe 622, source electrode is joined two pipes together623 drain electrode, grid is controlled by sram cell output s; The drain electrode of pipe 623 connects 622 source electrode, source ground, and grid is by believingNumber a controls; Pipe 624 drain electrode connects holding wire y end, join two pipes together 622,625 drain electrode of source electrode, 621 the source electrode of simultaneously joining two pipes together, gridThe utmost point is controlled by sram cell output s; Join two pipes together 621,624 source electrode of pipe 625 drain electrode, source ground, grid is controlled by signal bSystem.
The logic of the structure shown in the logic function that the circuit structure shown in above-mentioned Fig. 5 and Fig. 6 is realized and described Fig. 4Function is identical, and, in the time that s is high level 1, described upper pull-up network pFET application of logic circuit module realizes the pFET electricity of neither-NOR operationRoad logic function, described pulldown network nFET application of logic circuit module realizes the nFET circuit logic function of neither-NOR operation; WhenWhen the output control signal of SRAM memory cell is low level, described upper pull-up network pFET application of logic circuit module realizes NAND behaviourThe pFET circuit logic function of doing, described pulldown network nFET application of logic circuit module realizes the nFET circuit logic of NAND operationFunction.
The above-mentioned programmable logic cells based on AOI structure that the present invention also proposes can also pass through the second embodimentThe second circuit structure of middle proposition is realized.
The disclosed programmable logic cells based on AOI structure in second embodiment of the invention, it comprises AOI baseThis unit, described AOI elementary cell realizes the first input data under the control of the output control signal of SRAM memory cellWith the function of the second input data NAND or nondisjunction, by multistage interconnected, can realize any logic function and express formula;
Wherein, described AOI elementary cell comprises: upper pull-up network pFET application of logic circuit module and pulldown network nFET patrolCollect circuit module; Upper pull-up network pFET application of logic circuit module comprises that at least one pFET is at least one the 5th pFET pipe;
The source electrode of described at least one pFET pipe and at least one the 3rd pFET pipe connects power supply, described at least one theThe drain electrode of one pFET pipe connects the source electrode of at least one the 2nd pFET pipe and at least one the 5th pFET pipe, described at least one the 3rdThe drain electrode of pFET pipe connects the described source electrode of at least one the 4th pFET pipe and the drain electrode of described at least one the 5th pFET pipe, described inAt least one the 2nd pFET and described at least one the 4th pFET pipe drain signal line y end; Described at least one first toThe grid of at least one the 2nd pFET pipe of pFET connects respectively the output control letter of described the first input data and SRAM memory cellIn number one, the grid that described at least one the 3rd pFET one of manages at least at least one the 4th pFET connects described second defeatedEnter data, the grid of at least one the 5th pFET pipe connects the inversion signal of the output control signal of described SRAM memory cell.
Described pulldown network nFET application of logic circuit module comprises that at least one nFET is at least one the 5th nFET pipe;
The drain electrode of described at least one nFET pipe and at least one the 3rd nFET pipe connects holding wire y end, at least describedThe source electrode utmost point of an one nFET pipe connects the drain electrode of at least one the 2nd nFET pipe and at least one the 5th nFET pipe, at least describedThe source electrode of a 3rd nFET pipe connects the drain electrode of described at least one the 4th nFET pipe and described at least one the 5th nFET pipeSource electrode, the source ground of described at least one the 2nd nFET and described at least one the 4th nFET pipe; Described at least one firstConnect respectively the output control signal of described the first input data and SRAM memory cell to the grid of at least one the 2nd nFET pipeIn one of them, described at least one the 3rd nFET connects described second to the grid that at least one the 4th nFET one of manages at leastInput data, the grid of at least one the 5th nFET pipe connects the inversion signal of the output control signal of described SRAM memory cell.
The typical case of the second circuit structure that second embodiment of the invention proposes realizes as Figure 7-8, is situated between in detail belowContinue.
The pFET application of logic circuit module of NANDOR elementary cell also can realize by 710 modules shown in Fig. 7,710 by711,712,713,714,715 5 pFET pipes, a sram cell 716 and an inverter modules composition.
Sram cell 716 output s are connected to phase inverter input, produce oppositely output ns.
In 710 modules, pipe 711 source electrodes connect power supply, join two pipes together 712,715 source electrode of drain electrode, and grid is controlled by signal a;Join two pipes together 711 the drain electrode of pipe 712 source electrodes, drain electrode connects holding wire y end, and grid is controlled by signal s; Pipe 713 source electrodes connect power supply,Drain electrode join two pipes together 714 source electrode and the drain electrode of pipe 715, grid is controlled by signal s; Pipe 714 source electrodes connect 713 drain electrode, leakThe utmost point connects holding wire y end, and grid is controlled by signal b; The grid of pipe 715 is controlled by signal ns.
In the time that in sram cell 716, storing value is configured to high level 1, s signal end is that 1, ns is low level 0, pipeSon 712,713 cut-offs, 715 conductings, a and b signal are controlled respectively pipe 711 and 714, and pipe 711 and 714 series connection, have realized NORThe pFET circuit logic function of operation; In the time that in sram cell 716, storing value is configured to low level 0, s signal end is 0, nsBe low level 1, pipe 715 ends, 712 and 713 conductings, and pipe 711 and 714 parallel connections, control respectively by a and b signal, realShow the pFET circuit logic function of NAND operation.
Equally, 720 modules in Fig. 7 are nFET application of logic circuit module, are managed by 721,722,723,724,725 5 nFETComposition, with pFET logic circuit part symmetry in Fig. 7. Wherein s signal is from the sram cell shared with 710 modules.
In 720 modules, pipe 721 drain electrode connects signal y end, join two pipes together 722,725 drain electrode of source electrode, and grid is controlled by signal aSystem; Join two pipes together 721 source electrode of pipe 722 drain electrode, source ground, grid is controlled by signal s; Pipe 723 drain electrodes connect signal y end,Source electrode join two pipes together 724 drain electrode and the source electrode of pipe 725, grid is controlled by signal s; Pipe 724 drain electrodes connect 723 source electrode, sourceUtmost point ground connection, grid is controlled by signal b; The grid of pipe 725 is controlled by signal ns.
In the time that in sram cell, storing value is configured to high level 1, s signal end is that 1, ns is low level 0. NFET pipe722,723 conductings, 715 cut-offs, pipe 722 and 723 parallel connections, a and b signal are controlled respectively pipe 722 and 723, have realized NOR behaviourThe nFET circuit logic function of doing; In the time that in sram cell, storing value is configured to low level 0, s signal end is that 0, ns is lowLevel 1. 722,723 cut-offs of nFET pipe, pipe 721 and 724 series connection, a and b signal are controlled respectively pipe 721 and 724, have realizedThe nFET circuit logic function of NAND operation.
Module 710 is connected by y holding wire with module 720 and draws port output from y holding wire, can be somebody's turn to do by configurationSram cell can be realized complete NAND or NOR logic function.
Similarly, the pFET of NANDOR elementary cell and nPFET logic circuit also can be by 810 and 820 moulds shown in Fig. 8Piece circuit is realized.
In 810 modules, pipe 811 source electrodes connect power supply, join two pipes together 812,815 source electrode of drain electrode, and grid is controlled by signal a;Join two pipes together 811 the drain electrode of pipe 812 source electrodes, drain electrode connects holding wire y end, and grid is controlled by signal s; Pipe 813 source electrodes connect power supply,Drain electrode join two pipes together 814 source electrode and the drain electrode of pipe 815, grid is controlled by signal b; Pipe 814 source electrodes connect 813 drain electrode, leakThe utmost point connects holding wire y end, and grid is controlled by signal b; The grid of pipe 815 is controlled by signal ns.
In 820 modules, pipe 821 drain electrode connects signal y end, join two pipes together 822,825 drain electrode of source electrode, and grid is controlled by signal aSystem; Join two pipes together 821 source electrode of pipe 822 drain electrode, source ground, grid is controlled by signal s; Pipe 823 drain electrodes connect signal y end,Source electrode join two pipes together 824 drain electrode and the source electrode of pipe 825, grid is controlled by signal b; Pipe 824 drain electrodes connect 823 source electrode, sourceUtmost point ground connection, grid is controlled by signal b; The grid of pipe 825 is controlled by signal ns.
Wherein, the s signal and a data that in the module 810 shown in Fig. 8, on the first-two pFET pipe, connect are interchangeable, same,The s signal and a data that on the first-two nFET pipe in module 820, connect are interchangeable.
Upper pull-up network pFET application of logic circuit module shown in Fig. 7-8 and pulldown network nFET application of logic circuit module can be anyConstitute NANDOR elementary cell.
The above-mentioned programmable logic cells based on AOI structure that the present invention also proposes can also pass through the 3rd embodimentThe third circuit structure of middle proposition is realized.
The programmable logic cells based on AOI structure proposing in third embodiment of the invention, it comprises AOI baseThis unit, described AOI elementary cell realizes the first input data under the control of the output control signal of SRAM memory cellWith the function of the second input data NAND or nondisjunction, by multistage interconnected, can realize any logic function and express formula;
Wherein, described AOI elementary cell comprises: upper pull-up network pFET application of logic circuit module and pulldown network nFET patrolCollect circuit module; Upper pull-up network pFET application of logic circuit module comprises that at least one pFET pipe is at least one the 6th pFETPipe;
The source electrode of described at least one pFET pipe and at least one the 4th pFET pipe connects power supply, described at least one theThe drain electrode of one pFET pipe connects the source electrode of at least one the 2nd pFET pipe, described in the drain electrode of described at least one the 4th pFET pipe connects extremelyThe source electrode of few a 5th pFET pipe, the drain electrode of described at least one the 2nd pFET connects the source of described at least one the 3rd pFET pipeThe utmost point, the drain electrode of described at least one the 5th pFET pipe connects the source electrode of described at least one the 6th pFET pipe, described at least one theThe drain electrode of three pFET pipes and described at least one the 6th pFET pipe connects holding wire y end; Wherein, described at least one the 4th pFET pipeDrain electrode and the drain electrode interconnection of described at least one pFET pipe or the drain electrode of described at least one the 4th pFET pipe with at leastThe drain electrode interconnection of a 2nd pFET pipe, to be divided into described upper pull-up network pFET application of logic circuit module two that connect up and downPoint; Described at least one pFET pipe to the grid of at least one the 3rd pFET pipe connect respectively described first input data andIn the output control signal of SRAM memory cell one, described at least one the 4th pFET pipe is at least one the 6th pFET pipeGrid meet in the output control signal of described second input data and SRAM memory cell.
Described pulldown network nFET application of logic circuit module comprises that at least one nFET pipe is at least one the 6th nFETPipe;
The drain electrode of described at least one nFET pipe and at least one the 4th nFET pipe connects holding wire y end, at least describedThe source electrode of an one nFET pipe connects the drain electrode of at least one the 2nd nFET pipe, and the source electrode of described at least one the 4th nFET pipe connectsThe drain electrode of described at least one the 5th nFET pipe, the source electrode of described at least one the 2nd nFET meets described at least one the 3rd nFETThe drain electrode of pipe, the source electrode of described at least one the 5th nFET pipe connects the drain electrode of described at least one the 6th nFET pipe, at least describedThe source electrode of a 3rd nFET pipe and described at least one the 6th nFET pipe connects holding wire y end; Wherein, described at least one the 4thThe source electrode of nFET pipe is connected with the source electrode of at least one the 2nd nFET pipe, so that described upper pull-up network pFET application of logic circuit module is dividedBecome two parts of series connection up and down; Described in described at least one nFET pipe connects respectively to the grid of at least one the 3rd nFET pipeIn the output control signal of first input data and SRAM memory cell one, described at least one the 4th nFET pipe is at leastThe grid of a 6th nFET pipe meets in the output control signal of described second input data and SRAM memory cell.
The typical case of the third circuit structure realizes as shown in Figure 9, introduces in detail below.
The pFET application of logic circuit module of NANDOR elementary cell also can realize by 910 modules shown in Fig. 9,910 by911,912,913,914,915,916 6 pFET pipes, a sram cell 917 form.
As shown in Figure 9, in 910 modules, the source electrode of pipe 911 connects power supply, join two pipes together 912 source electrode of drain electrode, and grid is by SRAMUnit output s controls; Join two pipes together 911 the drain electrode of the source electrode of pipe 912, join two pipes together 913,915 source electrode of drain electrode, grid is by signalA controls; Join two pipes together 912,914 the drain electrode of the source electrode of pipe 913, drain electrode connects holding wire y end, and grid is controlled by signal a; Pipe914 source electrodes connect power supply, join two pipes together 913,915 source electrode of drain electrode, and grid is controlled by signal b; Pipe 915 source electrodes join two pipes together 912,914 drain electrode, join two pipes together 916 source electrode of drain electrode, grid is controlled by sram cell output s; Pipe 916 source electrodes join two pipes together 915Drain electrode, drain electrode connects holding wire y end, and grid is controlled by signal b.
In the time that in sram cell 917, storing value is configured to high level 1, pipe 911,915 cut-offs, a signal controlling 912 Hes913, b signal controlling pipe 914 and 916, pipe 913 and 914 series connection, have realized the pFET circuit logic function that NOR operates; WhenWhen in sram cell 917, storing value is configured to low level 0, pipe 911 and 915 conductings, have realized the pFET electricity that NAND operatesRoad logic function.
Equally, 920 modules in Fig. 9 are nFET application of logic circuit module, by 921,922,923,924,925,926 6PFET manages composition, with pFET logic circuit part symmetry in Fig. 9. Wherein s signal is from the sram cell shared with 910 modules.
In 920 modules, the drain electrode of pipe 921 connects holding wire y end, join two pipes together 922 drain electrode of source electrode, and grid is by sram cellOutput s controls; Join two pipes together 921 source electrode of the drain electrode of pipe 922, join two pipes together 923,925 drain electrode of source electrode joins two pipes together 924 simultaneouslySource electrode, grid is controlled by signal a; The drain electrode of pipe 923 connects 922 source electrode, source ground, and grid is controlled by signal a; PipeThe 924 drain electrode utmost points connect holding wire y end, join two pipes together 923,925 drain electrode of source electrode, and grid is controlled by signal b; Pipe 925 drain electrodes are taken overSon 922,924 source electrode, join two pipes together 926 drain electrode of source electrode, grid is controlled by sram cell output s; Pipe 926 drain electrodes are joined two pipes together925 source electrode, source ground, grid is controlled by signal b.
In the time that in sram cell, storing value is configured to high level 1, nFET manages 921 and 923 conductings, has realized NOR operationNFET circuit logic function; In the time that in sram cell, storing value is configured to low level 0,921 and 923 cut-offs of nFET pipe, pipeSon 923 and 924 series connection, a and b signal are controlled respectively pipe 923 and 924, have realized the nFET circuit logic function of NAND operation.
Module 910 is connected by y holding wire with module 920 and draws port output from y holding wire, can be somebody's turn to do by configurationSram cell can be realized complete NAND or NOR logic function.
Wherein, the s signal and a data that in the module 910 shown in Fig. 9, on first-, tri-pFET pipes, connect are interchangeable, the 3rd toThe s signal and the b signal that on the 6th pFET pipe, connect are interchangeable, same, the s signal connecing on first-, the tri-nFET pipes in module 920Interchangeable with a data, the s signal and the b signal that on the 3rd to the 6th nFET pipe, connect are interchangeable.
The way of realization of NANDOR elementary cell can be pFET application of logic circuit module and the nFET in said units equallyAny combination of application of logic circuit module realizes.
Upper pull-up network pFET application of logic circuit module shown in Fig. 4-9 and pulldown network nFET application of logic circuit module can be anyConstitute NANDOR elementary cell. Further, the upper pull-up network pFET logic electricity shown in Fig. 4-9 that the present invention proposesRoad module can also with in prior art, draw in the net nFET application of logic circuit module under any other and can be combined and form NANDOR baseThis unit.
The present invention proposes a kind of programmable logic cells based on AOI wimble structure, can be using this element as basicThe basic composition unit of AIC logic, by multilayer cascade, realizes various complex logic function. This NANDOR logic listMeta structure is simple, compared with basic AIC unit in Fig. 2, realizes the required number of tubes of complete function and can reduce, and institute is passed throughTime delay path also smaller, therefore all more excellent than the AIC elementary cell in prior art Fig. 2 on area and delay performance. WithTime this NANDOR logical block alleviated the different configuring condition path delay that the AIC elementary cell in Fig. 2 exists and differed greatlyProblem, can adjust by the pipe parameter in structure of the present invention, can realize the difference that difference is configured to time delayBe transferred to required scope.
The NANDOR unit that the present invention proposes is keeping the speed of Fig. 2 AIC elementary cell compared with traditional LUT structureHurry up, extensibility is strong, and the multiplexing logical resource of energy promotes on the basis of feature of resource utilization, more simple on structure realizesSingle, area is less, and speed is faster, and can make up that Fig. 2 AIC elementary cell exists by adjusting the method for pipe parameterConfiguration path delay difference problem.
Above-described specific embodiment, has carried out further in detail object of the present invention, technical scheme and beneficial effectDescribe in detail brightly, it should be understood that and the foregoing is only specific embodiments of the invention, be not limited to the present invention, allWithin the spirit and principles in the present invention, any amendment of making, be equal to replacement, improvement etc., all should be included in protection of the present inventionWithin scope.
Claims (11)
1. the programmable logic cells based on AOI structure, it comprises AOI elementary cell, described AOI is basicThe first input data and the second input data NAND are realized in unit under the control of the output control signal of SRAM memory cellOr the function of nondisjunction, by multistage interconnected, can realize any logic function and express formula;
Wherein, described AOI elementary cell comprises: upper pull-up network pFET application of logic circuit module and pulldown network nFET logic electricityRoad module; Described upper pull-up network pFET application of logic circuit module comprises that at least one pFET pipe is at least one the 5th pFETPipe;
The source electrode of described at least one pFET pipe and at least one the 4th pFET pipe connects power supply, described at least one firstThe drain electrode of pFET pipe connects the source electrode of at least one the 2nd pFET pipe, described in the drain electrode of described at least one the 4th pFET pipe connects at leastThe source electrode of a 5th pFET pipe, the drain electrode of described at least one the 2nd pFET connects the source of described at least one the 3rd pFET pipeThe utmost point, the drain electrode of described at least one the 3rd pFET pipe and described at least one the 5th pFET pipe connects holding wire y end; Wherein, described inThe drain electrode interconnection of at least one the 4th pFET pipe drain electrode and described at least one pFET pipe or described at least one the 4thThe drain electrode interconnection of the drain electrode of pFET pipe and at least one the 2nd pFET pipe, to divide described upper pull-up network pFET application of logic circuit moduleBecome two parts of series connection up and down; Described in described at least one pFET pipe connects respectively to the grid of at least one the 3rd pFET pipeIn the output control signal of first input data and SRAM memory cell one, described at least one the 4th pFET pipe is at leastThe grid of a 5th pFET pipe meets in the output control signal of described second input data and SRAM memory cell.
2. the programmable logic cells based on AOI structure as claimed in claim 1, wherein, described at least one firstThe grid that pFET pipe, at least one the 2nd pFET pipe and at least one the 3rd pFET manage one of them connects the defeated of SRAM memory cellGo out signal, all the other grids of two connect the first input data, described at least one the 4th pFET pipe and at least one the 5th pFETThe grid of one of them of pipe connects the output control signal of SRAM memory cell, and the grid of another pFET pipe connects the second inputData, and in described at least one pFET pipe, at least one the 2nd pFET pipe and at least one the 3rd pFET pipe with described inThe pFET that connects the output signal of SRAM memory cell at least one the 4th pFET pipe and at least one the 5th pFET pipe is not positioned atIn a described same part of connecting up and down in two parts.
3. the programmable logic cells based on AOI structure as claimed in claim 2, wherein, described at least one the 4thThe drain electrode interconnection of the drain electrode of pFET pipe and described at least one the 2nd pFET pipe, the grid of described at least one pFET pipe connectsThe output control signal of SRAM memory cell, the grid of described at least one the 2nd pFET pipe and at least one the 3rd pFET pipe connectsThe first input data, the grid of described at least one the 4th pFET pipe connects the second input data, described at least one the 5th pFETThe grid of pipe connects the output control signal of SRAM memory cell.
4. the programmable logic cells based on AOI structure as claimed in claim 2, wherein, described at least one the 4thThe drain electrode interconnection of the drain electrode of pFET pipe and described at least one pFET pipe, described at least one pFET pipe and at least oneThe grid of individual the 2nd pFET pipe connects the first input data, and the grid of described at least one the 3rd pFET pipe connects SRAM memory cellOutput control signal, the grid of described at least one the 4th pFET pipe connects the output control signal of SRAM memory cell, extremely describedThe grid of few a 5th pFET pipe connects the second input data.
5. the programmable logic cells based on AOI structure as claimed in claim 2, wherein, described at least one the 4thThe drain electrode interconnection of the drain electrode of pFET pipe and described at least one pFET pipe, described at least one pFET pipe and at least oneThe grid of individual the 3rd pFET pipe connects the first input data, and the grid of described at least one the 2nd pFET pipe connects SRAM memory cellOutput control signal, the grid of described at least one the 4th pFET pipe connects the output control signal of SRAM memory cell, extremely describedThe grid of few a 5th pFET pipe connects the second input data.
6. the programmable logic cells based on AOI structure as described in claim 1-5 any one, wherein, draws in the net under describedNetwork nFET application of logic circuit module comprises that at least one nFET pipe is at least one the 5th nFET pipe;
The drain electrode of described at least one nFET pipe and at least one the 4th nFET pipe connects holding wire y end, described at least oneThe source electrode of the one nFET pipe connects the drain electrode of at least one the 2nd nFET pipe, described in the source electrode of described at least one the 4th nFET pipe connectsThe drain electrode of at least one the 5th nFET pipe, the source electrode of described at least one the 2nd nFET connects described at least one the 3rd nFET pipeDrain electrode, the source ground of described at least one the 3rd nFET pipe and described at least one the 5th nFET pipe; Wherein, described at least oneThe source electrode interconnection of individual the 4th nFET pipe source electrode and described at least one nFET pipe or described at least one the 4th nFET pipeSource electrode and the source electrode interconnection of at least one the 2nd nFET pipe, so that described pulldown network nFET application of logic circuit module is divided into up and downTwo parts of series connection; Described at least one nFET pipe to the grid of at least one the 3rd nFET pipe connects respectively described first defeatedEnter in the output control signal of data and SRAM memory cell, described at least one the 4th nFET pipe at least oneThe grid of five nFET pipes meets in the output control signal of described second input data and SRAM memory cell.
7. the programmable logic cells based on AOI structure as claimed in claim 6, wherein, described at least one firstThe grid that nFET pipe, at least one the 2nd nFET pipe and at least one the 3rd nFET manage one of them connects the defeated of SRAM memory cellGo out signal, all the other grids of two connect the first input data, described at least one the 4th nFET pipe and at least one the 5th nFETThe grid of one of them of pipe connects the output control signal of SRAM memory cell, and the grid of another nFET pipe connects the second inputData, and in described at least one nFET pipe, at least one the 2nd nFET pipe and at least one the 3rd nFET pipe with described inThe nFET that connects the output signal of SRAM memory cell at least one the 4th nFET pipe and at least one the 5th nFET pipe is not positioned atIn a described same part of connecting up and down in two parts.
8. the programmable logic cells based on AOI structure as claimed in claim 7, wherein, described at least one the 4thThe source electrode interconnection of the source electrode of nFET pipe and described at least one the 2nd nFET pipe, the grid of described at least one nFET pipe connectsThe output control signal of SRAM memory cell, the grid of described at least one the 2nd nFET pipe and at least one the 3rd nFET pipe connectsThe first input data, the grid of described at least one the 4th nFET pipe connects the second input data, described at least one the 5th nFETThe grid of pipe connects the output control signal of SRAM memory cell.
9. the programmable logic cells based on AOI structure as claimed in claim 7, wherein, described at least one the 4thThe source electrode interconnection of the source electrode of nFET pipe and described at least one nFET pipe, described at least one nFET pipe and at least oneThe grid of individual the 2nd nFET pipe connects the first input data, and the grid of described at least one the 3rd nFET pipe connects SRAM memory cellOutput control signal, the grid of described at least one the 4th nFET pipe connects the output control signal of SRAM memory cell, extremely describedThe grid of few a 5th nFET pipe connects the second input data.
10. the programmable logic cells based on AOI structure as claimed in claim 7, wherein, described at least one the 4thThe source electrode interconnection of the source electrode of nFET pipe and described at least one nFET pipe, described at least one nFET pipe and at least oneThe grid of individual the 3rd nFET pipe connects the first input data, and the grid of described at least one the 2nd nFET pipe connects SRAM memory cellOutput control signal, the grid of described at least one the 4th nFET pipe connects the output control signal of SRAM memory cell, extremely describedThe grid of few a 5th nFET pipe connects the second input data.
11. programmable logic cells based on AOI structure as described in claim 1-5,7-10 any one, wherein, whenWhen the output control signal of SRAM memory cell is high level, described upper pull-up network pFET application of logic circuit module realizes the first inputThe pFET circuit logic function of data and the second input data neither-NOR operation, described pulldown network nFET application of logic circuit module is realThe nFET circuit logic function of existing the first input data and the second input data neither-NOR operation; When the output of SRAM memory cellWhen control signal is low level, described upper pull-up network pFET application of logic circuit module realizes the first input data and the second input dataThe pFET circuit logic function of NAND operation, described pulldown network nFET application of logic circuit module realizes the first input data andThe nFET circuit logic function of two input data NAND operations.
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| CN1547324A (en) * | 2003-12-16 | 2004-11-17 | 复旦大学 | Programmable logic unit structure |
| CN101682329A (en) * | 2008-01-30 | 2010-03-24 | 雅格罗技（北京）科技有限公司 | A kind of integrated circuit with improved logical block |
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