CN105609508A - TFT back plate and manufacturing method therefor - Google Patents
TFT back plate and manufacturing method therefor Download PDFInfo
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- CN105609508A CN105609508A CN201510975536.XA CN201510975536A CN105609508A CN 105609508 A CN105609508 A CN 105609508A CN 201510975536 A CN201510975536 A CN 201510975536A CN 105609508 A CN105609508 A CN 105609508A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
Abstract
A TFT back plate is disclosed. The TFT back plate comprises a first metal layer, a capacitance insulation layer positioned on the first metal layer, and a second metal layer positioned on the capacitance insulation layer, wherein an insulating dielectric layer is formed on the second metal layer; a third metal layer is formed on the insulating dielectric layer; the third metal layer passes through gate via holes formed in the insulating dielectric layer and the capacitance insulation layer to be in contact with the first metal layer; and hollow-out parts for allowing the gate via holes to pass through are formed in the second metal layer. According to the TFT back plate, the first metal layer and the third metal layer are used as a polar plate for a storage capacitor while the second metal layer is used as the other polar plate for the storage capacitor; the storage capacitor is divided into three parts, so that the area of the storage capacitor can be effectively enlarged under a limited layout area; and the invention also provides a manufacturing method for the TFT back plate.
Description
Technical field
The present invention relates to Display Technique field, relate in particular to a kind of TFT backboard and manufacture method thereof.
Background technology
Show field in plane, the image element circuit storage capacitor construction of TFT backboard generally comprises glassSubstrate, is directly formed at the polysilicon layer (p-Si layer) on glass substrate, is directly formed at glass-basedGate insulator (GI layer, GateInsulationLayer) on plate and polysilicon layer, directly shapeBe formed on gate insulator and be positioned at the first metal layer of polysilicon layer top, being directly formed at gridCapacitive insulation layer (CI layer, CapacitanceInsulation on insulating barrier and the first metal layerLayer), be directly formed on capacitive insulation layer and be positioned at the second metal level of the first metal layer top,Wherein, the first metal layer is as the grid of drive TFT, simultaneously also as the utmost point of memory capacitancePlate, the second metal level is as another pole plate of memory capacitance, the first metal layer, the second metal levelAnd the partition capacitance insulating barrier being clipped between the first metal layer and the second metal level forms memory capacitance.
The memory capacitance of image element circuit in the course of the work can storing driver TFT grid potential, withThe raising of display resolution, needed capacitance is also increasing. In current pixelIn circuitry stores capacitance structure, two using the first metal layer and the second metal level as electric capacity respectivelyPole plate, because two pole plates of electric capacity are planar structure, therefore just will obtain larger capacitanceNeed very large chip area, and the increase of capacity area can cause display unit aperture opening ratio underFall, affect display effect.
Summary of the invention
In view of this, the invention provides and a kind ofly can under limited chip area, effectively increase storageTFT backboard and the manufacture method thereof of capacitance.
TFT backboard provided by the invention comprises the first metal layer, is positioned on described the first metal layerCapacitive insulation layer and be positioned at the second metal level on described capacitive insulation layer, described the second metal levelOn be formed with insulating medium layer, on described insulating medium layer, be formed with the 3rd metal level, the described the 3rdMetal level is through the some grid via holes that form on described insulating medium layer and described capacitive insulation layerContact with described the first metal layer, on described the second metal level, be formed with for described grid via hole and pass throughSome hollow-out parts.
According to one embodiment of present invention, a part for described the second metal level is positioned at described firstDirectly over metal level, described the 3rd metal level comprise be positioned at described the second metal level directly overPart I and the Part II contacting with described the first metal layer through described grid via hole.
According to one embodiment of present invention, described the first metal layer, described the second metal level andThe partition capacitance insulating barrier being clipped between described the first metal layer and described the second metal level forms oneThe first electric capacity, the Part I of described the second metal level, described the 3rd metal level and be clipped in described inSI semi-insulation dielectric layer between the Part I of the second metal level and described the 3rd metal level formsOne second electric capacity, the Part II of described the second metal level, described the 3rd metal level and be clipped in instituteThe SI semi-insulation of stating between the side of the second metal level and the Part II of described the 3rd metal level is situated betweenMatter layer forms one the 3rd electric capacity, and the memory capacitance of described TFT comprises described the first electric capacity, described theTwo electric capacity and described the 3rd electric capacity.
According to one embodiment of present invention, the area of described memory capacitance equals described the first electricityThe area sum of appearance, described the second electric capacity and described the 3rd electric capacity.
According to one embodiment of present invention, the area of described memory capacitance equals described the first metalLayer and effective projected area of described the second metal level, described the second metal level and described the 3rd metalLayer effective projected area of described Part I and the side of described the second metal level with described inIt is total that effective projected area sum of the described Part II of the 3rd metal level deducts described grid via holeThe twice of area.
According to one embodiment of present invention, described TFT backboard also comprises substrate, is positioned on substrateSilicon nitride layer, be positioned at silicon oxide layer on silicon nitride layer, be positioned at polysilicon layer on silicon oxide layer,And being positioned at the gate insulator on polysilicon layer, it is exhausted that described the first metal layer is formed at described gridOn edge layer.
According to one embodiment of present invention, on described the 3rd metal level, be formed with planarization layer, instituteState and on planarization layer, be formed with anode.
The manufacture method of TFT backboard provided by the invention, comprising: form the first metal layer; InstituteState and on the first metal layer, form capacitive insulation layer; On described capacitive insulation layer, form the second metal levelAnd the second metal level described in patterning, on described the second metal level, form some hollow-out parts; InstituteState on the second metal level and form insulating medium layer; At described insulating medium layer and described capacitive insulation layerThe some grid via holes of upper formation, described grid via hole is through the described hollow-out parts of described the second metal levelExtend to described the first metal layer with described capacitive insulation layer by described insulating medium layer; Described exhaustedOn edge dielectric layer, form the 3rd metal level, described the 3rd metal level comprises and is positioned at described the second metal levelTop Part I and contact with described the first metal layer through described grid via hole theTwo parts.
According to one embodiment of present invention, described the first metal layer, described the second metal level andThe partition capacitance insulating barrier being clipped between described the first metal layer and described the second metal level forms oneThe first electric capacity, the Part I of described the second metal level, described the 3rd metal level and be clipped in described inSI semi-insulation dielectric layer between the Part I of the second metal level and described the 3rd metal level formsOne second electric capacity, the Part II of described the second metal level, described the 3rd metal level and be clipped in instituteThe SI semi-insulation of stating between the side of the second metal level and the Part II of described the 3rd metal level is situated betweenMatter layer forms one the 3rd electric capacity, and the memory capacitance of described TFT comprises described the first electric capacity, described theTwo electric capacity and described the 3rd electric capacity.
According to one embodiment of present invention, the area of described memory capacitance equals described the first electricityThe area sum of appearance, described the second electric capacity and described the 3rd electric capacity.
The present invention passes through to adopt three-layer metal, and offers hollow-out parts on the second metal level, and at electric capacityOn insulating barrier and insulating medium layer, offer grid via hole, make the 3rd metal level can be by grid via hole and theOne metal level is connected, thereby memory capacitance is divided into three parts, and has increased under limited chip areaThe area of memory capacitance, has effectively improved the capacity of memory capacitance.
Above-mentioned explanation is only the general introduction of technical solution of the present invention, in order to better understand the present inventionTechnological means, and can be implemented according to the content of description, and for allow of the present invention onState with other objects, feature and advantage and can become apparent, below especially exemplified by preferred embodiment, andCoordinate accompanying drawing, be described in detail as follows.
Brief description of the drawings
Figure 1 shows that the cross-sectional schematic of TFT backboard of the present invention;
Fig. 2 is the first metal layer of TFT backboard shown in Fig. 1 and the surface plate of below rete diagram thereofIntention, because silicon nitride layer, silicon oxide layer and gate insulator are transparent material layer, therefore,Only can see in the drawings substrate, polysilicon layer and the first metal layer;
Fig. 3 is the insulating medium layer of TFT backboard shown in Fig. 1 and the surface plate of below rete diagram thereofIntention, because capacitive insulation layer and insulating medium layer are transparent material layer, therefore, these two kinds absolutelyEdge layer is all invisible in the drawings, but for convenience of description, the perforate in these two kinds of insulating barriers is still at figureIn have shown;
Fig. 4 is the surface plate figure schematic diagram of the 3rd metal level of TFT backboard shown in Fig. 1, for justIn the corresponding relation of explanation the 3rd metal level and its below rete, grid via hole, many is also shown in figureCrystal silicon connecting hole and VDD connecting hole;
Wherein, 300-substrate, 301-silicon nitride layer, 302-silicon oxide layer, 303-polysilicon layer, 304-Gate insulator, 305-the first metal layer, 306-capacitive insulation layer, 307-the second metal level, 308-Insulating medium layer, 309-the 3rd metal level, 310-planarization layer, 311-anode, 312-hollow-out parts,313-grid via hole, 314-polysilicon connecting hole, 315-VDD connecting hole, C1-the first electric capacity,C2-the second electric capacity, C3-the 3rd electric capacity.
Detailed description of the invention
For further setting forth the present invention for the technological means reaching predetermined goal of the invention and take andEffect is below in conjunction with accompanying drawing and preferred embodiment, as follows to the detailed description of the invention.
Figure 1 shows that the cross-sectional schematic of TFT backboard of the present invention. As shown in Figure 1, of the present inventionTFT backboard comprises from bottom to top: substrate 300, be positioned at silicon nitride layer 301 on substrate 300,Be positioned at silicon oxide layer 302 on silicon nitride layer 301, be positioned at the polysilicon layer on silicon oxide layer 302303, be positioned at gate insulator 304 (GI layer, the GateInsulation on polysilicon layer 303Layer), be positioned at the first metal layer 305 on gate insulator 304, be positioned at the first metal layer 305On capacitive insulation layer 306 (CI layer, CapacitanceInsulationLayer), to be positioned at electric capacity exhaustedThe second metal level 307 on edge layer 306, be positioned at the insulating medium layer 308 on the second metal level 307(ILD layer, InsulationDielectricLayer), be positioned at the 3rd gold medal on insulating medium layer 308Belong to layer 309, be positioned at the planarization layer 310 on the 3rd metal level 309 and be positioned at planarization layerAnode 311 on 310.
Wherein, substrate 300 can be glass substrate, metal substrate or polymeric substrates, the present inventionBe preferably glass substrate. The first metal layer 305 can adopt metal molybdenum. Capacitive insulation layer 306 can be adoptedWith silica or silicon oxynitride. Insulating medium layer 308 can adopt silica that step coverage is good orSilicon oxynitride, it can adopt commaterial with capacitive insulation layer 306. The second metal level 307Can adopt commaterial with the first metal layer 305. The 3rd metal level 309 adopts titanium-aluminium alloy,Its structure adopting is titanium/aluminium/titanium structure, and the 3rd metal level 309 is by two-layer titanium coating and folderAluminum metal layer composition between this two-layer titanium coating.
The first metal layer 305 is as the grid of drive TFT, again as the first pole plate of memory capacitance.A part for the second metal level 307 be positioned at the first metal layer 305 directly over, as memory capacitanceThe second pole plate. Patternedly on the second metal level 307 be formed with some hollow-out parts 312, theseHollow-out parts 312 is the grid via hole 313 forming on capacitive insulation layer 306 and insulating medium layer 308Reserved empty position, makes the grid via hole 313 can be by the insulating medium layer 308 of the second metal level 307 topsArrive the capacitive insulation layer 306 of the second metal level 307 belows through the second metal level 307. TheThree metal levels 309 are as the tri-electrode of memory capacitance, and it comprises and is just being positioned at the second metal level 307The Part I of top, and contact the with the first metal layer 305 through grid via hole 313Two parts. By this kind of mode, make the final memory capacitance forming with the first metal layer 305 HesThe 3rd metal level 309 is as a capacitor plate, using the second metal level 307 as another electric capacityPole plate, like this, the memory capacitance that makes to form comprises the first capacitor C 1, the second capacitor C 2 and theThree 3 three of capacitor C parts, wherein, the first capacitor C 1 is by the first metal layer 305, the second metalLayer 307 and the partition capacitance being clipped between the first metal layer 305 and the second metal level 307 insulateLayer 306 forms, and the second capacitor C 2 is by the First of the second metal level 307, the 3rd metal level 309Point and to be clipped in part between the second metal level 307 and the Part I of the 3rd metal level 309 exhaustedEdge dielectric layer 308 forms, and the 3rd capacitor C 3 is by the second metal level 307, the 3rd metal level 309Part II and be clipped in the side of the second metal level 307 and second of the 3rd metal level 309SI semi-insulation dielectric layer 308 between point forms, can know in conjunction with background technology and the present invention,Generally the area of the memory capacitance of TFT image element circuit equates with the area of the first capacitor C 1, therefore,The area of the memory capacitance that the present invention forms is greater than the face of the memory capacitance of general TFT image element circuitLong-pending. The area of the memory capacitance that the present invention forms is the first capacitor C 1, the second capacitor C 2 and the 3rdThe area sum of capacitor C 3, the area of this memory capacitance can also calculate by following formula:
S＝S1+S2+S3-2*n*SHole；
Wherein, the area that S is memory capacitance, S1 is the first metal layer 305 and the second metal level 307Effective projected area, S2 is the Part I of the second metal level 307 and the 3rd metal level 309Effectively projected area, S3 is the side of the second metal level 307 and second of the 3rd metal level 309Effective projected area of dividing, n is the quantity of grid via hole 313, SHoleFor the face of grid via hole 313Long-pending, n*SHoleFor the gross area of grid via hole 313. Effectively projected area is two relative metal levelsIn a projection on another and the area of the overlapping part of another metal level, for example,Effective projected area of the first metal layer 305 and the second metal level 307 is that the first metal layer 305 existsThe area of the projection on the second metal level 307 and the overlapping part of the second metal level 307.
Further, the manufacture method of TFT backboard provided by the invention, comprising:
First, form the rete of the first metal layer 305 belows according to the technique of general TFT backboard,Be included in directly formation silicon nitride layer 301, directly formation on silicon nitride layer 301 on substrate 300Silicon oxide layer 302, on silicon oxide layer 302, directly form polysilicon layer 303, and at polycrystallineOn silicon layer 303, directly form gate insulator 304;
Then, on gate insulator 304, directly form the first metal layer 305 and carve by exposureErosion forms figure as shown in Figure 2, and the first metal layer 305 adopts metal molybdenum deposition to form, and firstThe rectangle part of metal level 305 is as the grid of drive TFT and the first pole plate of memory capacitance;
Then, on the first metal layer 305, directly form capacitive insulation layer 306;
Then, on capacitive insulation layer 306, directly form the second metal level 307 and carve by exposureErosion is patterned to figure as shown in Figure 3, the material of the second metal level 307 can with the first metal layer305 is commaterial, and it is as the second pole plate of memory capacitance, simultaneously as connecting VDD'sA part for cabling is formed with the hollow-out parts 312 of rectangle on the second metal level 307 after patterning,The area of hollow-out parts 312 is greater than the area of grid via hole 313;
Then, on the second metal level 307, directly form insulating medium layer 308, insulating medium layerA part of 308 is covered on the second metal level 307, and another part is filled in the second metal level 307Hollow-out parts 312 in;
Then, be etched on insulating medium layer 308 and capacitive insulation layer 306 and form grid by exposureUtmost point via hole 313 and polysilicon connecting hole 314, and on insulating medium layer 308, form VDD connectionHole 315, wherein grid via hole 313 is exhausted through hollow-out parts 312 and the electric capacity of the second metal level 307Edge layer 306 and extend to the first metal layer 305 by insulating medium layer 308, polysilicon connecting hole 314Pass insulating medium layer 308 and capacitive insulation layer 306 and extend to polycrystalline by insulating medium layer 308Silicon layer 303, VDD connecting hole 315 extends to the second metal level 307 by insulating medium layer 308;
Then, on insulating medium layer 308, directly form the 3rd metal level 309 and carve by exposureErosion forms figure as shown in Figure 4, and the 3rd metal level 309 adopts titanium/aluminium/titanium structure, the 3rd gold medalBelong to the top that layer 309 Part I is positioned at the second metal level 307, the of the 3rd metal level 309Two parts contact with the first metal layer 305 through grid via hole 313, the 3rd metal level 309The part (being Part I and Part II) being connected with grid is as the lambda line of writing of grid potential,And be connected with the first pole plate as the tri-electrode of memory capacitance, in addition, the 3rd metal level 309 is alsoComprise the part that is positioned at polysilicon connecting hole 314 and be connected with polysilicon layer 303 and be positioned atIn VDD connecting hole 315 and the part being connected with the second metal level 307;
Then, on the 3rd metal level 309, directly form planarization layer 310 at planarization layer 310Upper formation anode 311.
In sum, TFT backboard provided by the invention at least tool have the following advantages:
1. the present invention passes through to adopt three-layer metal, and offers hollow-out parts 312 on the second metal level 307,And offer grid via hole 313 on capacitive insulation layer 306 and insulating medium layer 308, make the 3rd metalLayer 309 can be connected with the first metal layer 305 by grid via hole 313, thereby memory capacitance is divided intoThree parts, and under limited chip area, increased the area of memory capacitance, effectively improve store electricityThe capacity holding;
2. the present invention adopts silicon oxide layer 302 or the silicon oxynitride layer 302 that Step Coverage is good to be situated between as insulationMatter layer 308, can prevent the second metal level 307 and the 3rd metal level 309 short circuits.
The above, be only preferred embodiment of the present invention, not the present invention done to any shapeRestriction in formula, although the present invention disclose as above with preferred embodiment, but not in order to limitThe present invention, any those skilled in the art, are not departing within the scope of technical solution of the present invention,When can utilizing the technology contents of above-mentioned announcement to make a little change or being modified to the equivalence of equivalent variationsEmbodiment is not depart from technical solution of the present invention content, according to technical spirit pair of the present invention in every caseAny simple modification, equivalent variations and modification that above embodiment does, all still belong to skill of the present inventionIn the scope of art scheme.
Claims (10)
1. a TFT backboard, comprises the first metal layer, is positioned at the electricity on described the first metal layerHold insulating barrier and be positioned at the second metal level on described capacitive insulation layer, it is characterized in that, described inOn the second metal level, be formed with insulating medium layer, on described insulating medium layer, be formed with the 3rd metalLayer, if described the 3rd metal level is through forming on described insulating medium layer and described capacitive insulation layerDry grid via hole contacts with described the first metal layer, is formed with for described grid on described the second metal levelSome hollow-out parts that utmost point via hole passes through.
2. TFT backboard according to claim 1, is characterized in that: described the second metalA part for layer be positioned at described the first metal layer directly over, described the 3rd metal level comprises and is positioned at instituteState Part I directly over the second metal level and through described grid via hole and described the first metalThe Part II that layer contacts.
3. TFT backboard according to claim 2, is characterized in that: described the first metalLayer, described the second metal level and be clipped in described the first metal layer and described the second metal level betweenPartition capacitance insulating barrier forms one first electric capacity, described the second metal level, described the 3rd metal levelPart I and be clipped in described the second metal level and the Part I of described the 3rd metal level betweenSI semi-insulation dielectric layer form one second electric capacity, described the second metal level, described the 3rd metal levelPart II and be clipped in the side of described the second metal level and described the 3rd metal level secondSI semi-insulation dielectric layer between part forms one the 3rd electric capacity, and the memory capacitance of described TFT comprisesDescribed the first electric capacity, described the second electric capacity and described the 3rd electric capacity.
4. TFT backboard according to claim 3, is characterized in that: described memory capacitanceArea equal the area sum of described the first electric capacity, described the second electric capacity and described the 3rd electric capacity.
5. TFT backboard according to claim 3, is characterized in that: described memory capacitanceArea equal effective projected area, described of described the first metal layer and described the second metal levelEffective projected area of the described Part I of two metal levels and described the 3rd metal level and described inEffective projected area of the described Part II of the side of the second metal level and described the 3rd metal levelSum deducts the twice of the described grid via hole gross area.
6. TFT backboard according to claim 1, is characterized in that: described TFT backboardAlso comprise substrate, be positioned at silicon nitride layer on substrate, be positioned at silicon oxide layer on silicon nitride layer, be positioned atPolysilicon layer on silicon oxide layer and be positioned at the gate insulator on polysilicon layer, described firstMetal level is formed on described gate insulator.
7. TFT backboard according to claim 1, is characterized in that: described the 3rd metalOn layer, be formed with planarization layer, on described planarization layer, be formed with anode.
8. a manufacture method for TFT backboard, is characterized in that: it comprises:
Form the first metal layer;
On described the first metal layer, form capacitive insulation layer;
On described capacitive insulation layer, form the second metal level described in the second metal level patterning,On described the second metal level, form some hollow-out parts;
On described the second metal level, form insulating medium layer;
On described insulating medium layer and described capacitive insulation layer, form some grid via holes, described gridUtmost point via hole through the described hollow-out parts of described the second metal level and described capacitive insulation layer by described absolutelyEdge dielectric layer extends to described the first metal layer;
On described insulating medium layer, form the 3rd metal level, described the 3rd metal level comprises and is positioned at instituteState the second metal level top Part I and through described grid via hole and described the first metalThe Part II that layer contacts.
9. the manufacture method of TFT backboard according to claim 8, is characterized in that: instituteState the first metal layer, described the second metal level and be clipped in described the first metal layer and described the second gold medalThe partition capacitance insulating barrier belonging between layer forms one first electric capacity, described the second metal level, described theThe Part I of three metal levels and be clipped in described the second metal level and described the 3rd metal levelSI semi-insulation dielectric layer between a part forms one second electric capacity, described the second metal level, described inThe Part II of the 3rd metal level and be clipped in side and described the 3rd gold medal of described the second metal levelSI semi-insulation dielectric layer between the Part II of genus layer forms one the 3rd electric capacity, and described TFT depositsAccumulate holds and comprises described the first electric capacity, described the second electric capacity and described the 3rd electric capacity.
10. the manufacture method of TFT backboard according to claim 9, is characterized in that: instituteThe area of stating memory capacitance equals described the first electric capacity, described the second electric capacity and described the 3rd electric capacityArea sum.
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| CN201510975536.XA CN105609508B (en) | 2015-12-22 | 2015-12-22 | TFT backplate and its manufacturing method |
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| US11532646B2 (en) * | 2020-08-05 | 2022-12-20 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Display panel, display device, and display system |
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| JP2616160B2 (en) * | 1990-06-25 | 1997-06-04 | 日本電気株式会社 | Thin film field effect transistor element array |
| CN104064688B (en) * | 2014-07-11 | 2016-09-21 | 深圳市华星光电技术有限公司 | There is manufacture method and this TFT substrate of the TFT substrate of storage electric capacity |
| CN104600078B (en) * | 2014-12-23 | 2017-08-01 | 上海中航光电子有限公司 | A kind of array base palte and its manufacture method and display panel |
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| US11532646B2 (en) * | 2020-08-05 | 2022-12-20 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Display panel, display device, and display system |
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