CN105609508B - TFT backplate and its manufacturing method - Google Patents
TFT backplate and its manufacturing method Download PDFInfo
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- CN105609508B CN105609508B CN201510975536.XA CN201510975536A CN105609508B CN 105609508 B CN105609508 B CN 105609508B CN 201510975536 A CN201510975536 A CN 201510975536A CN 105609508 B CN105609508 B CN 105609508B
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Abstract
A kind of TFT backplate, including the first metal layer, the capacitive insulating layer on the first metal layer and the second metal layer on capacitive insulating layer, insulating medium layer is formed in second metal layer, third metal layer is formed on insulating medium layer, third metal layer passes through the grid via hole formed on insulating medium layer and capacitive insulating layer and contacts with the first metal layer, and the hollow-out parts passed through for grid via hole are formed in second metal layer.TFT backplate structure of the invention is using the first metal layer and third metal layer as a pole plate of storage capacitance, using second metal layer as another pole plate of storage capacitance, and storage capacitance is divided into three parts, so as to effectively increase the area of storage capacitance under limited chip area.The present invention also provides the manufacturing methods of above-mentioned TFT backplate.
Description
Technical field
The present invention relates to field of display technology more particularly to a kind of TFT backplates and its manufacturing method.
Background technique
Glass substrate is generally comprised in the pixel circuit storage capacitor construction of plane display field, TFT backplate, is directly formed
In the polysilicon layer (p-Si layers) on glass substrate, the gate insulating layer (GI being formed directly on glass substrate and polysilicon layer
Layer, Gate Insulation Layer), it is formed directly into the first metal on gate insulating layer and being located above polysilicon layer
Layer, be formed directly on gate insulating layer and the first metal layer capacitive insulating layer (CI layers, Capacitance Insulation
Layer), it is formed directly into the second metal layer on capacitive insulating layer and being located above the first metal layer, wherein the first metal layer
As the grid of driving TFT, while also as a pole plate of storage capacitance, second metal layer as storage capacitance another
Pole plate, the first metal layer, second metal layer and the partition capacitance insulating layer shape being clipped between the first metal layer and second metal layer
At storage capacitance.
The storage capacitance of pixel circuit during the work time can storage driving TFT grid potential, as display screen is differentiated
The raising of rate, required capacitance are also increasing.In current pixel circuit storage capacitor construction, respectively with first
Two pole plates of metal layer and second metal layer as capacitor will be obtained since two pole plates of capacitor are planar structure
Biggish capacitance just needs very big chip area, and the increase of capacity area will cause under display device aperture opening ratio
Drop, influences display effect.
Summary of the invention
In view of this, the present invention provides one kind can effectively increase storage capacitance capacity under limited chip area
TFT backplate and its manufacturing method.
TFT backplate provided by the invention include the first metal layer, the capacitive insulating layer on the first metal layer with
And the second metal layer on the capacitive insulating layer, insulating medium layer, the insulation are formed in the second metal layer
Third metal layer is formed on dielectric layer, the third metal layer passes through shape on the insulating medium layer and the capacitive insulating layer
At several grid via holes contacted with the first metal layer, be formed in the second metal layer and pass through for the grid via hole
Several hollow-out parts.
According to one embodiment of present invention, a part of the second metal layer be located at the first metal layer just on
Side, the third metal layer include positioned at the second metal layer surface first part and pass through the grid via hole with
The second part that the first metal layer is in contact.
According to one embodiment of present invention, the first metal layer, the second metal layer and it is clipped in described first
Partition capacitance insulating layer between metal layer and the second metal layer forms a first capacitor, the second metal layer, described
The first part of third metal layer and the portion being clipped between the second metal layer and the first part of the third metal layer
Point insulating medium layer forms one second capacitor, the second metal layer, the third metal layer second part and be clipped in institute
It states the SI semi-insulation dielectric layer between the side of second metal layer and the second part of the third metal layer and forms third electricity
Hold, the storage capacitance of the TFT includes the first capacitor, second capacitor and the third capacitor.
According to one embodiment of present invention, the area of the storage capacitance is equal to the first capacitor, second electricity
The sum of the area of appearance and the third capacitor.
According to one embodiment of present invention, the area of the storage capacitance is equal to the first metal layer and described second
Effective perspective plane of the first part of effective projected area of metal layer, the second metal layer and the third metal layer
The sum of the side of the long-pending and described second metal layer and effective projected area of the second part of the third metal layer subtract
Twice for removing the grid via hole gross area.
According to one embodiment of present invention, the TFT backplate further include substrate, on substrate silicon nitride layer, be located at
Silicon oxide layer on silicon nitride layer, the polysilicon layer on silicon oxide layer and the gate insulating layer on polysilicon layer,
The first metal layer is formed on the gate insulating layer.
According to one embodiment of present invention, planarization layer is formed on the third metal layer, on the planarization layer
It is formed with anode.
The manufacturing method of TFT backplate provided by the invention, comprising: form the first metal layer；On the first metal layer
Form capacitive insulating layer；Second metal layer is formed on the capacitive insulating layer and patterns the second metal layer, described
Several hollow-out parts are formed in second metal layer；Insulating medium layer is formed in the second metal layer；In the insulating medium layer
With form several grid via holes on the capacitive insulating layer, the grid via hole passes through the hollow-out parts of the second metal layer
The first metal layer is extended to by the insulating medium layer with the capacitive insulating layer；Is formed on the insulating medium layer
Three metal layers, the third metal layer include positioned at the first part of the top of the second metal layer and across the grid mistake
The second part that hole is in contact with the first metal layer.
According to one embodiment of present invention, the first metal layer, the second metal layer and it is clipped in described first
Partition capacitance insulating layer between metal layer and the second metal layer forms a first capacitor, the second metal layer, described
The first part of third metal layer and the portion being clipped between the second metal layer and the first part of the third metal layer
Point insulating medium layer forms one second capacitor, the second metal layer, the third metal layer second part and be clipped in institute
It states the SI semi-insulation dielectric layer between the side of second metal layer and the second part of the third metal layer and forms third electricity
Hold, the storage capacitance of the TFT includes the first capacitor, second capacitor and the third capacitor.
According to one embodiment of present invention, the area of the storage capacitance is equal to the first capacitor, second electricity
The sum of the area of appearance and the third capacitor.
The present invention opens up hollow-out parts by using three-layer metal in second metal layer, and in capacitive insulating layer and
Grid via hole is opened up on insulating medium layer, third metal layer is allow to be connected by grid via hole with the first metal layer, thus will
Storage capacitance is divided into three parts, and the area of storage capacitance is increased under limited chip area, effectively increases storage electricity
The capacity of appearance.
The above description is only an overview of the technical scheme of the present invention, in order to better understand the technical means of the present invention,
And it can be implemented in accordance with the contents of the specification, and in order to allow above and other objects, features and advantages of the invention can
It is clearer and more comprehensible, it is special below to lift preferred embodiment, and cooperate attached drawing, detailed description are as follows.
Detailed description of the invention
Fig. 1 show the schematic cross-sectional view of TFT backplate of the present invention；
Fig. 2 is the first metal layer of TFT backplate shown in Fig. 1 and the surface plate of film layer illustrates intention below, due to nitridation
Silicon layer, silicon oxide layer and gate insulating layer are transparent material layer, therefore, can be only seen in figure substrate, polysilicon layer and
The first metal layer；
Fig. 3 is the insulating medium layer of TFT backplate shown in Fig. 1 and the surface plate of film layer illustrates intention below, due to capacitor
Insulating layer and insulating medium layer are transparent material layer, and therefore, two kinds of insulating layers are invisible in figure, but are said for convenience
Bright, the aperture in two kinds of insulating layers still has in figure shown；
Fig. 4 is that the surface plate of the third metal layer of TFT backplate shown in Fig. 1 illustrates intention, for ease of description third metal
Grid via hole, polysilicon connecting hole and VDD connecting hole is also shown in figure in the corresponding relationship of layer and film layer below；
Wherein, 300- substrate, 301- silicon nitride layer, 302- silicon oxide layer, 303- polysilicon layer, 304- gate insulating layer,
305- the first metal layer, 306- capacitive insulating layer, 307- second metal layer, 308- insulating medium layer, 309- third metal layer,
310- planarization layer, 311- anode, 312- hollow-out parts, 313- grid via hole, 314- polysilicon connecting hole, 315-VDD connecting hole,
C1- first capacitor, the second capacitor of C2-, C3- third capacitor.
Specific embodiment
It is of the invention to reach the technical means and efficacy that predetermined goal of the invention is taken further to illustrate, below in conjunction with
Attached drawing and preferred embodiment, the present invention is described in detail as follows.
Fig. 1 show the schematic cross-sectional view of TFT backplate of the present invention.As shown in Figure 1, TFT backplate of the invention is from bottom to top
Include: substrate 300, the silicon nitride layer 301 on substrate 300, the silicon oxide layer 302 on silicon nitride layer 301, be located at oxygen
Polysilicon layer 303 on SiClx layer 302, the gate insulating layer 304 on polysilicon layer 303 (GI layers, Gate
Insulation Layer), the first metal layer 305 on gate insulating layer 304, the electricity on the first metal layer 305
Hold insulating layer 306 (CI layers, Capacitance Insulation Layer), the second metal on capacitive insulating layer 306
Layer 307, the insulating medium layer 308 (ILD layer, Insulation Dielectric Layer) in second metal layer 307,
Third metal layer 309 on insulating medium layer 308, the planarization layer 310 on third metal layer 309 and it is located at
Anode 311 on planarization layer 310.
Wherein, substrate 300 can be glass substrate, metal substrate or polymeric substrates, and the present invention is preferably glass substrate.
Metal molybdenum can be used in the first metal layer 305.Silica or silicon oxynitride can be used in capacitive insulating layer 306.Insulating medium layer 308 can
Using step coverage good silica or silicon oxynitride, same material can be used with capacitive insulating layer 306.Second gold medal
Same material can be used with the first metal layer 305 by belonging to layer 307.Third metal layer 309 uses titanium-aluminium alloy, the knot used
Structure is titanium/aluminium/titanium structure, i.e., third metal layer 309 is by two layers of titanium coating and the aluminium gold being clipped between two layers of titanium coating
Belong to layer composition.
Grid of the first metal layer 305 as driving TFT, and the first pole plate as storage capacitance.Second metal layer 307
A part be located at the surface of the first metal layer 305, the second pole plate as storage capacitance.Through scheming in second metal layer 307
Case is formed with several hollow-out parts 312, these hollow-out parts 312 are the grid formed on capacitive insulating layer 306 and insulating medium layer 308
Via hole 313 reserved empty position in pole allows grid via hole 313 to pass through second by the insulating medium layer 308 of 307 top of second metal layer
Metal layer 307 and the capacitive insulating layer 306 for reaching the lower section of second metal layer 307.Third metal layer 309 as storage capacitance
Tri-electrode comprising the first part right above second metal layer 307, and pass through grid via hole 313 and with the first gold medal
Belong to layer 305 to be in contact second part.In this manner, so that finally formed storage capacitance is with the first metal layer 305 and
Three metal layers 309 are used as a capacitor plate, using second metal layer 307 as another capacitor plate, in this way, to be formed
Storage capacitance includes first capacitor C1, the second capacitor C2 and tri- parts third capacitor C3, wherein first capacitor C1 is by the first gold medal
Belong to layer 305, second metal layer 307 and the partition capacitance insulating layer being clipped between the first metal layer 305 and second metal layer 307
306 formed, the second capacitor C2 by second metal layer 307, third metal layer 309 first part and be clipped in second metal layer
The formation of SI semi-insulation dielectric layer 308 between 307 and the first part of third metal layer 309, third capacitor C3 is by the second metal
Layer 307, the second part of third metal layer 309 and be clipped in second metal layer 307 side and third metal layer 309 second
Between part SI semi-insulation dielectric layer 308 formation, in conjunction with background technique and it can be seen that, general TFT pixel circuit
Storage capacitance area and first capacitor C1 area equation, therefore, the area of the storage capacitance that the present invention is formed is greater than one
As TFT pixel circuit storage capacitance area.The area for the storage capacitance that the present invention is formed is first capacitor C1, the second capacitor
The sum of the area of C2 and third capacitor C3, the area of the storage capacitance can also be calculated by the following formula to obtain:
S=S1+S2+S3-2*n*SHole；
Wherein, S is the area of storage capacitance, and S1 is effective perspective plane of the first metal layer 305 and second metal layer 307
Product, S2 are effective projected area of the first part of second metal layer 307 and third metal layer 309, and S3 is second metal layer 307
Side and third metal layer 309 second part effective projected area, n be grid via hole 313 quantity, SHoleFor grid mistake
The area in hole 313, n*SHoleFor the gross area of grid via hole 313.Effective projected area is one in two opposite metal layers
Projection and the area of the overlapping part of another metal layer on another, for example, the first metal layer 305 and second metal layer
307 effective projected area is the overlapping of projection of the first metal layer 305 in second metal layer 307 and second metal layer 307
Partial area.
Further, the manufacturing method of TFT backplate provided by the invention, comprising:
Firstly, forming the film layer of 305 lower section of the first metal layer according to the technique of general TFT backplate, including on the substrate 300
It directly forms silicon nitride layer 301, directly form silicon oxide layer 302, the direct shape on silicon oxide layer 302 on silicon nitride layer 301
At polysilicon layer 303, and gate insulating layer 304 is directly formed on polysilicon layer 303；
Then, the first metal layer 305 is directly formed on gate insulating layer 304 and is formed by exposure etching such as Fig. 2 institute
The figure shown, the first metal layer 305 deposit to be formed using metal molybdenum, and the rectangle part of the first metal layer 305 is as driving TFT's
First pole plate of grid and storage capacitance；
Then, capacitive insulating layer 306 is directly formed on the first metal layer 305；
Then, second metal layer 307 is directly formed on capacitive insulating layer 306 and by exposure etching pattern chemical conversion as schemed
The material of figure shown in 3, second metal layer 307 can be same material with the first metal layer 305, as storage capacitance
Second pole plate, while a part of the cabling as connection VDD, are formed with rectangle after patterning in second metal layer 307
Hollow-out parts 312, the area of hollow-out parts 312 are greater than the area of grid via hole 313；
Then, insulating medium layer 308, a part covering of insulating medium layer 308 are directly formed in second metal layer 307
In in second metal layer 307, another part is filled in the hollow-out parts 312 of second metal layer 307；
Then, grid via hole 313 and more is formed on insulating medium layer 308 and capacitive insulating layer 306 by exposure etching
Crystal silicon connecting hole 314, and VDD connecting hole 315 is formed on insulating medium layer 308, wherein grid via hole 313 passes through the second metal
Hollow-out parts 312 and the capacitive insulating layer 306 of layer 307 and the first metal layer 305 is extended to by insulating medium layer 308, polysilicon connects
It connects hole 314 and polysilicon layer 303, VDD is extended to by insulating medium layer 308 across insulating medium layer 308 and capacitive insulating layer 306
Connecting hole 315 extends to second metal layer 307 by insulating medium layer 308；
Then, third metal layer 309 is directly formed on insulating medium layer 308 and is formed by exposure etching such as Fig. 4 institute
The figure shown, third metal layer 309 use titanium/aluminium/titanium structure, and the first part of third metal layer 309 is located at second metal layer
The second part of 307 top, third metal layer 309 passes through grid via hole 313 and is in contact with the first metal layer 305, third
Write line of the part (i.e. first part and second part) that metal layer 309 is connect with grid as grid potential, and as depositing
The third pole plate that storage is held is connected with the first pole plate, in addition, third metal layer 309 further includes being located in polysilicon connecting hole 314
And the part being connected with polysilicon layer 303 and the part being connected in VDD connecting hole 315 with second metal layer 307；
Then, planarization layer 310 is directly formed on third metal layer 309 and forms anode on planarization layer 310
311。
In conclusion TFT backplate provided by the invention at least has the advantages that
1. the present invention opens up hollow-out parts 312, and in capacitor by using three-layer metal in second metal layer 307
Grid via hole 313 is opened up on insulating layer 306 and insulating medium layer 308, third metal layer 309 is allow to pass through grid via hole 313
It is connected with the first metal layer 305, so that storage capacitance is divided into three parts, and increases storage electricity under limited chip area
The area of appearance effectively increases the capacity of storage capacitance；
2. the present invention is used as insulating medium layer 308 using the good silicon oxide layer 302 of Step Coverage or silicon oxynitride layer 302,
It can prevent 309 short circuit of second metal layer 307 and third metal layer.
The above described is only a preferred embodiment of the present invention, be not intended to limit the present invention in any form, though
So the present invention has been disclosed as a preferred embodiment, and however, it is not intended to limit the invention, any technology people for being familiar with this profession
Member, without departing from the scope of the present invention, when the technology contents using the disclosure above make a little change or modification
It is right according to the technical essence of the invention for the equivalent embodiment of equivalent variations, but without departing from the technical solutions of the present invention
Any simple modification, equivalent change and modification made by above embodiments, all of which are still within the scope of the technical scheme of the invention.
Claims (7)
1. a kind of TFT backplate including the first metal layer, the capacitive insulating layer on the first metal layer and is located at described
Second metal layer on capacitive insulating layer, which is characterized in that insulating medium layer, the insulation are formed in the second metal layer
Third metal layer is formed on dielectric layer, the first metal layer includes the rectangle part as TFT gate, second metal
A part of layer is located at the surface of the rectangle part of the first metal layer；The third metal layer passes through the insulation
Several grid via holes formed on dielectric layer and the capacitive insulating layer are contacted with the first metal layer, the second metal layer
The part right above the rectangle part of the first metal layer be formed with for the grid via hole pass through it is several
Hollow-out parts；A part of the second metal layer is located at the surface of the first metal layer, and the third metal layer includes position
First part right above the second metal layer and be in contact across the grid via hole with the first metal layer
Two parts；The first metal layer, the second metal layer and be clipped in the first metal layer and the second metal layer it
Between partition capacitance insulating layer formed a first capacitor, the second metal layer, the third metal layer first part and
The SI semi-insulation dielectric layer being clipped between the second metal layer and the first part of the third metal layer forms one second electricity
Hold, the second metal layer, the third metal layer second part and be clipped in the side of the second metal layer and described
SI semi-insulation dielectric layer between the second part of third metal layer forms a third capacitor, and the storage capacitance of the TFT includes
The first capacitor, second capacitor and the third capacitor.
2. TFT backplate according to claim 1, it is characterised in that: the area of the storage capacitance is equal to first electricity
The sum of appearance, second capacitor and area of the third capacitor.
3. TFT backplate according to claim 1, it is characterised in that: the area of the storage capacitance is equal to first gold medal
Belong to described first of effective projected area of layer and the second metal layer, the second metal layer and the third metal layer
The side of the effective projected area and the second metal layer divided is effective with the second part of the third metal layer
The sum of projected area subtracts twice of the grid via hole gross area.
4. TFT backplate according to claim 1, it is characterised in that: the TFT backplate further includes substrate, is located on substrate
Silicon nitride layer, the silicon oxide layer on silicon nitride layer, the polysilicon layer on silicon oxide layer and be located at polysilicon layer on
Gate insulating layer, the first metal layer is formed on the gate insulating layer.
5. TFT backplate according to claim 1, it is characterised in that: be formed with planarization layer on the third metal layer, institute
It states and is formed with anode on planarization layer.
6. a kind of manufacturing method of TFT backplate, it is characterised in that: comprising:
The first metal layer is formed, the first metal layer includes the rectangle part as TFT gate；
Capacitive insulating layer is formed on the first metal layer；
Second metal layer is formed on the capacitive insulating layer and patterns the second metal layer, in the second metal layer
Part above the rectangle part forms several hollow-out parts；
Insulating medium layer is formed in the second metal layer；
Form several grid via holes on the insulating medium layer and the capacitive insulating layer, the grid via hole passes through described the
The hollow-out parts of two metal layers and the capacitive insulating layer extend to the first metal layer by the insulating medium layer；
Third metal layer is formed on the insulating medium layer, the third metal layer includes positioned at the upper of the second metal layer
The first part of side and the second part being in contact across the grid via hole with the first metal layer；
Wherein, the first metal layer, the second metal layer and the first metal layer and the second metal layer are clipped in
Between partition capacitance insulating layer formed a first capacitor, the second metal layer, the third metal layer first part with
And the SI semi-insulation dielectric layer being clipped between the second metal layer and the first part of the third metal layer forms one second
Capacitor, the second metal layer, the third metal layer second part and be clipped in side and the institute of the second metal layer
The SI semi-insulation dielectric layer stated between the second part of third metal layer forms a third capacitor, the storage capacitance packet of the TFT
Include the first capacitor, second capacitor and the third capacitor.
7. the manufacturing method of TFT backplate according to claim 6, it is characterised in that: the area of the storage capacitance is equal to
The sum of the first capacitor, second capacitor and area of the third capacitor.
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| CN105609508B true CN105609508B (en) | 2019-04-05 |
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| US11532646B2 (en) * | 2020-08-05 | 2022-12-20 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Display panel, display device, and display system |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5182661A (en) * | 1990-06-25 | 1993-01-26 | Nec Corporation | Thin film field effect transistor array for use in active matrix liquid crystal display |
| CN104064688A (en) * | 2014-07-11 | 2014-09-24 | 深圳市华星光电技术有限公司 | Method for manufacturing TFT substrate with storage capacitors and TFT substrate |
| CN104600078A (en) * | 2014-12-23 | 2015-05-06 | 上海中航光电子有限公司 | Array substrate and manufacturing method thereof, and display panel |
-
2015
- 2015-12-22 CN CN201510975536.XA patent/CN105609508B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5182661A (en) * | 1990-06-25 | 1993-01-26 | Nec Corporation | Thin film field effect transistor array for use in active matrix liquid crystal display |
| CN104064688A (en) * | 2014-07-11 | 2014-09-24 | 深圳市华星光电技术有限公司 | Method for manufacturing TFT substrate with storage capacitors and TFT substrate |
| CN104600078A (en) * | 2014-12-23 | 2015-05-06 | 上海中航光电子有限公司 | Array substrate and manufacturing method thereof, and display panel |
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