CN107611163B - O L ED display substrate, manufacturing method thereof and display device - Google Patents
O L ED display substrate, manufacturing method thereof and display device Download PDFInfo
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- CN107611163B CN107611163B CN201710859381.2A CN201710859381A CN107611163B CN 107611163 B CN107611163 B CN 107611163B CN 201710859381 A CN201710859381 A CN 201710859381A CN 107611163 B CN107611163 B CN 107611163B
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Abstract
The O L ED display substrate comprises a substrate, and a light shielding layer pattern, a first insulating layer, a semiconductor layer pattern, a second insulating layer and a source drain metal layer pattern which are sequentially arranged on the substrate, wherein the light shielding layer pattern is made of a conductive material, and the semiconductor layer pattern is directly connected with the light shielding layer pattern through a through hole in the first insulating layer.
Description
Technical Field
The invention relates to the technical field of display, in particular to an O L ED (organic light emitting diode) display substrate, a manufacturing method thereof and a display device.
Background
Referring to fig. 1, a conventional O L ED adopts a driving method of 2T1C (two thin film transistors and a capacitor), wherein one of the driving thin film transistors T1, one of the switching thin film transistors T2 and one of the storage capacitors Cst, when an effective signal (Switch Scan) is inputted to a Scan line, the switching thin film transistor T2 is turned on to store a data voltage signal data to the storage capacitor Cst, and a voltage signal stored in the storage capacitor Cst controls the driving thin film transistor T1 to be turned on, so that the inputted data voltage signal data is converted into a current signal required by the O L ED to emit light to control the O L ED to display different gray scales.
In the Top Gate (Top Gate) technology, in order to avoid interference of an Active layer (Active) graph of a thin film transistor by light, a shield layer graph (shield layer) can be manufactured between the Active layer graph and a substrate, the shield layer graph is usually made of metal materials, and after the Active layer graph is electrified, parasitic capacitance can be generated between the Active layer graph and the shield layer graph.
Referring to fig. 2, in the prior art, the active layer pattern 104 can be connected to the light shielding layer pattern 102 only by the transition of the source/drain metal layer pattern 106, at this time, the source/drain metal layer pattern 106 and the active layer pattern 104 are connected through the via hole 110 on the second insulating layer 105, and then the source/drain metal layer pattern 106 is connected to the light shielding layer pattern 102 through the via hole 109 penetrating through the first insulating layer 103 and the second insulating layer 105, that is, in the prior art, the connection between the light shielding layer pattern 102 and the active layer pattern 104 can be completed by two via holes, and the number of via holes is large, which inevitably reduces the pixel aperture ratio.
Disclosure of Invention
In view of this, the present invention provides an O L ED display substrate, a method for manufacturing the same, and a display device, which are used to reduce the number of vias on the O L ED display substrate and improve the pixel aperture ratio.
In order to solve the technical problem, the invention provides an O L ED display substrate, which comprises a substrate, and a light shielding layer pattern, a first insulating layer, a semiconductor layer pattern, a second insulating layer and a source drain metal layer pattern which are sequentially arranged on the substrate, wherein the light shielding layer pattern is made of a conductive material, and the semiconductor layer pattern is directly connected with the light shielding layer pattern through a through hole on the first insulating layer.
Preferably, the light shield layer pattern comprises a first light shield layer pattern, the semiconductor layer pattern comprises a first semiconductor layer pattern, the source drain metal layer pattern comprises a first source drain metal layer pattern, the via hole on the first insulating layer comprises a first via hole, the O L ED display substrate further comprises a third insulating layer and an anode pattern which are sequentially arranged on the source drain metal layer pattern, the first light shield layer pattern, the first insulating layer, the first semiconductor layer pattern, the second insulating layer, the first source drain metal layer pattern, the third insulating layer and the anode pattern form a storage capacitor, the first semiconductor layer pattern is directly connected with the first light shield layer pattern through the first via hole on the first insulating layer, the anode pattern is connected with the first semiconductor layer pattern through a second via hole penetrating through the second insulating layer and the third insulating layer, the orthographic projection of the second via hole on the substrate is completely located in the orthographic projection area of the first via hole on the substrate, the first source drain metal layer pattern is used as a first electrode of the storage capacitor, and the first light shield layer pattern, the first semiconductor layer pattern and the anode pattern are connected as a second electrode of the storage capacitor.
Preferably, the second via hole is formed by communicating a third via hole on the second insulating layer with a fourth via hole on the third insulating layer, and the source-drain metal layer pattern further includes: and the second source drain metal layer graph is connected with the first semiconductor layer graph through a third via hole on the second insulating layer, and the anode graph is connected with the second source drain metal layer graph through a fourth via hole.
Preferably, the semiconductor layer pattern further includes a first active layer pattern for driving the thin film transistor, the source-drain metal layer pattern further includes a first source electrode pattern and a first drain electrode pattern for driving the thin film transistor, the first drain electrode pattern is connected with the second source-drain metal layer pattern, the first active layer pattern is connected with the first semiconductor layer pattern, and the first active layer pattern is connected with the first drain electrode pattern by means of the first semiconductor layer pattern and the second source-drain metal layer pattern.
Preferably, the semiconductor layer pattern further includes a second active layer pattern of the touch thin film transistor, the source-drain metal layer pattern further comprises a second source electrode pattern and a second drain electrode pattern of the touch thin film transistor, the light shielding layer pattern further comprises a second light shielding layer pattern, the via hole of the first insulating layer further comprises a fifth via hole, wherein the second light shielding layer pattern is connected with the second source electrode pattern of the touch thin film transistor, the second active layer pattern is directly connected with the second light shielding layer pattern through a fifth via hole on the first insulating layer, the second source pattern is connected to the second active layer pattern through a sixth via hole penetrating the second insulating layer, and the orthographic projection of the sixth via hole on the substrate base plate is positioned in the orthographic projection area of the fifth via hole on the substrate base plate.
Preferably, the second active layer pattern is connected to the first semiconductor layer pattern, the second drain electrode pattern is connected to the second source drain metal layer pattern, and the second active layer pattern is connected to the second drain electrode pattern by the first semiconductor layer pattern and the second source drain metal layer pattern.
The invention also provides a manufacturing method of the O L ED display substrate, which comprises the following steps:
providing a substrate base plate;
a shading layer pattern, a first insulating layer, a semiconductor layer pattern, a second insulating layer and a source drain metal layer pattern are sequentially formed on the substrate, the shading layer pattern is made of a conductive material, and the semiconductor layer pattern is directly connected with the shading layer pattern through a through hole in the first insulating layer.
Preferably, the light shielding layer pattern comprises a first light shielding layer pattern, the semiconductor layer pattern comprises a first semiconductor layer pattern, the source-drain metal layer pattern comprises a first source-drain metal layer pattern, and the via hole on the first insulating layer comprises a first via hole; the manufacturing method further comprises the following steps:
a third insulating layer and an anode pattern are sequentially formed on the source-drain metal layer pattern, the first shading layer pattern, the first insulating layer, the first semiconductor layer pattern, the second insulating layer, the first source-drain metal layer pattern, the third insulating layer and the anode pattern form a storage capacitor, the first semiconductor layer pattern is directly connected with the first light shielding layer pattern through a first via hole on the first insulating layer, the anode pattern is connected to the first semiconductor layer pattern through a second via hole penetrating the second and third insulating layers, the orthographic projection of the second via hole on the substrate base plate is completely positioned in the orthographic projection area of the first via hole on the substrate base plate, the first source drain metal layer pattern is used as a first electrode of the storage capacitor, and the first shading layer pattern, the first semiconductor layer pattern and the anode pattern are connected to be used as a second electrode of the storage capacitor.
Preferably, the second via hole is formed by communicating a third via hole on the second insulating layer with a fourth via hole on the third insulating layer, and the source-drain metal layer pattern further includes: and the second source drain metal layer graph is connected with the first semiconductor layer graph through a third via hole on the second insulating layer, and the anode graph is connected with the second source drain metal layer graph through a fourth via hole.
Preferably, the semiconductor layer pattern further includes a first active layer pattern for driving the thin film transistor, the source-drain metal layer pattern further includes a first source electrode pattern and a first drain electrode pattern for driving the thin film transistor, the first drain electrode pattern is connected with the second source-drain metal layer pattern, the first active layer pattern is connected with the first semiconductor layer pattern, and the first active layer pattern is connected with the first drain electrode pattern by means of the first semiconductor layer pattern and the second source-drain metal layer pattern.
Preferably, the semiconductor layer pattern further includes a second active layer pattern of the touch thin film transistor, the source-drain metal layer pattern further comprises a second source electrode pattern and a second drain electrode pattern of the touch thin film transistor, the light shielding layer pattern further comprises a second light shielding layer pattern, the via hole of the first insulating layer further comprises a fifth via hole, wherein the second light shielding layer pattern is connected with the second source electrode pattern of the touch thin film transistor, the second active layer pattern is directly connected with the second light shielding layer pattern through a fifth via hole on the first insulating layer, the second source pattern is connected to the second active layer pattern through a sixth via hole penetrating the second insulating layer, and the orthographic projection of the sixth via hole on the substrate base plate is positioned in the orthographic projection area of the fifth via hole on the substrate base plate.
Preferably, the second active layer pattern is connected to the first semiconductor layer pattern, the second drain electrode pattern is connected to the second source drain metal layer pattern, and the second active layer pattern is connected to the second drain electrode pattern by the first semiconductor layer pattern and the second source drain metal layer pattern.
The invention also provides a display device which comprises the O L ED display substrate.
The technical scheme of the invention has the following beneficial effects:
the light-shielding layer pattern and the semiconductor layer pattern are directly connected, and thus no parasitic capacitance is generated therebetween. In addition, the light shielding layer pattern is directly connected with the semiconductor layer pattern, and switching of the source drain metal layer pattern and the drain source metal layer pattern is not needed.
Drawings
FIG. 1 is a schematic diagram of a driving circuit on an O L ED display substrate;
FIG. 2 is a schematic diagram of a conventional O L ED display substrate;
FIG. 3 is a schematic view of an O L ED display substrate according to one embodiment of the present invention;
FIG. 4 is a schematic diagram of a storage capacitor according to an embodiment of the present invention;
FIG. 5 is a schematic view of an O L ED display substrate according to another embodiment of the present invention;
FIG. 6 is a schematic diagram of another driving circuit on an O L ED display substrate;
FIGS. 7-13 are schematic diagrams illustrating a method for fabricating an O L ED display substrate according to an embodiment of the invention;
description of reference numerals:
FIG. 2:
101 a substrate base plate; 102 a light shielding layer pattern;
103 a first insulating layer; 104 active layer pattern;
105 a second insulating layer; 106 source drain metal layer patterns;
107 a third insulating layer; 108 an anode pattern;
109 a via hole; a 110 via hole;
111 via holes;
FIGS. 3 to 13:
201 a substrate base plate; 202 a first light shielding layer pattern;
203 a first insulating layer; 2041 a first semiconductor layer pattern;
205 a second insulating layer; 2061 a first source/drain metal layer pattern;
207 a third insulating layer; 208 an anode pattern;
209 a first via; 210 a second via;
2062 a second source drain metal layer pattern.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention, are within the scope of the invention.
In order to solve the problems of large number of via holes and low pixel aperture ratio of the conventional O L ED display substrate, the embodiment of the invention provides an O L ED display substrate, which comprises a substrate, and a light shielding layer pattern, a first insulating layer, a semiconductor layer pattern, a second insulating layer and a source drain metal layer pattern which are sequentially arranged on the substrate, wherein the light shielding layer pattern is made of a conductive material, and the semiconductor layer pattern is directly connected with the light shielding layer pattern through the via holes in the first insulating layer.
In the embodiment of the invention, the light shielding layer pattern and the semiconductor layer pattern are directly connected, so that parasitic capacitance cannot be generated between the light shielding layer pattern and the semiconductor layer pattern. In addition, the light shielding layer pattern is directly connected with the semiconductor layer pattern, and switching of the source drain metal layer pattern and the drain source metal layer pattern is not needed.
The O L ED display substrate in the embodiment of the invention comprises a driving circuit and an O L ED driven by the driving circuit, wherein the driving circuit has a structure shown in fig. 1 and comprises a switching thin film transistor T2, a driving thin film transistor T1 and a storage capacitor Cst.
In the embodiment of the invention, in order to improve the storage capacity of the storage capacitor, the light shielding layer pattern, the semiconductor layer pattern, the source and drain metal layer pattern and the anode pattern can be used as electrode plates of the storage capacitor.
Therefore, in the embodiment of the present invention, preferably, the light shielding layer pattern includes a first light shielding layer pattern, the semiconductor layer pattern includes a first semiconductor layer pattern, the source drain metal layer pattern includes a first source drain metal layer pattern, the via hole on the first insulating layer includes a first via hole, the O L ED display substrate further includes a third insulating layer and an anode pattern sequentially disposed on the source drain metal layer pattern, the first light shielding layer pattern, the first insulating layer, the first semiconductor layer pattern, the second insulating layer, the first source drain metal layer pattern, the third insulating layer and the anode pattern form a storage capacitor, the first semiconductor layer pattern is directly connected with the first light shielding layer pattern through the first via hole on the first insulating layer, the anode pattern is connected with the first semiconductor layer pattern through a second via hole penetrating through the second insulating layer and the third insulating layer, an orthographic projection of the second via hole on the substrate is completely located in an orthographic projection area of the first via hole on the substrate, the first light shielding layer pattern serves as a first electrode of the storage capacitor, and the first light shielding layer pattern, the first semiconductor layer pattern, the second semiconductor layer pattern and the anode pattern serve as a second storage capacitor connecting electrode of the storage capacitor.
In the embodiment of the invention, the storage capacitor comprises the first shading layer pattern, the first semiconductor layer pattern, the first source drain metal layer pattern and the anode pattern which are arranged in a superposition mode, namely the storage capacitor comprises four layers of electrode plates, so that the storage capacitor is large. Meanwhile, the first light shielding layer pattern is connected with the first semiconductor layer pattern, so that parasitic capacitance cannot be generated between the first light shielding layer pattern and the first semiconductor layer pattern. In addition, the first via hole and the second via hole for connecting the first light shielding layer pattern, the first semiconductor layer pattern and the anode pattern are overlapped in position, and thus may be regarded as one via hole, that is, the first light shielding layer pattern, the first semiconductor layer pattern and the anode pattern may be connected by one via hole side, whereas, in the prior art, referring to fig. 2, the light shielding layer pattern 102, the active layer pattern 104 and the anode pattern 108 have to pass through two via holes if necessary for connection (wherein, the via hole 110 and the via hole 111 may be regarded as one via hole). In the embodiment of the invention, the number of the through holes is reduced, so that the occupied area of the through holes is reduced, and the aperture opening ratio of the pixel is improved.
In an embodiment of the invention, the first insulating layer may be a buffer layer, and silicon dioxide (SiO) may be used2) The manufacturing method is, of course, not excluded from adopting other materials. The second insulating layer may be an interlayer dielectric layer, or may be made of silicon dioxide, although other materials are not excluded. The third insulating layer may be a passivation layer or a planarization layer.
Referring to fig. 3 and fig. 4, an embodiment of the present invention provides an O L ED display substrate, including a substrate 201 and a storage capacitor disposed on the substrate 201, where the storage capacitor includes a first light shielding layer pattern 202, a first insulating layer 203, a first semiconductor layer pattern 2041, a second insulating layer 205, a first source-drain metal layer pattern 2061, a third insulating layer 207, and an anode pattern 208, the first light shielding layer pattern 202 is made of a conductive material, the first semiconductor layer pattern 2041 is directly connected to the first light shielding layer pattern 202 through a first via hole 209 on the first insulating layer 203, the anode pattern 208 is connected to the first semiconductor layer pattern 2041 through a second via hole 210 penetrating through the second insulating layer 205 and the third insulating layer 207, an orthographic projection of the second via hole 210 on the substrate 201 is completely located in an orthographic projection area of the first via hole 209 on the substrate 201 (that the first via hole 209 is superposed with the second via hole 210, and may be regarded as a via hole), the first source-drain metal layer pattern 1 is used as a first storage capacitor electrode 202 and is connected to the first storage capacitor electrode 202.
In the embodiment of the present invention, the storage capacitor includes the first light shielding layer pattern 202, the first semiconductor layer pattern 2041, the first source-drain metal layer pattern 2061, and the anode pattern 208, which are stacked, that is, includes four electrode plates, so that the storage capacitor is relatively large. Meanwhile, the first light-shielding layer pattern 202 is connected to the first semiconductor layer pattern 2041, and thus no parasitic capacitance is generated therebetween. In addition, the first via hole 209 and the second via hole 210 for connecting the first light shielding layer pattern 202, the first semiconductor layer pattern 2041 and the anode pattern 208 are overlapped in position, so that the first light shielding layer pattern 202, the first semiconductor layer pattern 2041 and the anode pattern 208 can be regarded as one via hole, that is, the first light shielding layer pattern 202, the first semiconductor layer pattern 2041 and the anode pattern 208 can be connected through one via hole edge, the number of the via holes is reduced, the occupied area of the via holes is reduced, and the aperture opening ratio of pixels is improved.
Referring to fig. 5, fig. 5 is a schematic structural diagram of an O L ED display substrate according to another embodiment of the present invention, and the difference between the embodiment of the present invention and the embodiment shown in fig. 3 is that the source-drain metal layer pattern further includes a second source-drain metal layer pattern 2062, the second source-drain metal layer pattern 2062 is not connected to the first source-drain metal layer pattern 2061, as can be seen from fig. 3 and 5, the second via hole 210 is formed by communicating a third via hole on the second insulating layer 205 with a fourth via hole on the third insulating layer 207, the second source-drain metal layer pattern 2062 is connected to the first semiconductor layer pattern 2041 through the third via hole, and the anode pattern 208 is connected to the second source-drain metal layer pattern 2062 through the fourth via hole.
In the embodiment of the present invention, the second source/drain metal layer pattern 2062 is added, so that the first semiconductor layer pattern 2041 can be protected, and the damage to the first semiconductor layer pattern 2041 when the third via hole on the second insulating layer 205 is formed can be avoided, and in addition, the depth of the second via hole can be reduced, so that the connection via hole is changed from a deep hole to a shallow hole, and the anode pattern 208 is prevented from being broken at the connection via hole. Meanwhile, the second source/drain metal layer pattern 2062 and the first source/drain metal layer pattern 2061 are formed of the same material in the same layer and may be formed by a single patterning process, so that the number of masks may be reduced and the process cost may be reduced.
The driving circuit in the embodiment of the present invention further includes a driving thin film transistor, and at this time, preferably, the semiconductor layer pattern further includes a first active layer pattern of the driving thin film transistor, and the source-drain metal layer pattern further includes a first source pattern and a first drain pattern of the driving thin film transistor.
In the embodiment of the present invention, the first source-drain metal layer pattern 2061 is connected to the gate pattern of the driving thin film transistor, that is, the first source-drain metal layer pattern 2061 is connected to the point G, and the first semiconductor layer pattern 2041 is connected to the drain pattern of the driving thin film transistor T1, that is, the first semiconductor layer pattern 2041 is connected to the point S, so as to implement the storage capacitor.
In order to further reduce the number of via holes on the O L ED display substrate, in an embodiment of the present invention, it is preferable that the first drain pattern is connected to the second source-drain metal layer pattern, the first active layer pattern is connected to the first semiconductor layer pattern, and the first active layer pattern is connected to the first drain pattern through the first semiconductor layer pattern and the second source-drain metal layer pattern, so that it is not necessary to separately provide via holes connecting the first active layer pattern and the first drain pattern, and the number of via holes is reduced.
Referring to fig. 6, the driving circuit in the embodiment of the invention may further include a touch thin film transistor T3.
In the embodiment of the present invention, preferably, the semiconductor layer pattern further includes a second active layer pattern of the touch thin film transistor, and the source-drain metal layer pattern further includes a second source pattern and a second drain pattern of the touch thin film transistor.
In the embodiment of the present invention, it is further preferable that the light shielding layer pattern further includes a second light shielding layer pattern, and the via hole of the first insulating layer further includes a fifth via hole, where the second light shielding layer pattern is connected to the second source pattern of the touch thin film transistor and is configured to input a touch signal to the touch thin film transistor, that is, the second light shielding layer pattern serves as a touch signal line. In an embodiment of the present invention, preferably, the second active layer pattern is directly connected to the second light shielding layer pattern through a fifth via hole on the first insulating layer, the second source pattern is connected to the second active layer pattern through a sixth via hole penetrating through the second insulating layer, and an orthographic projection of the sixth via hole on the substrate is located in an orthographic projection area of the fifth via hole on the substrate. The fifth via hole and the sixth via hole are overlapped in position and can be regarded as one via hole, that is, two via holes in the prior art are combined into one via hole, so that the number of the via holes is reduced, and the aperture opening ratio of the pixel is improved.
In the embodiment of the present invention, it can be understood that the second active layer pattern of the touch thin film transistor T3 further needs to be connected to the second drain electrode pattern, in the embodiment of the present invention, preferably, the second active layer pattern of the touch thin film transistor T3 is connected to the first semiconductor layer pattern, the second drain electrode pattern of the touch thin film transistor T3 is connected to the second source drain metal layer pattern, and the second active layer pattern is connected to the second drain electrode pattern through the first semiconductor layer pattern and the second source drain metal layer pattern. So that the second active layer pattern and the second drain pattern of the via touch tft T3 may be connected without adding a via touch tft T3. That is, in the embodiment of the present invention, one via (please refer to fig. 3, the first via 109 and the second via 110 are overlapped) is adopted to accomplish the following functions: first, a first semiconductor layer pattern and a first light shielding layer pattern are connected, second, an anode pattern and a first semiconductor layer pattern are connected, third, a first active layer pattern and a first drain pattern of a driving thin film transistor are connected, fourth, a first drain pattern and an anode pattern are connected, and fifth, a second active layer pattern and a second drain pattern of a touch thin film transistor T3 are connected.
In the above embodiments of the present invention, the semiconductor layer pattern may be made of a metal oxide material, such as IGZO.
The invention also provides a display device comprising the O L ED display substrate in any one of the embodiments.
The embodiment of the invention also provides a manufacturing method of the O L ED display substrate, which comprises the following steps:
step 11: providing a substrate base plate;
step 12: a shading layer pattern, a first insulating layer, a semiconductor layer pattern, a second insulating layer and a source drain metal layer pattern are sequentially formed on the substrate, the shading layer pattern is made of a conductive material, and the semiconductor layer pattern is directly connected with the shading layer pattern through a through hole in the first insulating layer.
The light shielding layer pattern formed by the manufacturing method of the embodiment of the invention is directly connected with the semiconductor layer pattern, so that parasitic capacitance cannot be generated between the light shielding layer pattern and the semiconductor layer pattern. In addition, the light shielding layer pattern is directly connected with the semiconductor layer pattern, and switching of the source drain metal layer pattern and the drain source metal layer pattern is not needed.
In some embodiments of the present invention, the light shielding layer pattern includes a first light shielding layer pattern, the semiconductor layer pattern includes a first semiconductor layer pattern, the source-drain metal layer pattern includes a first source-drain metal layer pattern, and the via hole on the first insulating layer includes a first via hole; the manufacturing method further comprises the following steps:
a third insulating layer and an anode pattern are sequentially formed on the source-drain metal layer pattern, the first shading layer pattern, the first insulating layer, the first semiconductor layer pattern, the second insulating layer, the first source-drain metal layer pattern, the third insulating layer and the anode pattern form a storage capacitor, the first semiconductor layer pattern is directly connected with the first light shielding layer pattern through a first via hole on the first insulating layer, the anode pattern is connected to the first semiconductor layer pattern through a second via hole penetrating the second and third insulating layers, the orthographic projection of the second via hole on the substrate base plate is completely positioned in the orthographic projection area of the first via hole on the substrate base plate, the first source drain metal layer pattern is used as a first electrode of the storage capacitor, and the first shading layer pattern, the first semiconductor layer pattern and the anode pattern are connected to be used as a second electrode of the storage capacitor.
The storage capacitor formed in the embodiment of the invention comprises the first shading layer pattern, the first semiconductor layer pattern, the first source drain metal layer pattern and the anode pattern which are arranged in a superposition mode, namely the storage capacitor comprises four electrode plates, so that the storage capacitor is large. Meanwhile, the first light shielding layer pattern is connected with the first semiconductor layer pattern, so that parasitic capacitance cannot be generated between the first light shielding layer pattern and the first semiconductor layer pattern. In addition, the first via hole and the second via hole which are used for connecting the first light shielding layer pattern, the first semiconductor layer pattern and the anode pattern can be regarded as a via hole due to position superposition, namely, the first light shielding layer pattern, the first semiconductor layer pattern and the anode pattern can be connected through a via hole edge, the number of the via holes is reduced, the occupied area of the via holes is reduced, and the aperture opening ratio of pixels is improved.
In the embodiment of the present invention, the second via hole is formed by communicating a third via hole on the second insulating layer with a fourth via hole on the third insulating layer, and the source-drain metal layer pattern further includes: and the second source drain metal layer graph is connected with the first semiconductor layer graph through a third via hole on the second insulating layer, and the anode graph is connected with the second source drain metal layer graph through a fourth via hole.
The O L ED display substrate manufactured in the embodiment of the invention is additionally provided with the second source drain metal layer graph, the first semiconductor layer graph can be protected, the damage to the first semiconductor layer graph is avoided when the third via hole on the second insulating layer is formed, in addition, the depth of the second via hole can be reduced, the connecting via hole is changed from a deep hole to a shallow hole, the anode graph is prevented from being broken at the connecting via hole, meanwhile, the second source drain metal layer graph and the first source drain metal layer graph are formed through a one-step composition process, the mask number can be reduced, and the process cost is reduced.
In some embodiments of the present invention, preferably, the semiconductor layer pattern further includes a first active layer pattern for driving the thin film transistor, the source-drain metal layer pattern further includes a first source pattern and a first drain pattern for driving the thin film transistor, the first drain pattern is connected to the second source-drain metal layer pattern, the first active layer pattern is connected to the first semiconductor layer pattern, and the first active layer pattern is connected to the first drain pattern by the first semiconductor layer pattern and the second source-drain metal layer pattern. In the embodiment of the invention, the through holes for connecting the first active layer pattern and the first drain electrode pattern do not need to be separately arranged, and the number of the through holes is reduced.
In some embodiments of the present invention, the semiconductor layer pattern further includes a second active layer pattern of a touch thin film transistor, the source-drain metal layer pattern further comprises a second source electrode pattern and a second drain electrode pattern of the touch thin film transistor, the light shielding layer pattern further comprises a second light shielding layer pattern, the via hole of the first insulating layer further comprises a fifth via hole, wherein the second light shielding layer pattern is connected with the second source electrode pattern of the touch thin film transistor, the second active layer pattern is directly connected with the second light shielding layer pattern through a fifth via hole on the first insulating layer, the second source pattern is connected to the second active layer pattern through a sixth via hole penetrating the second insulating layer, and the orthographic projection of the sixth via hole on the substrate base plate is positioned in the orthographic projection area of the fifth via hole on the substrate base plate. The fifth via hole and the sixth via hole are superposed in position and can be regarded as one via hole, that is, two via holes in the prior art are combined into one via hole, so that the number of the via holes is reduced, and the aperture opening ratio of the pixel is improved.
In some embodiments of the present invention, the second active layer pattern is connected to the first semiconductor layer pattern, the second drain electrode pattern is connected to the second source drain metal layer pattern, and the second active layer pattern is connected to the second drain electrode pattern by the first semiconductor layer pattern and the second source drain metal layer pattern. In the embodiment of the invention, the second active layer graph and the second drain electrode graph of the via hole touch thin film transistor can be connected without increasing, namely, the first semiconductor layer graph is connected with the second source drain metal layer graph, so that the number of via holes is further reduced.
In the conventional process for manufacturing an O L ED display substrate, please refer to fig. 2, a first insulating layer is usually formed first, then an active layer pattern is formed, then a second insulating layer is formed, then the via hole 109 is etched, the etched object is the second insulating layer and a part of the first insulating layer, then the second insulating layer is etched, the second insulating layer above the active layer pattern is etched by the etching, the remaining first insulating layer in the via hole 109 is also etched by the etching, two different layers are etched by the etching for one time, and the materials of the etching points of the two via holes are different, which is very difficult for the process and not beneficial to large-scale production.
In the embodiment of the invention, after the first insulating layer is formed, the via hole on the first insulating layer is etched immediately, the semiconductor layer pattern and the shading layer pattern are directly connected through the via hole, and then the second insulating layer is formed, and the via hole on the second insulating layer is etched, so that the difficulty of the process is greatly reduced, and the large-scale production can be realized.
Referring to fig. 7-13, fig. 7-13 are schematic flow charts illustrating a method for manufacturing an O L ED display substrate according to an embodiment of the present invention, the method for manufacturing an O L ED display substrate includes:
step 21: referring to fig. 7, a substrate 201 is provided, and a light shielding layer pattern is formed on the substrate 201, where the light shielding layer pattern includes a first light shielding layer pattern 202 and a second light shielding layer pattern (not shown);
the base substrate 201 may be a glass substrate.
The first and second light shielding layer patterns 202 and 202 may be made of a metal material, for example, Mo.
The first light-shielding layer pattern 202 is used for shielding an active layer of the thin film transistor and also can serve as a plate of the storage capacitor.
The second shading layer pattern is used as a touch signal line.
Step 22: referring to fig. 8, a first insulating layer 203 is formed, and a via hole is formed on the first insulating layer 203.
The first insulating layer 203 may be a buffer layer and may be made of silicon dioxide. The via may be formed by photolithography and dry etching processes.
Step 23: referring to fig. 9, a semiconductor layer pattern is formed through a single patterning process, the semiconductor layer pattern including: the touch screen includes a first semiconductor layer pattern 2041, a first active layer pattern (not shown) of the driving thin film transistor, and a second active layer pattern (not shown) of the touch thin film transistor, wherein the first semiconductor layer pattern 2041 is connected to the first light shielding layer pattern 202 through a via hole on the first insulating layer 203, the second active layer pattern is connected to the second light shielding layer pattern through a via hole on the first insulating layer 203, the first active layer pattern of the driving thin film transistor is connected to the first semiconductor layer pattern 2041, and the second active layer pattern of the touch thin film transistor is connected to the first semiconductor layer pattern 2041.
The semiconductor layer pattern may be made of a metal oxide, such as IGZO. The thickness of the semiconductor layer pattern may be about
The semiconductor layer pattern may be formed using photolithography and wet etching processes.
Step 24: a gate insulating layer (not shown), a gate pattern (not shown) including a driving transistor, and a gate pattern (not shown) of a touch thin film transistor are formed through a one-time patterning process.
Step 25: referring to fig. 10, a second insulating layer 205 is formed, and a via is formed on the second insulating layer 205.
The second insulating layer 205 may be an interlayer dielectric layer and may be made of silicon dioxide. The via hole may be formed using photolithography and dry etching processes.
Step 26: referring to fig. 11, a source-drain metal layer pattern is formed by a one-pass communication process, where the source-drain metal layer pattern includes: a first source-drain metal layer pattern 2061, a second source-drain metal layer pattern 2062, a first source electrode pattern (not shown) and a first drain electrode pattern (not shown) of the driving thin film transistor, a second source electrode pattern (not shown) and a second drain electrode pattern (not shown) of the touch thin film transistor, wherein the second source-drain metal layer pattern 2062 is connected to the first semiconductor layer pattern 2041 through a via hole in the second insulating layer 205, the first source pattern of the driving thin film transistor is connected to the first active layer pattern of the driving thin film transistor through a via hole in the second insulating layer 205, the first drain pattern of the driving thin film transistor is connected to the second source-drain metal layer pattern, since the first active layer pattern of the driving thin film transistor is connected to the first semiconductor layer pattern 2041, the first semiconductor layer pattern 2041 is connected to the second source drain metal layer pattern, thus, the first drain pattern of the driving thin film transistor is connected with the first active layer pattern of the driving thin film transistor. The second drain pattern of the touch thin film transistor is connected to the second source-drain metal layer pattern 2062, and since the second active layer pattern of the touch thin film transistor is connected to the first semiconductor layer pattern 2041 and the first semiconductor layer pattern 2041 is connected to the second source-drain metal layer pattern 2062, the second drain pattern of the touch thin film transistor is connected to the second active layer pattern of the touch thin film transistor. And a second source electrode graph of the touch thin film transistor is connected with the second active layer graph through a via hole of the second insulating layer, and the via hole is superposed with the via hole connected with the second active layer graph and the second light shielding layer graph in position.
The source and drain metal layer patterns can be formed by adopting photoetching and wet etching processes.
Step 27: referring to fig. 12, a third insulating layer 207 is formed, and a via hole is formed in the third insulating layer 207, and the via hole overlaps with a via hole connecting the second source-drain metal layer pattern 2062 and the first semiconductor layer pattern 2041.
The third insulating layer 207 may be a passivation layer. The via hole may be formed using photolithography and dry etching processes.
Step 28: referring to fig. 13, an anode pattern 208 is formed, and the anode pattern 208 is connected to the second source-drain metal layer pattern 2062 through a via hole on the third insulating layer.
The anode pattern 208 may be made of ITO or the like. The anode pattern 208 may be formed using photolithography and wet etching processes.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in the description and claims of the present application do not denote any order, quantity, or importance, but rather the terms are used to distinguish one element from another. Also, the use of the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships are changed accordingly.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (11)
1. An O L ED display substrate is characterized by comprising a substrate, and a light shielding layer pattern, a first insulating layer, a semiconductor layer pattern, a second insulating layer and a source drain metal layer pattern which are sequentially arranged on the substrate, wherein the light shielding layer pattern is made of a conductive material, and the semiconductor layer pattern is directly connected with the light shielding layer pattern through a through hole on the first insulating layer;
the light shield layer graph comprises a first light shield layer graph, the semiconductor layer graph comprises a first semiconductor layer graph, the source drain metal layer graph comprises a first source drain metal layer graph, the via hole in the first insulating layer comprises a first via hole, the O L ED display substrate further comprises a third insulating layer and an anode graph which are sequentially arranged on the source drain metal layer graph, the first light shield layer graph, the first insulating layer, the first semiconductor layer graph, the second insulating layer, the first source drain metal layer graph, the third insulating layer and the anode graph form a storage capacitor, the first semiconductor layer graph is directly connected with the first light shield layer graph through the first via hole in the first insulating layer, the anode graph is connected with the first semiconductor layer graph through a second via hole penetrating through the second insulating layer and the third insulating layer, the orthographic projection of the second via hole on the substrate is completely located in the orthographic projection area of the first via hole on the substrate, the first source drain metal layer graph serves as a first electrode of the storage capacitor, and the first light shield layer graph, the first semiconductor layer graph and the anode graph are connected as a second electrode of the storage capacitor.
2. The O L ED display substrate of claim 1, wherein the second via hole is formed by a third via hole on the second insulating layer and a fourth via hole on the third insulating layer in communication, the source-drain metal layer pattern further comprises a second source-drain metal layer pattern, the second source-drain metal layer pattern is connected with the first semiconductor layer pattern through the third via hole on the second insulating layer, and the anode pattern is connected with the second source-drain metal layer pattern through the fourth via hole.
3. The O L ED display substrate of claim 2, wherein the semiconductor layer pattern further includes a first active layer pattern for driving a thin film transistor, the source-drain metal layer pattern further includes a first source pattern and a first drain pattern for driving a thin film transistor, the first drain pattern is connected to the second source-drain metal layer pattern, the first active layer pattern is connected to the first semiconductor layer pattern, and the first active layer pattern is connected to the first drain pattern via the first semiconductor layer pattern and the second source-drain metal layer pattern.
4. The O L ED display substrate of claim 2, wherein the semiconductor layer pattern further includes a second active layer pattern of a touch thin film transistor, the source-drain metal layer pattern further includes a second source pattern and a second drain pattern of the touch thin film transistor, the light shield layer pattern further includes a second light shield layer pattern, the via hole of the first insulating layer further includes a fifth via hole, wherein the second light shield layer pattern is connected to the second source pattern of the touch thin film transistor for inputting a touch signal to the touch thin film transistor, the second active layer pattern is directly connected to the second light shield layer pattern through a fifth via hole on the first insulating layer, the second source pattern is connected to the second active layer pattern through a sixth via hole penetrating through the second insulating layer, and an orthographic projection of the sixth via hole on the substrate is located in an orthographic projection area of the fifth via hole on the substrate.
5. The O L ED display substrate of claim 4, wherein the second active layer pattern is connected to the first semiconductor layer pattern, the second drain pattern is connected to the second source-drain metal layer pattern, and the second active layer pattern is connected to the second drain pattern via the first semiconductor layer pattern and the second source-drain metal layer pattern.
6. A method for manufacturing an O L ED display substrate is characterized by comprising the following steps:
providing a substrate base plate;
sequentially forming a light shielding layer pattern, a first insulating layer, a semiconductor layer pattern, a second insulating layer and a source drain metal layer pattern on the substrate, wherein the light shielding layer pattern is made of a conductive material, and the semiconductor layer pattern is directly connected with the light shielding layer pattern through a through hole in the first insulating layer;
the light shielding layer patterns comprise first light shielding layer patterns, the semiconductor layer patterns comprise first semiconductor layer patterns, the source drain metal layer patterns comprise first source drain metal layer patterns, and the via holes in the first insulating layer comprise first via holes; the manufacturing method further comprises the following steps:
a third insulating layer and an anode pattern are sequentially formed on the source-drain metal layer pattern, the first shading layer pattern, the first insulating layer, the first semiconductor layer pattern, the second insulating layer, the first source-drain metal layer pattern, the third insulating layer and the anode pattern form a storage capacitor, the first semiconductor layer pattern is directly connected with the first light shielding layer pattern through a first via hole on the first insulating layer, the anode pattern is connected to the first semiconductor layer pattern through a second via hole penetrating the second and third insulating layers, the orthographic projection of the second via hole on the substrate base plate is completely positioned in the orthographic projection area of the first via hole on the substrate base plate, the first source drain metal layer pattern is used as a first electrode of the storage capacitor, and the first shading layer pattern, the first semiconductor layer pattern and the anode pattern are connected to be used as a second electrode of the storage capacitor.
7. The O L ED display substrate manufacturing method according to claim 6, wherein the second via hole is formed by communicating a third via hole on the second insulating layer with a fourth via hole on the third insulating layer, the source-drain metal layer pattern further includes a second source-drain metal layer pattern, the second source-drain metal layer pattern is connected with the first semiconductor layer pattern through the third via hole on the second insulating layer, and the anode pattern is connected with the second source-drain metal layer pattern through the fourth via hole.
8. The O L ED display substrate manufacturing method according to claim 7, wherein the semiconductor layer pattern further includes a first active layer pattern for driving a thin film transistor, the source-drain metal layer pattern further includes a first source pattern and a first drain pattern for driving a thin film transistor, the first drain pattern is connected to the second source-drain metal layer pattern, the first active layer pattern is connected to the first semiconductor layer pattern, and the first active layer pattern is connected to the first drain pattern by the first semiconductor layer pattern and the second source-drain metal layer pattern.
9. The O L ED display substrate manufacturing method according to claim 7, wherein the semiconductor layer pattern further includes a second active layer pattern of a touch thin film transistor, the source-drain metal layer pattern further includes a second source pattern and a second drain pattern of the touch thin film transistor, the light shielding layer pattern further includes a second light shielding layer pattern, the via hole of the first insulating layer further includes a fifth via hole, wherein the second light shielding layer pattern is connected to the second source pattern of the touch thin film transistor for inputting a touch signal to the touch thin film transistor, the second active layer pattern is directly connected to the second light shielding layer pattern through a fifth via hole on the first insulating layer, the second source pattern is connected to the second active layer pattern through a sixth via hole penetrating through the second insulating layer, and an orthographic projection of the sixth via hole on the substrate is located in an orthographic projection area of the fifth via hole on the substrate.
10. The O L ED display substrate manufacturing method of claim 9, wherein the second active layer pattern is connected to the first semiconductor layer pattern, the second drain pattern is connected to the second source-drain metal layer pattern, and the second active layer pattern is connected to the second drain pattern via the first semiconductor layer pattern and the second source-drain metal layer pattern.
11. A display device comprising the O L ED display substrate of any one of claims 1-5.
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| JP2004151546A (en) * | 2002-10-31 | 2004-05-27 | Sharp Corp | Active matrix substrate and display apparatus |
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