CN105590958A - 双沟槽高压屏蔽的横向绝缘栅双极器件及其制备方法 - Google Patents
双沟槽高压屏蔽的横向绝缘栅双极器件及其制备方法 Download PDFInfo
- Publication number
- CN105590958A CN105590958A CN201510965034.9A CN201510965034A CN105590958A CN 105590958 A CN105590958 A CN 105590958A CN 201510965034 A CN201510965034 A CN 201510965034A CN 105590958 A CN105590958 A CN 105590958A
- Authority
- CN
- China
- Prior art keywords
- groove
- type
- trench
- bipolar device
- polysilicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 30
- 229920005591 polysilicon Polymers 0.000 claims abstract description 30
- 229910052751 metal Inorganic materials 0.000 claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 230000002093 peripheral effect Effects 0.000 claims abstract description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 16
- 238000010276 construction Methods 0.000 claims description 16
- 229910052760 oxygen Inorganic materials 0.000 claims description 16
- 239000001301 oxygen Substances 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 13
- 238000005516 engineering process Methods 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 235000008429 bread Nutrition 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 claims 2
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical group [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 claims 1
- 210000000746 body region Anatomy 0.000 abstract 4
- 230000005684 electric field Effects 0.000 description 5
- 238000009825 accumulation Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000012216 screening Methods 0.000 description 3
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000010606 normalization Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7394—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
- Thyristors (AREA)
Abstract
一种双沟槽高压屏蔽的横向绝缘栅双极器件及其制备方法，包括：P型衬底，埋氧层，N型外延层，在N型外延层中设有P型体区和N型缓冲层，在P型体区内设有P型发射极和N型发射极，N型发射极上方设有多晶硅栅，多晶硅栅上设有金属连接多晶硅栅至结构外围的输入\输出，在N型缓冲层中设有P型集电极，N型缓冲层上方有多晶硅场板，多晶硅场板上连有栅极金属，P型体区三面包围着N型缓冲层，留有一面的间断，P型集电极连有集电极金属连线，在集电极金属连线之下靠近结构边缘设有沟槽，沟槽内掺有介质，在整个结构外包围有沟槽，沟槽内掺有介质。所述高压互连线屏蔽结构靠近集电极的沟槽下方不与埋氧层接触，留有空隙。
Description
技术领域
本发明主要涉及功率集成电路技术领域，具体来说，特别适用于开关电源、马达控制、汽车电子系统、家用电器等诸多功率控制处理领域。
背景技术
高压功率集成技术是VLSI与功率器件结合的产物。在同一芯片上集成有低压控制电路和高压功率元件的高压集成电路使电子系统所要求的电子元件数目极大的降低，从而降低系统成本，减小了设备尺寸，提高了系统可靠性。
高压集成电路已经被广泛运用到包括电子照明、电机驱动、电源管理、工业控制以及显示驱动等等广泛的领域中。高压集成电路的发展和应用，促使传统产业与信息产业融通，已经对人类生产和生活产生了深远的影响。
对于高压集成电路，需要高压互连线进行高侧及低侧之间的信号传递；遗憾的是，由于高压互连线上的电势较高，往往造成其下方硅区域耐压降低，使高压集成电路的可靠性降低。因此，高压互连线屏蔽技术是研究设计高压集成电路必须解决的关键技术。本发明针对高压互连线导致耐压降低的问题，提出一种新型的高压互连线屏蔽结构，极大地提高了高压互连线下方的耐压，提高整个高压集成电路可靠性。
发明内容
本发明针对上述问题，提出了一种双沟槽高压屏蔽的横向绝缘栅双极器件及其制备方法，本发明结构可以有效防止因高压互连线影响导致的器件提前击穿，增强整个高压集成电路的可靠性。
本发明提供如下技术方案：
一种具有新型双沟槽高压互连线屏蔽结构的横向绝缘栅双极器件结构，包括：P型衬底，在P型衬底上设有埋氧层，在埋氧层上设有N型外延层，在N型外延层中设有P型体区和N型缓冲层，在P型体区内设有P型发射极和N型发射极，N型发射极上方设有多晶硅栅，多晶硅栅上设有金属连接多晶硅栅至结构外围的输入\输出，在N型缓冲层中设有P型集电极，N型缓冲层上方有多晶硅场板，多晶硅场板由多晶硅场板上方的金属连接至结构外围的输入\输出，P型体区三面包围着N型缓冲层，留有一面的间断，由P型集电极引出的集电极金属连线通过间断区域延伸至结构外的输入\输出，在集电极金属连线之下靠近结构边缘设有相互靠近的两个沟槽，靠近集电极的沟槽短于距离集电极较远的沟槽，沟槽内掺有多晶硅，沟槽的走向垂直于集电极金属连线的走向，在整个结构外包围有沟槽，内掺有多晶硅，隔离整个结构与外围区域。上述高压互连线屏蔽结构其特征在于靠近集电极的沟槽下方不与埋氧层接触，留有空隙。
与现有技术相比，本发明具有如下优点：
本发明在传统结构基础上，提出了一种新的结构，P型体区包围N型缓冲层的结构为三面包围，留有一侧间断，高压互连线从间断一侧延伸至结构外，当高压互连线上通过高压时，其下方的沟槽帮助耐压，靠近集电极的沟槽不与埋氧层接触，留有较大空隙，使得电压更加均匀地分布在沟槽结构中，距离集电极较远的沟槽所分担的电势相对于靠近集电极的沟槽得到提升，当缩小沟槽到集电极的距离时，仍能保证高压器件不提前击穿。
本发明提出的高压互连线屏蔽结构，工艺简单，通过调整沟槽刻蚀窗口的宽度，一步形成多个沟槽，不增加制备成本。
对于双沟槽结构，本发明结构减小了靠近集电极的沟槽长度，一般的，沟槽长度缩短，沟槽的电容减小，沟槽的耐压能力下降，器件总体的高压互连线屏蔽能力下降。本发明指出，缩短靠近集电极的沟槽长度后，虽然靠近集电极的沟槽的耐压能力有所降低，但是距离集电极较远的沟槽承受更高的电压，使器件总体的高压互连线屏蔽能力上升。
此外，对于双沟槽结构，UIS、dv/dt产生的空穴会往低电位方向流动，积累在靠近集电极的沟槽的顶部，导致动态雪崩，本发明由于提高了距离集电极较远的沟槽的耐压，降低了靠近集电极的沟槽的耐压，缓解了靠近集电极的沟槽表面的电场，使得在UIS时空穴积累量减少，提高了器件的动态雪崩抑制能力。
附图说明
图1所示为普通高压互连线的顶层部分腐蚀结构图。
图2所示为普通高压互连线去除金属铝和氧化层后的顶层结构图图。
图3所示为普通高压互连线的AB方向剖面图。
图4所示为普通高压互连线的CD方向剖面图。
图5所示为本发明高压互连线的顶层部分腐蚀结构图。
图6所示为本发明高压互连线去除金属铝和氧化层后的顶层结构图。
图7所示为本发明高压互连线的AB方向剖面图。
图8所示为本发明高压互连线的CD方向剖面图。
图9所示为普通双沟槽互连线结构UIS关断过程中空穴移动的示意图。
图10所示为本发明高压互连线屏蔽结构UIS关断过程中空穴移动的示意图。
图11所示为本发明高压互连线屏蔽结构与普通双沟槽互连线结构的耐压对比图。
图12所示为本发明结构制作工艺流程图。
具体实施方式
下面结合图2，对本发明做详细说明，一种具有新型双沟槽高压互连线屏蔽结构的横向绝缘栅双极器件，包括：P型衬底1，在P型衬底1上设有埋氧层2，在埋氧层2上设有N型外延层3，在N型外延层3中设有P型体区4和N型缓冲层5，在P型体区4内设有N型发射极6和P型发射极7，N型发射极7上方设有多晶硅栅13，多晶硅栅13上设有金属18连接多晶硅栅14至结构外围的输入\输出16，在N型缓冲层5中设有P型集电极8，N型缓冲层5上方有多晶硅场板14，多晶硅场板14由多晶硅场板14上方的金属9连接至结构外围的输入\输出15，P型体区4三面包围着N型缓冲层5，留有一面的间断，由P型集电极8引出的集电极金属连线9通过间断区域延伸至结构外的输入\输出15，在集电极金属连线9之下靠近结构边缘设有沟槽10和沟槽11，沟槽10浅于沟槽11，沟槽10和沟槽11内掺有耐压介质，沟槽10和沟槽11的走向垂直于集电极金属连线9的走向，在整个结构外包围有沟槽12，沟槽12内掺有多晶硅，隔离整个结构与外围区域。上述高压互连线屏蔽结构其特征在于沟槽10下方不与埋氧层接触，留有空隙。
所述的一种高压互连线屏蔽结构，沟槽10深度介于0.1um到100um之间。
所述的一种高压互连线屏蔽结构，沟槽10与沟槽11的宽度介于0.1um到50um之间。
所述的一种高压互连线屏蔽结构，沟槽11的深度介于0.1um到100umm之间。
所述的一种高压互连线屏蔽结构,沟槽10与沟槽11之间的沟槽数量介于0到100之间。
所述的一种高压互连线屏蔽结构,沟槽10与沟槽11之间的沟槽依次变深。
所述的一种高压互连线屏蔽结构,沟槽10、沟槽11与沟槽12可以是全二氧化硅或其它耐压介质，也可以是二氧化硅或其它耐压介质包裹多晶硅。
下面介绍本发明结构的制备方法，包括以下步骤，如图12所示。
一种具有新型高压互连线屏蔽结构的横向绝缘栅双极器件的制备方法，包括以下步骤：P型衬底1、埋氧层2的制备，在埋氧层2上外延N型外延层3，在N型外延层上用深槽工艺形成沟槽10、沟槽11与沟槽12，在N型外延层3中用高浓度离子注入工艺形成P型体区4、N型发射极6和P型发射极7，用高浓度离子注入工艺形成N型缓冲层5和P型集电极区8，用槽栅工艺制造成多晶硅场板13、多晶硅栅14，在器件表面淀积氧化层20，接着进行打孔处理、淀积金属铝形成发射极金属连线19、多晶硅栅14的金属连线18和集电极金属连线9，最后在结构外围形成输入\输出16、输入\输出17、输入\输出15。
下面结合附图对本发明进行进一步说明。
本发明的工作原理：
高压集成电路将低压控制电路和高压器件集成在同一芯片时，需要实现高低压隔离之间的互联。LDMOS或者LIGBT漂移区上方通常需要跨过高压互连线，由于高压互连线相对于半导体表面带正电，且一般需要耐压达到几百伏，导致高压互联线下方电势线的局部集中，该处电场急剧增大，导致高压器件提前击穿。
传统方案中，高压互连线从绝缘介质层的表面跨过高压器件，这种方法工艺复杂，成本高，最糟糕的是整体器件的耐压被高压互连线上的高压引入的高电场以及介质层的耐压能力所限制。为了提高耐压，有方案采用了双沟槽结构，当高压互连线上通过高压时，其下方的沟槽帮助耐压，从而提高器件的耐压。然而，这种方法亦有其缺点，耐压主要由靠近集电极的沟槽完成，其他的沟槽没有充分发挥作用。
本发明在传统结构基础上，提出了一种新的结构，P型体区包围N型缓冲层的结构为三面包围，留有一侧间断，高压互连线从间断一侧延伸至结构外，当高压互连线上通过高压时，电压分布在沟槽结构中，距离集电极较远的沟槽承受更高的电压，从而提高器件的耐压，工艺简单，同时不增加制备成本。
在本发明结构中，沟槽的作用相当于电容,吸收周围的电势线。未缩短靠近集电极的沟槽时，耐压主要由该沟槽完成，距离集电极较远的沟槽上的电荷主要是感应电荷，耐压较小。一般的，沟槽长度缩短，沟槽的电容减小，沟槽的耐压能力下降，器件总体的高压互连线屏蔽能力下降。本结构看似反其道而行，虽然缩小了靠近集电极的沟槽长度，减小了该电容的面积，但是沟槽和埋氧层之间的空隙使得电势线扩展至后一沟槽，距离集电极较远的沟槽上的电荷不再以感应电荷为主，该沟槽的吸收的电势线增多、耐压增大，充分发挥了该沟槽的作用，从而避免了提前击穿，提高开关管的耐压，使器件总体的高压互连线屏蔽能力上升。附图11为本发明高压互连线屏蔽结构与普通双沟槽互连线结构的耐压对比图，纵坐标为归一化电势，VT2为距离集电极较远沟槽的耐压。从图中可以清晰地看到，与双沟槽结构相比，本结构VT2显著提升，使得器件总体耐压能力提高。
此外，在UIS关断过程中，器件集电极的电压增加，但此时器件的电流没有减小，器件处于高电压、大电流的工作环境。此时，对于双沟槽结构器件，如图9所示，集电极附近的空穴向靠近集电极的沟槽移动，并在此积累，由于靠近集电极的沟槽表面电场集中，靠近集电极的沟槽顶部极易发生雪崩击穿。在本发明中，一方面由于提高了距离集电极较远的沟槽的耐压，降低了靠近集电极的沟槽的耐压，缓解了靠近集电极的沟槽表面的电场；另一方面，由于靠近集电极的沟槽不与埋氧层接触，留有空穴移动的通道，部分空穴向距离集电极较远的沟槽移动，分散了空穴，抑制空穴在靠近集电极的沟槽顶部的过度积累，如图10所示。本发明结构，相对于双沟槽结构，在UIS关断过程中，通过降低靠近集电极的沟槽顶部的电场，大幅减少该区域积累的载流子，提高了器件的动态雪崩抑制能力。
Claims (8)
1.一种双沟槽高压屏蔽的横向绝缘栅双极器件，包括：P型衬底(1)，在P型衬底(1)上设有埋氧层(2)，在埋氧层(2)上设有N型外延层(3)，在N型外延层(3)中设有P型体区(4)和N型缓冲层(5)，在P型体区(4)内设有N型发射极(6)和P型发射极(7)，N型发射极(7)上方设有多晶硅栅(13)，多晶硅栅(13)上设有金属(18)连接多晶硅栅(14)至结构外围的输入\输出(16)，在N型缓冲层(5)中设有P型集电极(8)，N型缓冲层(5)上方有多晶硅场板(14)，多晶硅场板(14)由多晶硅场板(14)上方的金属(9)连接至结构外围的输入\输出(15)，P型体区(4)三面包围着N型缓冲层(5)，留有一面的间断，由P型集电极(8)引出的集电极金属连线(9)通过间断区域延伸至结构外的输入\输出(15)，在集电极金属连线(9)之下靠近结构边缘设有沟槽(10)和沟槽(11)，沟槽(10)浅于沟槽(11)，沟槽(10)和沟槽(11)内掺有介质，沟槽(10)和沟槽(11)的走向垂直于集电极金属连线(9)的走向，在整个结构外包围有沟槽(12)，沟槽(12)内掺有介质，隔离整个结构与外围区域，上述高压互连线屏蔽结构，其特征在于沟槽(10)下方不与埋氧层接触，留有空隙。
2.根据权利要求1所述的双沟槽高压屏蔽的横向绝缘栅双极器件，其特征在于沟槽(10)深度介于0.1um到100um之间。
3.根据权利要求1所述的双沟槽高压屏蔽的横向绝缘栅双极器件，其特征在于沟槽(10)与沟槽(11)的宽度介于0.1um到50um之间。
4.根据权利要求1所述的双沟槽高压屏蔽的横向绝缘栅双极器件，其特征在于沟槽(11)的深度介于0.1um到100umm之间。
5.根据权利要求1所述的一种高压互连线屏蔽结构，其特征在于沟槽(10)与沟槽(11)之间的沟槽数量介于0到100之间。
6.根据权利要求7所述的双沟槽高压屏蔽的横向绝缘栅双极器件，其特征在于沟槽(10)与沟槽(11)之间的沟槽依次变深。
7.根据权利要求1所述的双沟槽高压屏蔽的横向绝缘栅双极器件，其特征在于沟槽(10)、沟槽(11)与沟槽(12)可以是全二氧化硅或其它耐压介质，也可以是二氧化硅或其它耐压介质包裹多晶硅。
8.一种双沟槽高压屏蔽的横向绝缘栅双极器件的制备方法，包括以下步骤：P型衬底(1)、埋氧层(2)的制备，在埋氧层(2)上外延N型外延层(3)，在N型外延层上用深槽工艺形成沟槽(10)、沟槽(11)与沟槽(12)，在N型外延层(3)中用离子注入工艺形成P型体区(4)、N型发射极(6)和P型发射极(7)，用离子注入工艺形成N型缓冲层(5)和P型集电极区(8)，用槽栅工艺制造成多晶硅场板(13)、多晶硅栅(14)，在器件表面淀积氧化层(20)，接着进行打孔处理、淀积金属铝形成发射极金属连线(19)、多晶硅栅(14)的金属连线(18)和集电极金属连线(9)，最后在结构外围形成输入\输出(16)、输入\输出(17)、输入\输出(15)。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510965034.9A CN105590958B (zh) | 2015-12-21 | 2015-12-21 | 双沟槽高压屏蔽的横向绝缘栅双极器件及其制备方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510965034.9A CN105590958B (zh) | 2015-12-21 | 2015-12-21 | 双沟槽高压屏蔽的横向绝缘栅双极器件及其制备方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105590958A true CN105590958A (zh) | 2016-05-18 |
| CN105590958B CN105590958B (zh) | 2018-06-19 |
Family
ID=55930397
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510965034.9A Active CN105590958B (zh) | 2015-12-21 | 2015-12-21 | 双沟槽高压屏蔽的横向绝缘栅双极器件及其制备方法 |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105590958B (zh) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106206702A (zh) * | 2016-07-19 | 2016-12-07 | 东南大学 | 分段双沟槽高压屏蔽的横向绝缘栅双极器件 |
| CN108269843A (zh) * | 2018-01-15 | 2018-07-10 | 东南大学 | 一种带有沟槽的横向绝缘栅双极型晶体管及其制备方法 |
| CN112825301A (zh) * | 2019-11-21 | 2021-05-21 | 东南大学 | 绝缘栅双极型晶体管器件及其制造方法 |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101964344B (zh) * | 2009-06-19 | 2012-06-27 | 东南大学 | 基于绝缘体上硅平板显示器驱动芯片及其制备方法 |
| CN104576722A (zh) * | 2014-12-24 | 2015-04-29 | 东南大学 | 一种高可靠性的横向绝缘栅双极器件及其制备方法 |
-
2015
- 2015-12-21 CN CN201510965034.9A patent/CN105590958B/zh active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106206702A (zh) * | 2016-07-19 | 2016-12-07 | 东南大学 | 分段双沟槽高压屏蔽的横向绝缘栅双极器件 |
| CN106206702B (zh) * | 2016-07-19 | 2019-06-18 | 东南大学 | 分段双沟槽高压屏蔽的横向绝缘栅双极器件 |
| CN108269843A (zh) * | 2018-01-15 | 2018-07-10 | 东南大学 | 一种带有沟槽的横向绝缘栅双极型晶体管及其制备方法 |
| CN112825301A (zh) * | 2019-11-21 | 2021-05-21 | 东南大学 | 绝缘栅双极型晶体管器件及其制造方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105590958B (zh) | 2018-06-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101969050B (zh) | 一种绝缘体上硅可集成大电流n型组合半导体器件 | |
| CN109065539B (zh) | 一种bcd半导体器件及其制造方法 | |
| CN108231878B (zh) | 一种双向沟槽栅电荷存储型igbt及其制作方法 | |
| CN104518023B (zh) | 高压ldmos器件 | |
| CN108091685A (zh) | 一种提高耐压的半超结mosfet结构及其制备方法 | |
| JP2013254857A (ja) | 半導体装置およびその製造方法 | |
| CN110690278B (zh) | 一种绝缘栅双极型晶体管及其制备方法 | |
| CN105590958A (zh) | 双沟槽高压屏蔽的横向绝缘栅双极器件及其制备方法 | |
| CN104103522B (zh) | 一种高耐压超结终端结构的制备方法 | |
| CN103745988B (zh) | 一种高压驱动电路的隔离结构 | |
| CN103855208A (zh) | 一种高压ldmos集成器件 | |
| CN101976670B (zh) | 一种绝缘体上硅可集成大电流p型组合半导体器件 | |
| CN107425056A (zh) | 一种绝缘栅双极型晶体管器件 | |
| CN104037231A (zh) | 一种高边横向双扩散场效应晶体管 | |
| CN108321192B (zh) | 一种双向沟槽栅电荷存储型igbt及其制作方法 | |
| CN104078498B (zh) | 一种沟槽隔离横向绝缘栅双极型晶体管 | |
| CN202076269U (zh) | 一种绝缘体上硅可集成大电流n型组合半导体器件 | |
| US20150137176A1 (en) | Semiconductor power device | |
| CN201038163Y (zh) | 沟槽高压p型金属氧化物半导体管 | |
| CN105206608A (zh) | 一种双管芯的Trench MOSFET及其加工方法 | |
| CN104576722A (zh) | 一种高可靠性的横向绝缘栅双极器件及其制备方法 | |
| CN102684457A (zh) | 高压桥式电路及其制作方法 | |
| CN108461536B (zh) | 一种双向沟槽栅电荷存储型igbt及其制作方法 | |
| CN112349769A (zh) | 改善雪崩能力的超结终端结构及制造方法 | |
| CN102956636B (zh) | 一种大电流n型绝缘体上硅横向绝缘栅双极型晶体管 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |