CN105589234B - A kind of detection method and its detecting system of panel - Google Patents
A kind of detection method and its detecting system of panel Download PDFInfo
- Publication number
- CN105589234B CN105589234B CN201610173568.2A CN201610173568A CN105589234B CN 105589234 B CN105589234 B CN 105589234B CN 201610173568 A CN201610173568 A CN 201610173568A CN 105589234 B CN105589234 B CN 105589234B
- Authority
- CN
- China
- Prior art keywords
- tft
- array substrate
- panel
- test sample
- sample group
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/1306—Details
- G02F1/1309—Repairing; Testing
Abstract
The invention discloses a kind of detection method of panel and its detecting system, this method includes：High temperature reliability test is carried out to test sample group, determines occur the panel of defect in test sample group；Test sample group is the index plane board group for including uncut multiple panels；Test sample group is disassembled to obtain the motherboard for including multiple array substrates, according to the grid cut-off voltage value of the TFT of array substrate, determines the leakage current value corresponding with grid cut-off voltage value of the TFT of array substrate in the panel for defect occur；If it is determined that leakage current value and predetermined standard off-state current value between difference be less than or equal to given threshold, judge that the TFT of array substrate is qualified；If it is not, then judging not qualified.Method provided in an embodiment of the present invention can be before not being made module by index plane board group, and whether the TFT of array substrate is qualified in timely criterion panel group, has saved the time of manufacturing process, and reduces cost.
Description
Technical field
The present invention relates to display technology field, the detection method and its detecting system of espespecially a kind of panel.
Background technology
Currently, liquid crystal display panel (Liquid Crystal Display, LCD) has high picture quality, small, again
The advantages that light is measured, is widely used in the products such as mobile phone, laptop, television set and display.
TFT switch in thin film transistor (TFT) (Thin Film Transistor, TFT) array substrate has liquid crystal display
Extremely important effect, the quality of TFT switch performance directly affect the height of liquid crystal display quality.But traditional uses liquid crystal
The LCD of technology shows that product will appear a large amount of high temperature spot when carrying out reliability test or adjacent pixel interferes with each other
(crosstalk) the problem of, this is bulk bad to cause low competitiveness to influence to market end.Existing high temperature reliability test
It after method is usually by production at module, puts into temperature control box (high temperature storage device) more than several hours, occurs
A large amount of module goods, materials and equipments can be wasted after high temperature is bad.But the substrate design of product is completed in leading portion already at this time, and product also experienced
Flow from substrate to module, the period is very long, does not have time enough to be designed after problem exposure and is changed with technique.
Invention content
In view of this, the embodiment of the present invention provides a kind of detection method of panel, index plane board group can be made
Before module, whether the TFT of array substrate is qualified in timely criterion panel group, has saved the time of manufacturing process, and
Reduce cost.
Therefore, an embodiment of the present invention provides a kind of detection methods of panel, including：
High temperature reliability test is carried out to test sample group, determines in the test sample group panel of defect occur；Institute
It is the index plane board group for including uncut multiple panels to state test sample group；
The test sample group is disassembled to obtain the motherboard for including multiple array substrates, according to the array substrate
The grid cut-off voltage value of TFT is determining the TFT of array substrate in the panel for defect occur with the grid cut-off voltage
It is worth corresponding leakage current value；
If it is determined that the leakage current value and predetermined standard off-state current value between difference be less than or equal to set
Determine threshold value, judges that the TFT of array substrate in the test sample group is qualified；If it is not, then judging array in the test sample group
The TFT of substrate is not qualified.
In one possible implementation, in the detection method of above-mentioned panel provided in an embodiment of the present invention, according to
The grid cut-off voltage value of the TFT of the array substrate, determine the TFT of array substrate in the panel for defect occur with institute
The corresponding leakage current value of grid cut-off voltage value is stated, is specifically included：
TFT characteristic curve tests are carried out to the test point in array substrate in the panel for defect occur；The test
Point is arranged the non-display area in the array substrate and includes identical with display area and the TFT shapes of gate driving circuit
TFT；
According to the grid cut-off voltage value of the TFT of the array substrate, go out described in determination in obtained TFT characteristic curves
The leakage current value corresponding with the grid cut-off voltage value of the TFT of array substrate in the panel of existing defect.
In one possible implementation, it in the detection method of above-mentioned panel provided in an embodiment of the present invention, uses
Following manner, which determines, there is the panel of defect in test sample group：
Grid open signal is loaded to all array substrates in the test sample group；
When all pixels point in the test sample group is lit, control temperature rise to predetermined temperature determines
Occurs the panel of bad phenomenon during temperature rise as there is the panel of defect.
In one possible implementation, in the detection method of above-mentioned panel provided in an embodiment of the present invention, to institute
All array substrate load grid open signals in test sample group are stated, are specifically included：
Pass through the enabling signal being electrically connected with all array substrates being arranged in the neighboring area of the test sample group
End loads grid open signal to all array substrates；Or,
Grid open signal is loaded to all array substrates respectively.
In one possible implementation, it in the detection method of above-mentioned panel provided in an embodiment of the present invention, uses
Following manner determines standard off-state current value：
TFT characteristic curve tests are carried out to not occurring the test point in the panel of defect in array substrate；The test point
Non-display area in the array substrate is set and includes identical with display area and the TFT shapes of gate driving circuit
TFT；
According to the grid cut-off voltage value of the TFT of the array substrate, in obtained TFT characteristic curves described in determination not
There is the leakage current value corresponding with the grid cut-off voltage value of the TFT of array substrate in the panel of defect as standard OFF state
Current value.
In one possible implementation, in the detection method of above-mentioned panel provided in an embodiment of the present invention, judge
When the TFT of array substrate is not qualified in the test sample group, the TFT designs or process conditions of the array substrate are changed
Into, and remake test sample group and be detected until the TFT of all array substrates is qualified in improved test sample group.
In one possible implementation, in the detection method of above-mentioned panel provided in an embodiment of the present invention, it is poised for battle
The TFT designs of row substrate are improved, and are specifically included：
Adjust the position correspondence of the grid and active layer of each TFT in array substrate；Or,
Adjust the size of active layer.
In one possible implementation, in the detection method of above-mentioned panel provided in an embodiment of the present invention, it is poised for battle
The process conditions of row substrate are improved, and are specifically included：
The technological parameter of gate insulating layer, active layer, passivation layer or ohmic contact layer in adjustment array substrate.
In one possible implementation, described in the detection method of above-mentioned panel provided in an embodiment of the present invention
Given threshold is 15pA.
An embodiment of the present invention provides a kind of detecting systems of panel, including：
Test cell determines and occurs in the test sample group for carrying out high temperature reliability test to test sample group
The panel of defect；The test sample group is the index plane board group for including uncut multiple panels；
Determination unit obtains the motherboard for including multiple array substrates for being disassembled the test sample group, according to
The grid cut-off voltage value of the TFT of the array substrate, determine the TFT of array substrate in the panel for defect occur with institute
State the corresponding leakage current value of grid cut-off voltage value；
Judging unit, be used for if it is determined that the leakage current value and predetermined standard off-state current value between difference
Less than or equal to given threshold, judge that the TFT of array substrate in the test sample group is qualified；If it is not, then judging the test
The TFT of array substrate is not qualified in sample sets.
In one possible implementation, in the detecting system of above-mentioned panel provided in an embodiment of the present invention, test
Unit is specifically used for loading grid open signal to all array substrates in the test sample group；
When all pixels point in the test sample group is lit, control temperature rise to predetermined temperature determines
Occurs the panel of bad phenomenon during temperature rise as there is the panel of defect.
In one possible implementation, it in the detecting system of above-mentioned panel provided in an embodiment of the present invention, determines
Unit, specifically for carrying out TFT characteristic curve tests to there is the test point in the panel of defect in array substrate；The test
Point is arranged the non-display area in the array substrate and includes identical with display area and the TFT shapes of gate driving circuit
TFT；
It is determining in obtained TFT characteristic curves to lack according to the grid cut-off voltage value of the TFT of the array substrate
The leakage current value corresponding with the grid cut-off voltage value of the TFT of array substrate in sunken panel.
The advantageous effect of the embodiment of the present invention includes：
The detection method and its detecting system of a kind of panel provided in an embodiment of the present invention, this method include：To test specimens
Product group carries out high temperature reliability test, determines occur the panel of defect in test sample group；Test sample group be include not cutting
Multiple panels index plane board group；Test sample group is disassembled to obtain the motherboard for including multiple array substrates, according to battle array
The grid cut-off voltage value of the TFT of row substrate, determine occur array substrate in the panel of defect TFT's and grid cut-off voltage
It is worth corresponding leakage current value；If it is determined that leakage current value and predetermined standard off-state current value between difference be less than or wait
In given threshold, judge that the TFT of array substrate is qualified；If it is not, then judging not qualified.Method provided in an embodiment of the present invention can be with
Before module is not made in index plane board group, whether the TFT of array substrate is qualified in timely criterion panel group, saves
The time of manufacturing process, and reduce cost.
Description of the drawings
Fig. 1 is the flow chart of the detection method of panel provided in an embodiment of the present invention；
Fig. 2 is one of test device schematic diagram provided in an embodiment of the present invention；
Fig. 3 is the two of test device schematic diagram provided in an embodiment of the present invention；
Fig. 4 is the TFT performance diagrams of array substrate provided in an embodiment of the present invention.
Specific implementation mode
Below in conjunction with the accompanying drawings, to the specific implementation of the detection method and its detecting system of panel provided in an embodiment of the present invention
Mode is described in detail.
An embodiment of the present invention provides a kind of detection methods of panel, as shown in Figure 1, may comprise steps of：
S101, high temperature reliability test is carried out to test sample group, determines occur the panel of defect in test sample group；It surveys
Test agent group is the index plane board group (Q-panel) for including uncut multiple panels；
S102, test sample group is disassembled to obtain the motherboard for including multiple array substrates, according to the TFT of array substrate
Grid cut-off voltage value, determine the leakage corresponding with grid cut-off voltage value of the TFT of array substrate in the panel of defect occur
Current value；
S103, determination leakage current value and predetermined standard off-state current value between difference whether be less than or equal to
Given threshold；If so, thening follow the steps S104；
S104, judge that the TFT of array substrate in test sample group is qualified；
If it is not, thening follow the steps S105；
S105, judge that the TFT of array substrate in test sample group is not qualified.
In the detection method of above-mentioned panel provided in an embodiment of the present invention, high temperature trust is carried out to test sample group first
Property test, determine occur the panel of defect in test sample group；Test sample group is the standard for including uncut multiple panels
Panel group；Then test sample group is disassembled to obtain the motherboard for including multiple array substrates, according to the TFT's of array substrate
Grid cut-off voltage value determines that the TFT's of array substrate corresponding with the panel for defect occur is corresponding with grid cut-off voltage value
Leakage current value；Later if it is determined that leakage current value and predetermined standard off-state current value between difference be less than or equal to
Given threshold judges that the TFT of array substrate in test sample group is qualified；If it is not, judging the TFT of array substrate in test sample group
It is not qualified.Detection method provided in an embodiment of the present invention can judge mark in time before module is not made in index plane board group
Whether the TFT of array substrate is qualified in quasi- panel group, has saved the time of manufacturing process, and reduces cost.
In the specific implementation, in the detection method of above-mentioned panel provided in an embodiment of the present invention, step S101 is being executed
When, specifically, following manner may be used and determine occur the panel of defect in test sample group, i.e., test sample group is carried out high
The detailed process of warm reliability test is as follows：
First, grid open signal is loaded to all array substrates in test sample group；
Then, when all pixels point in test sample group is lit, control temperature rise to predetermined temperature determines
Occurs the panel of bad phenomenon during temperature rise as there is the panel of defect.
Specifically, as shown in Fig. 2, test sample group 1 (index plane board group Q-panel) is placed on (this in test device 2
Test device can carry out high temperature reliability test, and the environment temperature in test device can be arranged to be risen to successively from small to large
Preset temperature, also, test device is equipped with the backlight of corresponding Q-panel sizes), which can be arranged Celsius 50
It spends between 70 degrees Celsius, i.e., the preset temperature is in hot environment, preferably, the preset temperature can be arranged at 60 degrees Celsius
Left and right.Grid open signal, all pixels in meeting test sample group are loaded to all array substrates in test sample group 1
When point is lit, i.e., when all TFT in array substrate are opened, control temperature rise is to predetermined temperature, in the mistake of temperature rise
There are several panels bad phenomenon occurs in journey, such as high temperature spot or adjacent pixel interfere with each other phenomenon, determine above-mentioned
Several panels are as there is the panel of defect, convenient for testing in next step.Compared with prior art, it is not necessarily to index plane board group system
Being made after module can just be positioned in test device, save back-end process and module goods, materials and equipments.It should be noted that for default
The setting of temperature can not limit herein depending on actual conditions.
In the specific implementation, in the detection method of above-mentioned panel provided in an embodiment of the present invention, in test sample group
All array substrates load grid open signal, can specifically include：
Pass through the enabling signal end pair being electrically connected with all array substrates being arranged in the neighboring area of test sample group
All array substrates load grid open signal；Or, loading grid open signal to all array substrates respectively.
Specifically, as shown in Fig. 2, loading grid open signal to all array substrates, can be passed through by signal generator 3
With all array substrates be electrically connected enabling signal end 4 or directly grasped by using the signal wire in array substrate
Make, method is simple, convenient for control.
In the specific implementation, in the detection method of above-mentioned panel provided in an embodiment of the present invention, step S102 roots are executed
According to the grid cut-off voltage value of the TFT of array substrate, ending with grid for the TFT of array substrate in the panel for defect occur is determined
The corresponding leakage current value of voltage value, can specifically include：
First, TFT characteristic curve tests are carried out to there is the test point in the panel of defect in array substrate；Test point is set
It sets the non-display area in array substrate and includes TFT identical with display area and the TFT shapes of gate driving circuit；
Then, according to the grid cut-off voltage value of the TFT of array substrate, determine occur in obtained TFT characteristic curves
The leakage current value corresponding with grid cut-off voltage value of the TFT of array substrate in the panel of defect.
Specifically, the non-display area of array substrate is provided with test point in the panel for defect occur, which uses
TFT in the display area of characterization array substrate and gate driving circuit, in this way, in the case where not destroying array substrate, it can
Directly to utilize the characteristic of test point instead of the characteristic of display area and multiple TFT of gate driving circuit, method is simple；To surveying
Pilot carries out TFT characteristic curve tests, can obtain the relationship of drain current and grid voltage, according to drain current and grid electricity
The relationship of pressure can accurately find out leakage current value corresponding with grid cut-off voltage value.By taking Fig. 3 as an example, to test sample group
After being disassembled comprising each array substrate motherboard 5 be placed in test device 6 (this test device include TFT test system,
It can carry out TFT characteristic curve tests, the environment temperature in test device could be provided as preset temperature, i.e. preset temperature can be with
It is arranged between 50 degrees Celsius to 70 degrees Celsius, preferably, the preset temperature can be arranged in 60 degrees centigrades), predetermined
At a temperature of, characteristic curve test is carried out to motherboard 5 using the TFT test systems 7 in test device 6, as shown in figure 4, being leaked
The relationship of electrode current and grid voltage can accurately be found out and end with grid according to the relationship of drain current and grid voltage
The corresponding leakage current value of voltage value (the grid cut-off voltage value shown in Fig. 4 is -8V).This embodiment can be adapted for ADS
The panels such as pattern, TN patterns.Certainly, when panel is TN patterns, carrying out the test of TFT characteristic curves can need not be non-display
Test point is arranged in region, can directly test the TFT of display area, not limit herein.
In the specific implementation, in the detection method of above-mentioned panel provided in an embodiment of the present invention, it is true to execute step S103
When whether the difference between fixed leakage current value and predetermined standard off-state current value is less than or equal to given threshold, specifically
Ground can set given threshold to 15pA.The leakage current value that will determine and predetermined standard off-state current value into
Row compares, however, it is determined that the leakage current value gone out differs by more than 15pA with predetermined standard off-state current value, it is determined that array base
The TFT of plate is not qualified；If it is determined that leakage current value is differed with predetermined standard off-state current value is less than or equal to 15pA, then
Determine that the TFT of array substrate is qualified.
In the specific implementation, it in the detection method of above-mentioned panel provided in an embodiment of the present invention, specifically, may be used
Following manner determines standard off-state current value：
TFT characteristic curve tests are carried out to not occurring the test point in the panel of defect in array substrate；Test point is arranged
Array substrate non-display area and include TFT identical with display area and the TFT shapes of gate driving circuit；
It is determining in obtained TFT characteristic curves not occur defect according to the grid cut-off voltage value of the TFT of array substrate
Panel in array substrate TFT leakage current value corresponding with grid cut-off voltage value as standard off-state current value.
It should be noted that the panel for not occurring defect can carry out the test of high temperature reliability really to test sample group
It is fixed, it is disassembled the test sample group to obtain the motherboard comprising multiple array substrates and carries out TFT characteristic curve tests again.Specifically
Ground, the non-display area of array substrate is provided with test point in the panel for not occurring defect, which is used for characterization array
The display area of substrate and the TFT of gate driving circuit can be utilized directly in this way, in the case where not destroying array substrate
The characteristic of test point replaces the characteristic of multiple TFT of display area and gate driving circuit, method simple；Test point is carried out
TFT characteristic curves are tested, and the relationship of drain current and grid voltage can be obtained, according to the pass of drain current and grid voltage
System, can accurately find out leakage current value corresponding with grid cut-off voltage value.At this time using the leakage current value found as standard
Off-state current value.
In the specific implementation, in the detection method of above-mentioned panel provided in an embodiment of the present invention, when judging test sample
In group when the TFT qualifications of array substrate, can directly it be produced according to the TFT design and processes condition in test sample group.
Conversely, in the specific implementation, in the detection method of above-mentioned panel provided in an embodiment of the present invention, when judging in test sample group
When the TFT of array substrate is not qualified, it can be designed with the TFT of array substrate or process conditions are improved, and remake survey
Test agent group is detected until the TFT of all array substrates is qualified in improved test sample group；Finally, after according to improvement
Array substrate TFT design or process conditions produced.
Further, in the specific implementation, in the detection method of above-mentioned panel provided in an embodiment of the present invention, step is executed
The TFT designs of rapid array substrate are improved, and following manner specifically may be used：
Adjust the position correspondence of the grid and active layer of each TFT in array substrate；Or, the size of adjustment active layer
Size.
Specifically, the position correspondence of the grid and active layer of each TFT in array substrate can be directly adjusted, such as
By active layer relative to grid position to the left/right avertence moves；The size of active layer can also be directly changed；Both
Mode is very simple, saves cost, it is of course also possible to other designs of the TFT of array substrate are improved, it can be according to reality
Depending on the situation of border, do not limit herein.
Further, in the specific implementation, in the detection method of above-mentioned panel provided in an embodiment of the present invention, to array
The process conditions of substrate are improved, and are specifically included：
The technological parameter of gate insulating layer, active layer, passivation layer or ohmic contact layer in adjustment array substrate.Such as
During fast deposition gate insulating layer, increase ammonia, it is possible to reduce internal flaw, or power is reduced, film can be improved
Matter (density of film is big)；During fast deposition a-Si active layers, thickness thinning can improve film quality, and a-Si is illuminated by the light
Influence it is small, or increase pressure, passivation layer interfacial state can be improved；During forming N+ Ohmic contact layer patterns, reduce
Power is etched, the time is increased, increases SF6Gas, can improve N+ ohmic contact layers etching homogeneity, and improvement is contacted with passivation layer
Face, etc..Certainly, the technological parameter of the film layer in array substrate is adjusted, includes not only the above-mentioned film layer enumerated, or its
Its film layer can not limit herein depending on actual conditions.
Based on same inventive concept, the embodiment of the present invention additionally provides a kind of above-mentioned panel provided in an embodiment of the present invention
Detecting system, including：
Test cell determines in test sample group defect occur for carrying out high temperature reliability test to test sample group
Panel；Test sample group is the index plane board group for including uncut multiple panels；
Determination unit obtains the motherboard for including multiple array substrates, according to array for being disassembled test sample group
The grid cut-off voltage value of the TFT of substrate, determine there is the TFT of array substrate in the panel of defect with grid cut-off voltage value
Corresponding leakage current value；
Judging unit, be used for if it is determined that the leakage current value and predetermined standard off-state current value between difference
Less than or equal to given threshold, judge that the TFT of array substrate in the test sample group is qualified；If it is not, then judging the test
The TFT of array substrate is not qualified in sample sets.
Detecting system provided in an embodiment of the present invention can judge mark in time before module is not made in index plane board group
Whether the TFT of array substrate is qualified in quasi- panel group, has saved the time of manufacturing process, and reduces cost..
In the specific implementation, in the detecting system of above-mentioned panel provided in an embodiment of the present invention, test cell is specific to use
All array substrates load grid open signal in test sample group；All pixels point in test sample group is lit
When, control temperature rise to predetermined temperature determines that the panel for occurring bad phenomenon during temperature rise is used as and lacks
Sunken panel.
In the specific implementation, in the detecting system of above-mentioned panel provided in an embodiment of the present invention, determination unit is specific to use
Test point in the display panel to there is defect in array substrate carries out TFT characteristic curve tests；Test point is arranged in battle array
The non-display area of row substrate and include TFT identical with display area and the TFT shapes of gate driving circuit；According to array base
The grid cut-off voltage value of the TFT of plate determines array substrate in the panel for defect occur in obtained TFT characteristic curves
The leakage current value corresponding with grid cut-off voltage value of TFT.
The detection method and its detecting system of a kind of panel provided in an embodiment of the present invention, this method include：To test specimens
Product group carries out high temperature reliability test, determines occur the panel of defect in test sample group；Test sample group be include not cutting
Multiple panels index plane board group；Test sample group is disassembled to obtain the motherboard for including multiple array substrates, according to battle array
The grid cut-off voltage value of the TFT of row substrate, determine occur array substrate in the panel of defect TFT's and grid cut-off voltage
It is worth corresponding leakage current value；If it is determined that leakage current value and predetermined standard off-state current value between difference be less than or wait
In given threshold, judge that the TFT of array substrate is qualified；If it is not, then judging not qualified.Method provided in an embodiment of the present invention can be with
Before module is not made in index plane board group, whether the TFT of array substrate is qualified in timely criterion panel group, saves
The time of manufacturing process, and reduce cost.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
God and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (12)
1. a kind of detection method of panel, which is characterized in that including：
High temperature reliability test is carried out to test sample group, determines in the test sample group panel of defect occur；The survey
Test agent group is the index plane board group for including uncut multiple panels；The temperature range setting of the high temperature reliability test exists
Between 50 degrees Celsius to 70 degrees Celsius；
The test sample group is disassembled to obtain the motherboard for including multiple array substrates, according to the grid of the TFT of array substrate
Pole cutoff voltage value determines that the TFT's of array substrate in the panel for defect occur is corresponding with the grid cut-off voltage value
Leakage current value；
If it is determined that the leakage current value and predetermined standard off-state current value between difference be less than or equal to setting threshold
Value judges that the TFT of array substrate in the test sample group is qualified；If it is not, then judging array substrate in the test sample group
TFT it is not qualified.
2. the method as described in claim 1, which is characterized in that according to the grid cut-off voltage value of the TFT of the array substrate,
It determines the leakage current value corresponding with the grid cut-off voltage value of the TFT of array substrate in the panel for defect occur, has
Body includes：
TFT characteristic curve tests are carried out to the test point in array substrate in the panel for defect occur；The test point is set
It sets the non-display area in the array substrate and includes TFT identical with display area and the TFT shapes of gate driving circuit；
According to the grid cut-off voltage value of the TFT of the array substrate, described lack is determined in obtained TFT characteristic curves
The leakage current value corresponding with the grid cut-off voltage value of the TFT of array substrate in sunken panel.
3. the method as described in claim 1, which is characterized in that determine in test sample group defect occur using following manner
Panel：
Grid open signal is loaded to all array substrates in the test sample group；
When all pixels point in the test sample group is lit, control temperature rise to predetermined temperature is determined in temperature
Occurs the panel of bad phenomenon during rising as there is the panel of defect.
4. method as claimed in claim 3, which is characterized in that load grid to all array substrates in the test sample group
Open signal specifically includes：
Pass through the enabling signal end pair being electrically connected with all array substrates being arranged in the neighboring area of the test sample group
All array substrates load grid open signal；Or,
Grid open signal is loaded to all array substrates respectively.
5. the method as described in claim 1, which is characterized in that determine standard off-state current value using following manner：
TFT characteristic curve tests are carried out to not occurring the test point in the panel of defect in array substrate；The test point setting
The array substrate non-display area and include TFT identical with display area and the TFT shapes of gate driving circuit；
According to the grid cut-off voltage value of the TFT of the array substrate, do not occur described in determination in obtained TFT characteristic curves
The leakage current value corresponding with the grid cut-off voltage value of the TFT of array substrate is as standard off-state current in the panel of defect
Value.
6. the method as described in claim 1, which is characterized in that judge that the TFT of array substrate in the test sample group is not closed
When lattice, the TFT designs or process conditions of the array substrate are improved, and remake test sample group and be detected directly
TFT to all array substrates in improved test sample group is qualified.
7. method as claimed in claim 6, which is characterized in that the TFT designs of array substrate are improved, and are specifically included：
Adjust the position correspondence of the grid and active layer of each TFT in array substrate；Or,
Adjust the size of active layer.
8. method as claimed in claim 6, which is characterized in that the process conditions of array substrate are improved, and are specifically included：
The technological parameter of gate insulating layer, active layer, passivation layer or ohmic contact layer in adjustment array substrate.
9. the method as described in claim 1, which is characterized in that the given threshold is 15pA.
10. a kind of detecting system of panel, which is characterized in that including：
Test cell determines in the test sample group defect occur for carrying out high temperature reliability test to test sample group
Panel；The test sample group is the index plane board group for including uncut multiple panels；The high temperature reliability test
Temperature range is arranged between 50 degrees Celsius to 70 degrees Celsius；
Determination unit obtains the motherboard for including multiple array substrates, according to described for being disassembled the test sample group
The grid cut-off voltage value of the TFT of array substrate is determining the TFT of array substrate in the panel for defect occur with the grid
The corresponding leakage current value of pole cutoff voltage value；
Judging unit, for if it is determined that the leakage current value and predetermined standard off-state current value between difference be less than
Or it is equal to given threshold, judge that the TFT of array substrate in the test sample group is qualified；If it is not, then judging the test sample
The TFT of array substrate is not qualified in group.
11. detecting system as claimed in claim 10, which is characterized in that test cell is specifically used for the test sample
All array substrates load grid open signal in group；
When all pixels point in the test sample group is lit, control temperature rise to predetermined temperature is determined in temperature
Occurs the panel of bad phenomenon during rising as there is the panel of defect.
12. detecting system as claimed in claim 11, which is characterized in that determination unit, specifically for there is the face of defect
Test point in plate in array substrate carries out TFT characteristic curve tests；The test point is arranged in the non-aobvious of the array substrate
Show region and includes TFT identical with display area and the TFT shapes of gate driving circuit；
It is determining in obtained TFT characteristic curves defect occur according to the grid cut-off voltage value of the TFT of the array substrate
The leakage current value corresponding with the grid cut-off voltage value of the TFT of array substrate in panel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610173568.2A CN105589234B (en) | 2016-03-24 | 2016-03-24 | A kind of detection method and its detecting system of panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610173568.2A CN105589234B (en) | 2016-03-24 | 2016-03-24 | A kind of detection method and its detecting system of panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105589234A CN105589234A (en) | 2016-05-18 |
| CN105589234B true CN105589234B (en) | 2018-09-11 |
Family
ID=55928929
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610173568.2A Expired - Fee Related CN105589234B (en) | 2016-03-24 | 2016-03-24 | A kind of detection method and its detecting system of panel |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105589234B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107134269B (en) * | 2017-07-03 | 2020-11-10 | 京东方科技集团股份有限公司 | Gate drive circuit, gate drive method, array substrate and display device |
| CN107402462B (en) * | 2017-09-21 | 2020-06-05 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and control method |
| CN109979843B (en) * | 2019-04-09 | 2021-04-13 | 德淮半导体有限公司 | Apparatus and method for verifying pattern shifts in a layout |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5786707A (en) * | 1995-12-07 | 1998-07-28 | Sharp Kabushiki Kaisha | Method of detecting possible defect of liquid crystal panel |
| JP2008034141A (en) * | 2006-07-26 | 2008-02-14 | Denso Corp | Heater device, and vehicular liquid crystal display device equipped with heater device |
| CN103091918A (en) * | 2013-01-18 | 2013-05-08 | 北京京东方光电科技有限公司 | Array substrate, display device of array substrate and detection method of array substrate |
| CN104062777A (en) * | 2013-03-22 | 2014-09-24 | 深圳市海洋王照明工程有限公司 | Bright line defect testing method for TFT-LCD (thin film transistor liquid crystal display) screen |
| CN105116573A (en) * | 2015-09-24 | 2015-12-02 | 京东方科技集团股份有限公司 | Method for detecting array substrates |
-
2016
- 2016-03-24 CN CN201610173568.2A patent/CN105589234B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5786707A (en) * | 1995-12-07 | 1998-07-28 | Sharp Kabushiki Kaisha | Method of detecting possible defect of liquid crystal panel |
| JP2008034141A (en) * | 2006-07-26 | 2008-02-14 | Denso Corp | Heater device, and vehicular liquid crystal display device equipped with heater device |
| CN103091918A (en) * | 2013-01-18 | 2013-05-08 | 北京京东方光电科技有限公司 | Array substrate, display device of array substrate and detection method of array substrate |
| CN104062777A (en) * | 2013-03-22 | 2014-09-24 | 深圳市海洋王照明工程有限公司 | Bright line defect testing method for TFT-LCD (thin film transistor liquid crystal display) screen |
| CN105116573A (en) * | 2015-09-24 | 2015-12-02 | 京东方科技集团股份有限公司 | Method for detecting array substrates |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105589234A (en) | 2016-05-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10288655B2 (en) | Touch structure, test method thereof, touch panel and display apparatus | |
| CN105589234B (en) | A kind of detection method and its detecting system of panel | |
| CN106098007B (en) | Liquid crystal display panel and its control method | |
| CN103197478B (en) | A kind of array base palte and liquid crystal indicator | |
| CN103676354B (en) | Electrode structure and preparation method, array base palte and preparation method and display device | |
| CN106409199B (en) | The test method of test system for display panel and display panel | |
| CN102243443A (en) | Detection method for pattern offset between exposure areas and test pattern | |
| CN109188812A (en) | A kind of array substrate, its test method, display panel and display device | |
| WO2006062812A2 (en) | Line short localization in lcd pixel arrays | |
| CN106773426A (en) | Array base palte test circuit and preparation method thereof, display panel | |
| CN110221468A (en) | Display panel and its temperature-compensation method, display device | |
| CN104090389A (en) | Test element group, array substrate, display device and testing method | |
| US9638943B2 (en) | LCD panel and manufacturing method thereof | |
| CN109839767A (en) | A kind of array substrate, display panel and display device | |
| CN107123655B (en) | A kind of array substrate and preparation method thereof, detection method and display device | |
| WO2019119591A1 (en) | Method for catching leaky pixel of display panel, and display panel | |
| CN105116573B (en) | A kind of detection method of array base palte | |
| CN101515442B (en) | Peripheral circuit | |
| CN101846828A (en) | Active component array substrate and liquid crystal display panel | |
| CN107463015B (en) | Double-data-line testing method, circuit and manufacturing method, array substrate and display device | |
| CN202870441U (en) | Array substrate, display device and line width measuring device | |
| CN106782254A (en) | Array base palte test circuit and preparation method thereof | |
| CN108169972A (en) | Array substrate and its driving method, display device | |
| CN104091804B (en) | A kind of array base palte and preparation method thereof, display device | |
| CN108417507A (en) | A kind of measurement method of thin film transistor (TFT) and array substrate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20180911 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |