CN105578714A - A new laminate structure of multi-layer high-speed PCB and signal via hole optimization method - Google Patents

Abstract

The invention relates to a novel lamination structure of a multilayer high-speed PCB. The novel lamination structure comprises multiple layers of ground planes, power supply planes arranged between every two adjacent ground planes, and two layers of signal planes arranged on the top layer and the bottom layer of a PCB, which are up-down successively arranged. Spaces between the power supply planes and adjacent two layers of ground planes are filled with medium. Each of the signal planes arranged on the top layer and the bottom layer of the PCB comprises a weld disc and a microstrip line. A signal via hole is arranged in each of the weld discs. The microstrip lines are connected together via the signal via holes. N grounding short circuit holes are uniformly arranged around each of the signal via hole. According to the invention, the grounding short circuit holes can provide ideal low-impedance returning paths for the signal via holes, and parasitic parameters of current paths among the planes are reduced.

Description

A new laminate structure of multi-layer high-speed PCB and signal via hole optimization method

technical field

The invention relates to the field of signal via impedance consistency control, and more specifically, relates to a novel laminated structure of a multilayer high-speed PCB and a signal via hole optimization method.

Background technique

With the development of semiconductor technology towards high speed and high density, the speed and bandwidth of high-speed PCB interconnection system are getting bigger and bigger, and the signal integrity problems caused by it are getting more and more serious. The signal integrity problem of high-speed PCB directly restricts the performance of the product, and is also a key issue in the actual product design process. Now most of the communication equipment is the so-called high-density interconnect (HDI) system, and the functions integrated on the PCB board More and more, the layout and wiring density is quite large, and the signal integrity problem faced is more severe. The application of high-speed serdes with numbers of 10G+ puts forward strict requirements on the signal integrity of high-speed PCB.

The reflection problem of a single network is a major problem of signal integrity (SI) problems. As a signal propagates along a transmission line, each step in its path has a corresponding transient impedance. If the impedance of the interconnection line is controllable, then the transient impedance is equal to the characteristic impedance of the line. Whatever causes the transient impedance to change, part of the signal will be reflected in the opposite direction from the original propagation direction, while another part will continue to propagate, but with a changed amplitude. The place where the transient impedance changes is called impedance mutation, which is the root cause of signal emission.

Via hole is a typical impedance discontinuity structure in PCB, but in the design process, it is inevitable to use via hole for signal layer change. The present invention proposes an optimization method for multi-layer high-speed PCB stacking methods and signal vias, by minimizing the impedance discontinuity of the vias, the influence of the impedance discontinuity of the vias on the signal link drop to lowest.

Contents of the invention

The laminated structure provided by the present invention is used to solve the signal integrity problem caused by the impedance discontinuity of the signal via hole to the link of the high-speed PCB, thereby improving the SI performance of the PCB and better serving product design.

For realizing above-mentioned purpose of the invention, the technical scheme that adopts is:

A new laminated structure of multi-layer high-speed PCB, including multi-layer ground planes arranged sequentially from top to bottom, power planes arranged between adjacent two-layer ground planes, and two-layer signal layers arranged on the top and bottom layers of the PCB respectively plane, the power plane and the two adjacent ground planes are filled with a medium with a thickness of no more than 0.1mm; the two-layer signal planes arranged on the top and bottom layers of the PCB include pads and microstrip lines, and signal via holes are opened On the pad, the microstrip lines on the top layer and the bottom layer of the PCB are connected through signal via holes, and N grounding short-circuit holes are uniformly arranged around the signal via holes.

In the above solution, all power planes are only used for power supply, each power plane is sandwiched by two ground planes, and all signal layers are separated by ground planes, which makes each signal plane have a good reference plane, improving The power integrity (PI) performance of the power distribution network (PDN), and evenly setting N grounding short-circuit holes around the signal vias, can provide low-impedance loop paths for the signal vias and reduce the parasitic parameters of the current path between planes .

Preferably, the N=4.

Preferably, an anti-pad is provided on the ground plane or the power plane.

Preferably, the thickness of the medium filled between the power supply plane and the upper ground plane and the lower ground plane is 0.05 mm and 0.1 mm, respectively.

Preferably, the radius of the signal via hole is 0.15 mm, the radius of the anti-pad is 0.4 mm, the radius of the pad is 0.25 mm, and the distance from the ground short-circuit hole to the signal via hole is 1 mm.

At the same time, the present invention also provides a method for optimizing signal vias based on the above laminated structure, the specific scheme of which is as follows:

Include the following steps:

S1. Establish a three-dimensional parasitic parameter extraction model according to the physical size of the new laminated structure;

S2. Extract the parasitic inductance L and parasitic capacitance C of the signal via through the three-dimensional parasitic parameter extraction model, and calculate the characteristic impedance of the signal via according to the parasitic inductance L and parasitic capacitance C;

S3. Determine whether the characteristic impedance of the signal via hole is 50Ω, if so, skip to step S4, otherwise adjust the anti-pad radius parameter, pad radius parameter, signal via hole radius parameter, distance parameter between the grounding short-circuit hole and the signal via hole, And re-execute step S2;

S4. Output signal via hole radius parameters, anti-pad radius parameters, pad radius parameters, distance parameters between the grounding short-circuit hole and the signal via hole;

S5. Perform simulation in the full-wave simulation software according to the parameters output in step S4, calculate S parameters, and analyze frequency domain results to ensure that the transmission performance of the signal via hole is optimized.

Compared with prior art, the beneficial effect of the present invention is:

Compared with the scheme of adding decoupling capacitors around the signal via holes, the stacked structure proposed by the present invention has obvious advantages. Since the impedance introduced by the series inductance of the decoupling capacitor becomes very large at high frequencies, increasing the capacitance of the decoupling capacitor cannot effectively provide a return path for the high-speed current. The more effective way to control the return current is to add a ground short-circuit hole near the signal via. The ground short-circuit hole can provide an ideal low-impedance return path for the signal via and reduce the parasitic parameters of the current path between planes.

Description of drawings

Figure 1 is a side view of the laminated structure in the full-wave simulation software experiment.

Fig. 2 is a top view of the laminated structure in the full-wave simulation software experiment.

FIG. 3 is a flowchart of a signal via optimization method.

Fig. 4 is a top view of the laminated structure generated by the three-dimensional parasitic parameter extraction model.

Figure 5 is a side view of a PCB stackup without optimized signal vias.

Fig. 6 is the insertion loss curve of the optimized signal via hole.

Fig. 7 shows the insertion loss curve of the signal via without optimization.

detailed description

The accompanying drawings are for illustrative purposes only and cannot be construed as limiting the patent;

The present invention will be further elaborated below in conjunction with the accompanying drawings and embodiments.

Example 1

The invention provides a novel multi-layer high-speed PCB laminate design and proposes a multi-layer high-speed PCB signal via optimization method with wide applicability on the basis of the laminate.

The main feature of the high-speed multi-layer PCB stacking scheme provided by the present invention is that all power planes are only used for power supply, each power plane is sandwiched by two ground planes with a thin medium, and all signal layers are separated by ground planes , so that each signal layer has a good reference plane, and four short-circuit holes (ground holes) are evenly placed around the signal via hole to provide a low-impedance return path for the signal via hole.

On the basis of this stack, by optimizing the parameters such as pad radius, via hole radius, anti-pad radius, and the distance from the short-circuit hole to the signal via hole, a performance optimization scheme for signal vias is proposed through repeated iterative optimization.

The optimization scheme mainly includes: according to the actual application scenario, according to the physical size of the corresponding single-board via, establish a parasitic parameter model, place the position of the short-circuit hole, and extract the parasitic inductance L and Parasitic capacitance C, according to the formula for calculating the characteristic impedance of the via Determine whether the impedance of the via is 50Ω. If it is not 50Ω, continue to optimize the via parameters so that the impedance of the via is 50Ω, reducing the discontinuity of the link impedance caused by the via. Reducing the distance between the short-circuit hole and the signal via hole, increasing the radius of the signal via hole, pad and short-circuit hole, and reducing the radius of the anti-pad can reduce the characteristic impedance of the via hole, and vice versa, the impedance increases. If the impedance of the via is 50Ω, perform a full-wave simulation in the full-wave simulation software with the same via design size, calculate the S parameters, and observe the frequency domain results.

The stack thickness of the power supply layer of the new stack structure is 0.05mm (t1) and 0.1mm (t2), the dielectric material is common FR4, each signal layer has a complete reference plane, and the SI performance of the whole board is obtained. Nice boost.

Perform simulation in the full-wave simulation software and analyze the results in the frequency domain to ensure the correctness of the conclusion on signal via transmission performance optimization. According to the parasitic L and C parameters extracted by the three-dimensional parasitic parameter extraction software, the calculated characteristic impedance is 50Ω, and the insertion loss curve (S21) obtained by modeling with the same via and stack parameters in the full-wave simulation software is approximately a slope Wire.

Compared with the scheme of adding decoupling capacitors around the signal via holes, the stacked structure proposed by the present invention has obvious advantages. Since the impedance introduced by the series inductance of the decoupling capacitor becomes very large at high frequencies, increasing the capacitance of the decoupling capacitor cannot effectively provide a return path for the high-speed current. The more effective way to control the return current is to add a ground short-circuit hole near the signal via. The ground short-circuit hole can provide an ideal low-impedance return path for the signal via and reduce the parasitic parameters of the current path between planes.

Example 2

The schematic diagrams of the multi-layer high-speed PCB stacked in this embodiment are shown in Figures 1 and 2, and four short-circuit holes (ground holes) are evenly placed around the signal via holes. The lamination thicknesses in Fig. 1 are respectively: t1=0.05mm, t2=0.1mm, t3=1mm. First, establish a three-dimensional parasitic parameter extraction model according to the stack diagram shown in Figure 1 and the size of the top view shown in Figure 4. The size of the PCB in the established three-dimensional parasitic parameter extraction model is: 18mm*20mm, and the length of the microstrip line is: 1mm. Set the solution frequency to 5GHz, repeatedly optimize parameters such as pad radius, via hole radius, anti-pad radius, distance from short-circuit hole to signal via hole, and iteratively optimize, according to the characteristic impedance calculation formula Calculate impedance. After actual calculation and optimization, on the basis of the model established above, a set of optimal physical parameters of vias are obtained: via-r = 0.15mm, antipad radius antipad-r = 0.40mm, via-hole welding Disk radius viapad-r=0.25mm, distance from short circuit hole to signal via hole d=1mm. When this set of parameters is taken, the characteristic impedance of the via hole is 50Ω. In the second step, according to the via parameters and short-circuit hole parameters optimized in the 3D parasitic parameter extraction software, in the full-wave simulation software, follow the stacking method in Figure 1, and follow the circuit board size and microstrip line length in the top view of Figure 2 Establish the full-wave simulation model of the full-wave simulation software. The size of the PCB is: 36mm*40mm, the length of the microstrip line is: 16mm, and the physical parameters of the signal vias and short-circuit holes are optimized in the 3D parasitic parameter extraction software: vias Radius via-r=0.15mm, antipad radius antipad-r=0.40mm, via pad radius viapad-r=0.25mm, distance from short circuit hole to signal via hole d=1mm. Set the port mode, solve and sweep the frequency, and get the via insertion loss curve shown in Figure 6 through simulation. It can be seen from the figure that the curve is approximately a slanted line, indicating that the signal via optimization result has good performance in the frequency domain. . At the same time, a full-wave simulation software simulation model without hole optimization was established according to the PCB size and microstrip line length shown in Figure 2 and the stackup in Figure 5, and the S21 curve shown in Figure 7 was obtained. From the curve, It can be seen that the frequency domain performance of vias is extremely poor. From this comparison, it can be seen that the transmission performance of signal vias has been significantly improved by adopting the stacking scheme and via optimization scheme proposed in this embodiment.

The above is only a preferred embodiment of this embodiment, and is not limited to this embodiment. For those skilled in the art, the signal via optimization method proposed in this embodiment can be generally used in other application scenarios In other PCBs where vias are applied, excellent via transmission performance can still be obtained according to the optimization method and steps proposed in this embodiment. The stacking scheme proposed in this embodiment can also be widely applied to the scene of power supply noise suppression and promotion of power distribution network (PDN).

Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (6)

1. the novel laminated structure of a multiple layer high speed PCB, it is characterized in that: comprise set gradually from top to bottom multilayer ground level, be arranged on the power plane between adjacent two layers ground level and be separately positioned on the two-layer signal plane of PCB top layer and bottom, be filled with the medium that thickness is no more than 0.1mm between described power plane and adjacent two layers ground level; The two-layer signal plane of the described PCB of being arranged on top layer, bottom comprises pad and microstrip line, signal via is opened on pad, the microstrip line of described PCB top layer, bottom is connected by signal via, and the surrounding of described signal via is evenly provided with N number of ground short circuit hole.

2. the novel laminated structure of multiple layer high speed PCB according to claim 1, is characterized in that: described N=4.

3. the novel laminated structure of multiple layer high speed PCB according to claim 2, is characterized in that: described ground level or power plane are provided with anti-pad.

4. the novel laminated structure of multiple layer high speed PCB according to claim 2, is characterized in that: the thickness of the medium of filling between described power plane and top ground level, below ground level is respectively 0.05mm, 0.1mm.

5. the novel laminated structure of multiple layer high speed PCB according to claim 3, is characterized in that: the radius of described signal via is 0.15mm, and anti-pad radius is 0.4mm, and pad radius is 0.25mm, and ground short circuit hole is 1mm to the distance of signal via.

6. the signal via optimization method of the novel laminated structure of multiple layer high speed PCB according to any one of Claims 1 to 5, is characterized in that: comprise the following steps:

S1. according to the physical size of novel laminated structure, three-dimensional parasitic parameter extraction model is set up;

S2. by stray inductance L and the parasitic capacitance C of three-dimensional parasitic parameter extraction model extraction signal via, the characteristic impedance of signal via is calculated according to stray inductance L and parasitic capacitance C;

Whether the characteristic impedance S3. judging signal via is 50 Ω, if so, jumps to step S4, otherwise the distance parameter of adjustment anti-pad radius parameter, pad radius parameter, signal via radius parameter, ground short circuit hole and signal via, and re-execute step S2;

S4. via hole radius parameter, anti-pad radius parameter, pad radius parameter, distance parameter between ground short circuit hole and signal via is outputed signal;

S5. the parameter exported according to step S4 emulates in full-wave simulation software, calculates S parameter, analyzes frequency-domain result, to guarantee that the transmission performance of signal via is optimized.