CN105578714A - Novel lamination structure of multilayer high-speed PCB and signal via-hole optimization method - Google Patents
Novel lamination structure of multilayer high-speed PCB and signal via-hole optimization method Download PDFInfo
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- CN105578714A CN105578714A CN201510926116.2A CN201510926116A CN105578714A CN 105578714 A CN105578714 A CN 105578714A CN 201510926116 A CN201510926116 A CN 201510926116A CN 105578714 A CN105578714 A CN 105578714A
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- 238000005457 optimization Methods 0.000 title claims description 18
- 238000000034 method Methods 0.000 title claims description 12
- 238000003475 lamination Methods 0.000 title abstract description 11
- 230000003071 parasitic effect Effects 0.000 claims abstract description 22
- 238000000605 extraction Methods 0.000 claims description 9
- 230000005540 biological transmission Effects 0.000 claims description 6
- 238000010276 construction Methods 0.000 description 8
- 239000003990 capacitor Substances 0.000 description 6
- 238000003780 insertion Methods 0.000 description 4
- 230000037431 insertion Effects 0.000 description 4
- 239000011148 porous material Substances 0.000 description 4
- 230000001052 transient effect Effects 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 238000012938 design process Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012913 prioritisation Methods 0.000 description 2
- 230000000644 propagated effect Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/0929—Conductive planes
- H05K2201/093—Layout of power planes, ground planes or power supply conductors, e.g. having special clearance holes therein
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention relates to a novel lamination structure of a multilayer high-speed PCB. The novel lamination structure comprises multiple layers of ground planes, power supply planes arranged between every two adjacent ground planes, and two layers of signal planes arranged on the top layer and the bottom layer of a PCB, which are up-down successively arranged. Spaces between the power supply planes and adjacent two layers of ground planes are filled with medium. Each of the signal planes arranged on the top layer and the bottom layer of the PCB comprises a weld disc and a microstrip line. A signal via hole is arranged in each of the weld discs. The microstrip lines are connected together via the signal via holes. N grounding short circuit holes are uniformly arranged around each of the signal via hole. According to the invention, the grounding short circuit holes can provide ideal low-impedance returning paths for the signal via holes, and parasitic parameters of current paths among the planes are reduced.
Description
Technical field
The present invention relates to signal via impedance consistency control field, more specifically, relate to novel laminated structure and the signal via optimization method of a kind of multiple layer high speed PCB.
Background technology
Along with semiconductor technology is towards high speed, high-density development, speed and the bandwidth of High-Speed PCB interconnection system are increasing, and the problems of Signal Integrity brought thus is more and more serious.The problems of Signal Integrity of High-Speed PCB directly governs the performance of product, also be the critical problem in actual product design process, present most communication equipment is all so-called highly dense interconnection (HDI) system, function integrated on pcb board gets more and more, placement-and-routing's density is all quite large, the problems of Signal Integrity faced is severeer, and the application of the high speed serdes of number 10G+, proposes strict requirement to the signal integrity of High-Speed PCB more.
The reflection problems of single network is the subject matter of signal integrity (SI) problem, and when signal is propagated along transmission line, on its path, each step has corresponding transient impedance.If the impedance of interconnection line is controlled, so transient impedance just equals the characteristic impedance of line.Whatsoever reason makes transient impedance there occurs change, and part signal reflects along the direction contrary with the former direction of propagation, and continuation is propagated by another part, but amplitude changes to some extent.The place changed by transient impedance is called change in the instantaneous impedance, and change in the instantaneous impedance is the basic reason that signal occurs to launch.
Via hole is more typical a kind of impedance discontinuity structure in PCB, but in the design process, signal changes layer and inevitably uses via hole again.The present invention proposes a kind of for the stacked system of multiple layer high speed PCB and the optimization method of signal via, by the impedance discontinuity of via hole is dropped to minimum, makes the impedance discontinuity due to via hole drop to minimum on the impact that signal link causes.
Summary of the invention
The problems of Signal Integrity that laminated construction provided by the invention brings for the link of impedance discontinuity to High-Speed PCB solved due to signal via, thus the SI performance promoting PCB, service product design better.
For realizing above goal of the invention, the technical scheme of employing is:
The novel laminated structure of a kind of multiple layer high speed PCB, comprise set gradually from top to bottom multilayer ground level, be arranged on the power plane between adjacent two layers ground level and be separately positioned on the two-layer signal plane of PCB top layer and bottom, be filled with the medium that thickness is no more than 0.1mm between described power plane and adjacent two layers ground level; The two-layer signal plane of the described PCB of being arranged on top layer, bottom comprises pad and microstrip line, signal via is opened on pad, the microstrip line of described PCB top layer, bottom is connected by signal via, and the surrounding of described signal via is evenly provided with N number of ground short circuit hole.
In such scheme, all power plane are only used to power supply, each power plane is clipped in the middle by two ground levels, all signals layers are all separated by ground level, this makes each signal plane have good reference planes, promotes Power Integrity (PI) performance of power distribution network (PDN), and evenly arranges N number of ground short circuit hole in signal via surrounding, then can provide low-impedance loop path to signal via, reduce the parasitic parameter of interplanar current path.
Preferably, described N=4.
Preferably, described ground level or power plane are provided with anti-pad.
Preferably, the thickness of the medium of filling between described power plane and top ground level, below ground level is respectively 0.05mm, 0.1mm.
Preferably, the radius of described signal via is 0.15mm, and anti-pad radius is 0.4mm, and pad radius is 0.25mm, and ground short circuit hole is 1mm to the distance of signal via.
Meanwhile, present invention also offers a kind of signal via optimization method based on above laminated construction, its concrete scheme is as follows:
Comprise the following steps:
S1. according to the physical size of novel laminated structure, three-dimensional parasitic parameter extraction model is set up;
S2. by stray inductance L and the parasitic capacitance C of three-dimensional parasitic parameter extraction model extraction signal via, the characteristic impedance of signal via is calculated according to stray inductance L and parasitic capacitance C;
Whether the characteristic impedance S3. judging signal via is 50 Ω, if so, jumps to step S4, otherwise the distance parameter of adjustment anti-pad radius parameter, pad radius parameter, signal via radius parameter, ground short circuit hole and signal via, and re-execute step S2;
S4. via hole radius parameter, anti-pad radius parameter, pad radius parameter, distance parameter between ground short circuit hole and signal via is outputed signal;
S5. the parameter exported according to step S4 emulates in full-wave simulation software, calculates S parameter, analyzes frequency-domain result, to guarantee that the transmission performance of signal via is optimized.
Compared with prior art, the invention has the beneficial effects as follows:
Relative to the scheme of adding decoupling capacitor in signal via surrounding, the laminated construction that the present invention proposes has obvious advantage.The impedance introduced due to the series inductance of decoupling capacitor becomes very large at high frequency, and the capacitance of now employing increasing decoupling capacitor can not effectively for high speed electric current provides return path.Control return current comparatively effective method adds ground short circuit hole exactly near signal via, and ground short circuit hole can provide desirable Low ESR return path for signal via, reduces the parasitic parameter of interplanar current path.
Accompanying drawing explanation
Fig. 1 is the end view of the laminated construction in full-wave simulation software experimentation.
Fig. 2 is the vertical view of the laminated construction in full-wave simulation software experimentation.
Fig. 3 is the flow chart of signal via optimization method.
Fig. 4 is the vertical view of the laminated construction of three-dimensional parasitic parameter extraction model generation.
Fig. 5 is that signal via is not through the end view of the PCB laminated construction of optimization.
Fig. 6 is the signal via Insertion Loss curve of signal via after optimizing.
Fig. 7 is the signal via Insertion Loss curve of signal via not through optimizing.
Embodiment
Accompanying drawing, only for exemplary illustration, can not be interpreted as the restriction to this patent;
Below in conjunction with drawings and Examples, the present invention is further elaborated.
Embodiment 1
The invention provides a kind of novel multiple layer high speed PCB stack-design and on the basis of this lamination, propose the optimization method of a kind of applicability multiple layer high speed PCB signal via widely.
The all exactly power plane of main feature of high speed multi-layer PCB lamination scheme provided by the invention are only used to power supply, each power plane is clipped in the middle by very thin medium by two ground levels, all signals layers are all separated by ground level, each signals layer is made to have good reference planes, evenly place four short circuit hole (hole) in signal via surrounding, provide low-impedance loop path to signal via.
On the basis of this lamination, by optimizing pad radius, cross pore radius, anti-pad radius, short circuit hole is to the parameter such as distance of signal via, and iterate optimization, proposes a kind of performance optimization scheme of signal via.
This prioritization scheme mainly comprises: according to practical application scene, according to the physical size of corresponding veneer via hole, set up parasitic parameter model, and the position of short circuit hole is put well, stray inductance L and the parasitic capacitance C of via hole is extracted, according to the characteristic impedance computing formula of via hole by three-dimensional parasitic parameter extraction software
judge whether through hole impedance is 50 Ω, if be not that 50 Ω continuation optimization via parameters make through hole impedance be 50 Ω, reduce the link impedance discontinuity due to via hole introducing.Reduce the spacing of short circuit hole and signal via, increase the radius of signal via, pad and short circuit hole, minimizing anti-pad radius can make the characteristic impedance of via hole reduce, otherwise impedance increases.If the impedance of via hole is 50 Ω, then in full-wave simulation software, carry out full-wave simulation with identical Via Design size, calculating S parameter, observe frequency-domain result.
The laminated thickness of the power supply layer of novel laminated structure is respectively 0.05mm (t1) and 0.1mm (t2), and dielectric material is common FR4, and each signals layer has complete reference planes, and the SI performance of whole plate is well promoted.
Emulate in full-wave simulation software, analyze frequency-domain result, to guarantee the correctness of signal via transmission performance optimization conclusion.According to parasitic L, C parameter that three-dimensional parasitic parameter extraction software extracts, the characteristic impedance calculated is 50 Ω, and the Insertion Loss curve (S21) obtained with same via hole and stacked parameter model in full-wave simulation software is approximately an oblique line.
Relative to the scheme of adding decoupling capacitor in signal via surrounding, the laminated construction that the present invention proposes has obvious advantage.The impedance introduced due to the series inductance of decoupling capacitor becomes very large at high frequency, and the capacitance of now employing increasing decoupling capacitor can not effectively for high speed electric current provides return path.Control return current comparatively effective method adds ground short circuit hole exactly near signal via, and ground short circuit hole can provide desirable Low ESR return path for signal via, reduces the parasitic parameter of interplanar current path.
Embodiment 2
The schematic diagram of the lamination of the multiple layer high speed PCB that the present embodiment proposes as shown in Figure 1, 2, evenly places four short circuit hole (hole) in signal via surrounding.Laminated thickness in Fig. 1 is respectively: t1=0.05mm, t2=0.1mm, t3=1mm.First, set up three-dimensional parasitic parameter extraction model according to the vertical view size shown in the lamination schematic diagram shown in Fig. 1 and Fig. 4, in the three-dimensional parasitic parameter extraction model of foundation, PCB is of a size of: 18mm*20mm, microstrip line length is: 1mm.It is 5GHz that setting solves frequency, repeatedly optimizes pad radius, crosses pore radius, anti-pad radius, and short circuit hole is to the parameter such as distance of signal via, and iterate optimization, according to characteristic impedance computing formula
computing impedance.Through Practical Calculation optimization, on the basis of the model of above-mentioned foundation, the via hole physical parameter obtaining one group of the best is: cross pore radius via-r=0.15mm, anti-pad radius antipad-r=0.40mm, via pad radius viapad-r=0.25mm, short circuit hole is to signal via distance d=1mm.When getting this group parameter, the characteristic impedance of via hole is 50 Ω.Second step, according to optimizing the via parameters and short circuit hole parameter that obtain in three-dimensional parasitic parameter extraction software, according to the stacked system of Fig. 1 in full-wave simulation software, full-wave simulation software full-wave simulation model is set up according to the circuit board size of Fig. 2 vertical view and microstrip line length, PCB is of a size of: 36mm*40mm, microstrip line length is: 16mm, the physical parameter of signal via and short circuit hole to be in three-dimensional parasitic parameter extraction software to optimize and to obtain: cross pore radius via-r=0.15mm, anti-pad radius antipad-r=0.40mm, via pad radius viapad-r=0.25mm, short circuit hole is to signal via distance d=1mm.Arrange port mode, solve and swept frequency, emulation obtains the via hole Insertion Loss curve shown in Fig. 6, and as can be seen from the figure, curve approximation is an oblique line, shows that this signal via optimum results is functional at frequency domain.Meanwhile, establish according to the lamination of the PCB size shown in Fig. 2 and microstrip line length and Fig. 5 the full-wave simulation software phantom not doing via hole and optimize, obtain the S21 curve shown in Fig. 7, as can be seen from curve, via hole frequency domain representation extreme difference.Contrast can be found out thus, and the lamination scheme adopting the present embodiment to propose and via hole prioritization scheme, the transmission performance of signal via is significantly improved.
The foregoing is only the preferred embodiment of the present embodiment, be not limited in for the present embodiment, for a person skilled in the art, the signal via optimization method that the present embodiment proposes, generally can be used in the signal via optimization of other application scenarioss, be applied in the PCB of via hole at other, the optimization method proposed according to the present embodiment and step, still can obtain excellent via hole transmission performance.The lamination scheme that the present embodiment proposes also can be widely used in the scene that Power supply rejection promotes power distribution network (PDN).
Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. the novel laminated structure of a multiple layer high speed PCB, it is characterized in that: comprise set gradually from top to bottom multilayer ground level, be arranged on the power plane between adjacent two layers ground level and be separately positioned on the two-layer signal plane of PCB top layer and bottom, be filled with the medium that thickness is no more than 0.1mm between described power plane and adjacent two layers ground level; The two-layer signal plane of the described PCB of being arranged on top layer, bottom comprises pad and microstrip line, signal via is opened on pad, the microstrip line of described PCB top layer, bottom is connected by signal via, and the surrounding of described signal via is evenly provided with N number of ground short circuit hole.
2. the novel laminated structure of multiple layer high speed PCB according to claim 1, is characterized in that: described N=4.
3. the novel laminated structure of multiple layer high speed PCB according to claim 2, is characterized in that: described ground level or power plane are provided with anti-pad.
4. the novel laminated structure of multiple layer high speed PCB according to claim 2, is characterized in that: the thickness of the medium of filling between described power plane and top ground level, below ground level is respectively 0.05mm, 0.1mm.
5. the novel laminated structure of multiple layer high speed PCB according to claim 3, is characterized in that: the radius of described signal via is 0.15mm, and anti-pad radius is 0.4mm, and pad radius is 0.25mm, and ground short circuit hole is 1mm to the distance of signal via.
6. the signal via optimization method of the novel laminated structure of multiple layer high speed PCB according to any one of Claims 1 to 5, is characterized in that: comprise the following steps:
S1. according to the physical size of novel laminated structure, three-dimensional parasitic parameter extraction model is set up;
S2. by stray inductance L and the parasitic capacitance C of three-dimensional parasitic parameter extraction model extraction signal via, the characteristic impedance of signal via is calculated according to stray inductance L and parasitic capacitance C;
Whether the characteristic impedance S3. judging signal via is 50 Ω, if so, jumps to step S4, otherwise the distance parameter of adjustment anti-pad radius parameter, pad radius parameter, signal via radius parameter, ground short circuit hole and signal via, and re-execute step S2;
S4. via hole radius parameter, anti-pad radius parameter, pad radius parameter, distance parameter between ground short circuit hole and signal via is outputed signal;
S5. the parameter exported according to step S4 emulates in full-wave simulation software, calculates S parameter, analyzes frequency-domain result, to guarantee that the transmission performance of signal via is optimized.
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Cited By (12)
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| CN106793459A (en) * | 2016-12-20 | 2017-05-31 | 中国航空工业集团公司雷华电子技术研究所 | A kind of multiplayer microwave circuit board interconnection structure |
| CN107135606A (en) * | 2017-06-09 | 2017-09-05 | 郑州云海信息技术有限公司 | It is a kind of to improve the method for PCB Power Integrities using full cavity model |
| CN107623989A (en) * | 2017-10-24 | 2018-01-23 | 广东欧珀移动通信有限公司 | Printed circuit board (PCB) and mobile terminal |
| CN109558683A (en) * | 2018-12-03 | 2019-04-02 | 上海泽丰半导体科技有限公司 | A kind of data information input method and system based on Via Wizard software |
| CN111315120A (en) * | 2018-12-12 | 2020-06-19 | 三星电机株式会社 | Printed circuit board |
| CN112768936A (en) * | 2020-12-30 | 2021-05-07 | 深圳市信丰伟业科技有限公司 | Discrete 5G antenna isolation system |
| CN112770492A (en) * | 2019-10-18 | 2021-05-07 | 恒为科技（上海）股份有限公司 | Design method and system of high-speed signal via hole and storage medium |
| CN113068306A (en) * | 2021-04-26 | 2021-07-02 | Tcl通讯（宁波）有限公司 | PCB and PCB mounting method |
| CN114184933A (en) * | 2021-11-26 | 2022-03-15 | 浪潮(北京)电子信息产业有限公司 | Backflow ground hole detection method, system, device and computer readable storage medium |
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| CN115983189A (en) * | 2023-01-06 | 2023-04-18 | 中山大学 | Analog integrated circuit layout wiring method and system for self-adaptive grid |
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| CN106793459A (en) * | 2016-12-20 | 2017-05-31 | 中国航空工业集团公司雷华电子技术研究所 | A kind of multiplayer microwave circuit board interconnection structure |
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Application publication date: 20160511 |