CN114492291B

CN114492291B - Method and device for designing high-speed serial link, electronic equipment and storage medium

Info

Publication number: CN114492291B
Application number: CN202210352775.XA
Authority: CN
Inventors: 刘勇辉; 陈才; 王刚; 谢俊; 陈中意
Original assignee: Phytium Technology Co Ltd
Current assignee: Phytium Technology Co Ltd
Priority date: 2022-04-06
Filing date: 2022-04-06
Publication date: 2022-07-15
Anticipated expiration: 2042-04-06
Also published as: CN114492291A

Abstract

The application provides a design method and a device of a high-speed serial link, electronic equipment and a storage medium, wherein the method comprises the following steps: building a high-speed serial link model consisting of a transmission line model, a high-speed connector model and a via hole model; determining via hole parameters meeting design requirements by measuring the impedance of the high-speed serial link model under different via hole parameters; and/or determining the transmission line length meeting the design requirement according to the active simulation eye pattern of the high-speed serial link model in different transmission line lengths. The method can determine the structural parameters of the high-speed serial link meeting the design requirements in a model simulation mode, so that designers can be assisted to accurately grasp the design parameters, and the high-speed serial link meeting the design requirements can be designed more quickly.

Description

Design method and device of high-speed serial link, electronic equipment and storage medium

Technical Field

The present application relates to the field of circuit design technologies, and in particular, to a method and an apparatus for designing a high-speed serial link, an electronic device, and a storage medium.

Background

With the continuous improvement of the transmission rate of the high-speed serial signals and the complexity of the high-speed serial link, the reasonability and the effectiveness of the design of the high-speed serial link need to be considered more when the PCB is designed, and if the designed high-speed serial link cannot meet the design requirements, the design resources are wasted, and the production efficiency is seriously influenced.

If the designer can accurately grasp the design parameters when designing the high-speed serial link, the designer is helped to design the high-speed serial link meeting the design requirements more efficiently.

Disclosure of Invention

Based on the above requirements, the present application provides a method and an apparatus for designing a high-speed serial link, an electronic device, and a storage medium, which can assist a designer to accurately grasp design parameters and design a high-speed serial link meeting design requirements more quickly.

The first aspect of the present application provides a method for designing a high-speed serial link, where the method includes:

building a high-speed serial link model consisting of a transmission line model, a high-speed connector model and a via hole model;

determining via hole parameters meeting design requirements by measuring the impedance of the high-speed serial link model under different via hole parameters;

and/or the presence of a gas in the atmosphere,

and determining the transmission line length meeting the design requirement according to the active simulation eye pattern of the high-speed serial link model at different transmission line lengths.

In one implementation manner of the first aspect, determining via hole parameters meeting design requirements by measuring impedances of the high-speed serial link model under different via hole parameters includes:

and determining the via hole parameters which enable the impedance of the high-speed serial link model to meet the design requirements by adjusting the via hole parameters of the high-speed serial link model and measuring the impedance consistency of the high-speed serial link model under different via hole parameters.

In an implementation manner of the first aspect, determining a via parameter that makes an impedance of the high-speed serial link model meet a design requirement by adjusting a via parameter of the high-speed serial link model and measuring impedance consistency of the high-speed serial link model under different via parameters includes:

measuring the impedance consistency of the high-speed serial link model, and judging whether the impedance consistency of the high-speed serial link model meets a target impedance;

if the impedance does not accord with the target impedance, adjusting the via hole parameters of the high-speed serial link model and measuring the impedance consistency of the high-speed serial link model under different via hole parameters until the impedance consistency of the high-speed serial link model accords with the target impedance;

and determining the via hole parameters when the impedance consistency of the high-speed serial link model meets the target impedance as the via hole parameters which enable the impedance of the high-speed serial link model to meet the design requirements.

In an implementation manner of the first aspect, determining a transmission line length meeting design requirements according to an active simulated eye diagram of the high-speed serial link model at different transmission line lengths includes:

and determining the length of the transmission line which enables the signal transmission quality of the high-speed serial link model to meet the design requirement by adjusting the length of the transmission line of the high-speed serial link model and measuring the eye height and eye width of the active simulation eye pattern of the high-speed serial link model at different lengths of the transmission line.

In one implementation manner of the first aspect, determining the length of the transmission line, which enables the signal transmission quality of the high-speed serial link model to meet the design requirement, by adjusting the length of the transmission line of the high-speed serial link model and measuring the eye height and eye width of the active simulated eye pattern of the high-speed serial link model at different lengths of the transmission line includes:

respectively adding a sending end and a receiving end at two ends of the high-speed serial link model, and carrying out signal transmission simulation on the high-speed serial link model based on the sending end and the receiving end;

acquiring a simulated eye pattern for performing signal transmission simulation on the high-speed serial link model, and judging whether the simulated eye pattern meets the preset eye height and eye width requirements or not;

if the requirements of the preset eye height and eye width are not met, at least adjusting the length of a transmission line of the high-speed serial link model and measuring the eye height and eye width of a simulated eye pattern of the high-speed serial link model at different lengths of the transmission line until the simulated eye pattern for carrying out signal transmission simulation on the high-speed serial link model meets the requirements of the preset eye height and eye width;

and determining the length of a transmission line when the simulated eye pattern for carrying out signal transmission simulation on the high-speed serial link model meets the preset eye height and eye width requirements as the length of the transmission line which enables the signal transmission quality of the high-speed serial link model to meet the design requirements.

In one implementation manner of the first aspect, adjusting at least transmission line lengths of the high-speed serial link model and measuring eye heights and eye widths of simulated eye diagrams of the high-speed serial link model at different transmission line lengths includes:

adjusting the transmission line length and the via hole parameters of the high-speed serial link model, and measuring the eye height and the eye width of the simulated eye pattern of the high-speed serial link model under different transmission line lengths and via hole parameters;

the method further comprises the following steps:

and determining the via hole parameters when the simulated eye pattern for carrying out signal transmission simulation on the high-speed serial link model meets the preset eye height and eye width requirements as the via hole parameters for enabling the signal transmission quality of the high-speed serial link model to meet the design requirements.

In one implementation form of the first aspect, the method further comprises:

and determining the working margin of the high-speed serial link model according to the active simulation eye pattern of the high-speed serial link model under different transmission line lengths and different balanced values of the transmitting end and the receiving end.

In an implementation manner of the first aspect, determining a working margin of the high-speed serial link model according to an active simulation eye diagram of the high-speed serial link model when the high-speed serial link model has different transmission line lengths and different sending end and receiving end equalization values includes:

determining the working margin of the high-speed serial link model by measuring the eye height and the eye width of the active simulation eye pattern of the high-speed serial link model under different state combinations; the different state combinations are combinations of different transmission line lengths and different equalization values of the transmitting end and the receiving end.

In one implementation manner of the first aspect, determining the working margin of the high-speed serial link model by measuring the eye height and the eye width of the active simulation eye diagram of the high-speed serial link model under different state combinations includes:

respectively carrying out signal transmission simulation on the high-speed serial link model under various state combinations, and acquiring a simulation eye pattern;

respectively determining whether each simulated eye pattern meets the preset eye height and eye width requirements;

and determining the working margin of the high-speed serial link model according to the number of the simulated eye diagrams meeting the preset eye height and eye width requirements.

In one implementation manner of the first aspect, the line length of the transmission line model and the transmission loss are positively correlated.

In one implementation of the first aspect, the via parameter includes at least one of a via radius, an anti-pad size, and a via distribution for reflow.

In a second aspect of the present application, a device for designing a high-speed serial link is provided, including:

the link building module is used for building a high-speed serial link model consisting of a transmission line model, a high-speed connector model and a via hole model;

the test verification module is used for determining the via hole parameters meeting the design requirements by measuring the impedance of the high-speed serial link model under different via hole parameters; and/or determining the transmission line length meeting the design requirement according to the active simulation eye pattern of the high-speed serial link model in different transmission line lengths.

A third aspect of the present application provides an electronic device, comprising:

a memory and a processor;

wherein the memory is connected with the processor and used for storing programs;

the processor is configured to implement the design method for a high-speed serial link proposed in the first aspect by running the program in the storage.

A fourth aspect of the present application provides a storage medium, where a computer program is stored, and when the computer program is executed by a processor, the method for designing a high-speed serial link according to the first aspect is implemented.

According to the design method of the high-speed serial link, when the high-speed serial link is designed, a high-speed serial link model composed of a transmission line model, a high-speed connector model and a via hole model is built, then via hole parameters meeting design requirements are determined by measuring impedance of the high-speed serial link model under different via hole parameters, and/or transmission line degrees meeting the design requirements are determined according to active simulation eye diagrams of the high-speed serial link model under different transmission line lengths. The method can determine the structural parameters of the high-speed serial link meeting the design requirements in a model simulation mode, so that designers can be assisted to accurately grasp the design parameters, and the high-speed serial link meeting the design requirements can be designed more quickly.

Furthermore, the design method performs key analysis on key structures, namely the via holes and the transmission lines, in the high-speed serial link, so that influence factors playing a key role in the link performance can be more quickly grasped, and the link structure is more specifically and optimally designed, so that the design efficiency can be further improved, and the design resources can be saved.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only the embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

Fig. 1 is a schematic diagram of a PCB via provided in an embodiment of the present application.

Fig. 2 is a schematic diagram of a high-speed serial link simulation test circuit model according to an embodiment of the present application.

Fig. 3 is a schematic flowchart of a method for designing a high-speed serial link according to an embodiment of the present disclosure.

Fig. 4 is a schematic structural diagram of a high-speed serial link model according to an embodiment of the present application.

Fig. 5 is a schematic processing flow diagram of performing a passive simulation test on a high-speed serial link model according to an embodiment of the present application.

Fig. 6 is a schematic processing flow diagram for performing active simulation test on a high-speed serial link model according to an embodiment of the present application.

Fig. 7 is a schematic diagram of a test circuit for performing active simulation test on a high-speed serial link model according to an embodiment of the present application.

Fig. 8 is a schematic structural diagram of a device for designing a high-speed serial link according to an embodiment of the present application.

Fig. 9 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.

Due to the great advantages of high-speed serial links in data transmission, high-speed serial interconnection technology has become a focus of related industries, and has been designed as the most important work content in the current PCB (Printed circuit board) design.

A high-speed serial link realized by depending on a PCB mainly comprises a transmission line, a via hole and a connector.

The transmission line refers to a signal line (composed of two wires with a certain length, one is a signal propagation path, and the other is a signal return path) with signal backflow, and the most common transmission line is a trace on a PCB.

The transmission line structure in a typical PCB is made up of conductive lines embedded in or adjacent to a dielectric or insulating material and having one or more reference planes. The metal in a typical PCB is copper, i.e. the transmission lines are made of copper wire, and the dielectric is a glass fibre called FR 4.

The via hole is an important component of the multilayer PCB and plays a role of connecting signals of different layers. In terms of process, PCB via holes are generally classified into 3 types: blind, buried and through holes as shown in fig. 1.

The connector is used for connecting different serial links, especially for connecting serial links on different PCB boards. For example connecting transmission lines on different PCB boards.

Based on the transmission lines, the through holes and the connectors, the high-speed serial links with different lengths and different complexities can be designed in a combined mode by changing the length of the transmission lines, the number of the through holes and the number of the connectors. For example, different configurations of high-speed serial links such as "transmission line-via-transmission line-connector-transmission line", "transmission line-via-transmission line-connector-via-transmission line", "transmission line-connector-transmission line-via-transmission line" may be combined.

In addition, the purpose of adjusting the performance of the high-speed serial link can be achieved by changing the characteristic parameters of the transmission line, the via hole and the connector, for example, the consistency of the impedance of the link, the performance (such as signal integrity) of a transmission signal of the link and the like can be adjusted. In addition, the PCB board, the routing method, etc. also have a certain influence on the performance of the high-speed serial link.

Overall, the transmission line, the via hole and the connector are the most main link structures for building the high-speed serial link, and are key structures for influencing the link performance. In order to design a high-speed serial link meeting design requirements, hardware designers need to comprehensively consider the influence of PCB plates, transmission lines, via holes, connectors and the like on the link performance.

However, the influence of the above factors on the link performance cannot be effectively grasped by general hardware designers, and it is common practice to perform an empirical comparative analysis based on reference design provided by a chip manufacturer and data provided by a board manufacturer. The design method has certain blindness, has great limitation on the design of the high-speed serial link, and is difficult to ensure that the high-speed serial link meeting the design requirement can be designed.

In order to design a high-speed serial link meeting design requirements more efficiently, designers apply a simulation verification scheme to the design of the high-speed serial link, so that the designed high-speed serial link meets design requirements. After the PCB high-speed serial link is designed, simulation verification is carried out on the PCB high-speed serial link, and whether the impedance consistency, the signal integrity and the like of the link meet the design requirements or not is tested. And if the simulation result does not meet the design requirement, re-edition design is carried out. Although the scheme can ensure that the finally designed high-speed serial link meets the design requirement, the re-version design is required when the simulation is failed every time, and huge waste of time, labor cost and production cost is caused.

In order to further improve the design efficiency, the industry also provides simulation verification before PCB design, namely before designing an actual PCB high-speed serial link, firstly building a high-speed serial link model through simulation software, then carrying out simulation test on the built high-speed serial link model to verify whether the performance of the model meets the design requirements, and if not, directly modifying link parameters of the high-speed serial link model on the simulation software until the performance of the simulated high-speed serial link model meets the design requirements. And then designing an actual high-speed serial link product according to a high-speed serial link model which meets the design requirement through simulation verification.

As an example, FIG. 2 shows a simulation circuit model diagram of a high speed serial link pre-design simulation. The simulation circuit model includes a transmitter TX, a receiver RX, and a high speed serial link model between the transmitter TX and the receiver RX. The high-speed serial link model is a serial link (the specific structure of which is not shown in the drawing) made up of transmission lines, vias, connectors, and the like, in accordance with the link structure of the high-speed serial link design target. Furthermore, oscilloscopes for measuring signal eye diagrams are respectively provided at the input and output of the high-speed serial link model and at the output of the receiver RX.

In the simulation test process, an oscilloscope is used for measuring a signal eye pattern of a signal flowing through a high-speed serial link model, so that whether the performance of the high-speed serial link can meet the design requirement or not is judged, and if the performance of the high-speed serial link cannot meet the design requirement, parameters of the high-speed serial link model are corrected and retested.

In the simulation test scheme, the high-speed serial link is taken as a whole and taken as a tested object, and when the test fails, the whole high-speed serial link needs to be analyzed and the parameters need to be corrected. However, as described above, the performance of the high-speed serial link is affected by various factors, and based on the above simulation test, when correcting the parameters of the high-speed serial link model, the conventional method is to randomly adjust the structural parameters of each part of the whole link, try different parameter combinations, and test the performance of the link respectively until the performance of the link model meets the design requirements.

Therefore, in the above simulation test before design, the whole link needs to be analyzed and parameter corrected during each parameter correction, which requires a long simulation time and large calculation resources, and has a limited effect on improving the design efficiency of the high-speed serial link.

Based on the technical current situation, the inventor of the application provides a more efficient high-speed serial link design scheme through research and comparative analysis, and can remarkably improve the design efficiency of the high-speed serial link. The high speed serial link design proposed in the present application is exemplified by various embodiments.

Exemplary method

First, the embodiment of the present application provides a method for designing a high-speed serial link, which can be exemplarily applied to an intelligent processing device, thereby implementing an automated design of a high-speed serial link.

The intelligent processing equipment can be various types of electronic equipment with data processing functions, such as a computer, an intelligent terminal, a single chip microcomputer and the like. In the embodiment of the present application, the above-mentioned intelligent processing device is particularly a device having a high-speed serial link design capability and a high-speed serial link simulation test capability. The high-speed serial link design capability enables the intelligent processing equipment to build high-speed serial links with different structures and different parameters or adjust the structures and the parameters of the existing high-speed serial links; the high-speed serial link simulation test capability enables the intelligent processing equipment to perform simulation test on the built high-speed serial link, and the specific simulation test item is a conventional high-speed serial link simulation test item. For example, the intelligent processing device may call or control simulation software, and implement high-speed serial link model building and model simulation testing by performing model building and model simulation testing operations.

Referring to fig. 3, a method for designing a high-speed serial link according to an embodiment of the present application includes:

s301, building a high-speed serial link model composed of a transmission line model, a high-speed connector model and a via hole model.

Specifically, the transmission line model is created by simulation software and represents a transmission line model of all transmission lines in the high-speed serial link corresponding to the link design target. The length of the transmission line model is equal to the sum of the lengths of all the transmission lines in the high-speed serial link corresponding to the link design target, the type of the transmission line model is the same as that of the transmission lines in the high-speed serial link corresponding to the link design target, and the parameters of the transmission line model are consistent with those of the transmission lines in the high-speed serial link corresponding to the link design target.

As a preferred design scheme, the transmission line model created in the embodiment of the present application is a simple differential transmission line model, adjustable parameters of the differential transmission line model only include two parameters, namely, a board parameter and a copper foil roughness, and other parameters are all constant values. In addition, the impedance of the differential transmission line model is set to meet the impedance requirement of a link design target, and the line length of the differential transmission line model is set to be in positive correlation with the transmission loss of the differential transmission line model, so that the transmission loss of the differential transmission line model can be changed by changing the line length of the differential transmission line model.

The impedance requirement of the link design target is specifically a link impedance which enables the signal integrity of a signal transmitted in a link transmission line to meet the design requirement. Generally, when a signal is transmitted in a transmission line of a high-speed serial link and meets an impedance discontinuity point, a reflection phenomenon exists, and the reflection causes loss of signal energy, so that the signal transmitted by the high-speed serial link is incomplete. If the impedance of the high-speed serial link transmission line meets the impedance requirement of the design target, the reflection of the signal during transmission in the link can be minimized, that is, the loss of the signal during transmission in the link can be minimized, so that the signal integrity meets the design requirement.

Specifically, the transmission lines transmit different types of signals, and the reflection of the signals by the transmission lines is different. Therefore, the impedance requirement of the link design target is different according to the type of the signal to be transmitted by the link, for example, the impedance of the differential transmission line may be set to 85 ohms, 93 ohms, 100 ohms, and the like according to different signal types, that is, the deviation between the impedance of each part of the differential transmission line and the set impedance value is within a preset range, so that the impedance consistency of the whole transmission line is good.

Illustratively, the impedance adjustment of the differential transmission line can be realized by adjusting the copper foil thickness, the line width and the line distance, the plate parameters and the like of the differential transmission line.

The high-speed connector model can be particularly used for connecting different transmission lines, such as differential transmission lines on different mainboards. The structure and characteristic parameters of the high-speed connector can be designed according to a conventional PCB circuit connector, and the high-speed connector is named as a high-speed connector because the embodiment of the application applies the high-speed connector to the connection of the transmission line of the high-speed serial link.

In an actual high-speed serial link design, a high-speed connector in a link may be a connector designed according to requirements of the high-speed serial link, or may be a connector provided by a third party, and in an embodiment of the present application, the connector provided by the third party is exemplarily used, that is, the high-speed connector provided by the third party is used to design the high-speed serial link.

Based on the design concept of the high-speed serial link, the attribute parameters of the connector provided by a third party are obtained, for example, the S parameters of the connector are obtained, and then the S parameters of the connector are introduced into the simulation software, so that a connector model can be generated in the simulation software, and the high-speed connector model can be obtained.

The number of high speed connector models described above may be set depending on the purpose of the high speed serial link design. For example, assuming that the high-speed serial link design is intended to design a high-speed serial link including 3 high-speed connectors, the number of the above-mentioned high-speed connector models is set to 3, that is, 3 high-speed connector models are included in the built high-speed serial link model.

In addition, in the actual simulation test, since the S parameter of the connector provided by the third party is fixed, and the parameter of the connector cannot be adjusted at will in the high-speed serial link design, the above-mentioned high-speed connector model is also set as a connector model whose parameter is not adjustable. Therefore, when performance optimization or parameter adjustment is required for the high-speed serial link model, the parameter adjustment and optimization cannot be performed on the high-speed connector model, and only other parts can be adjusted.

It will be appreciated that if the high speed connector is designed by itself rather than using an off-the-shelf connector provided by a third party, the parameters or performance of the high speed connector can be freely adjusted based on design requirements. Accordingly, under the design concept, the high-speed connector model is a self-designed connector model, rather than directly adopting a connector model provided by a third party, and the parameters or performance of the high-speed connector model can be adjusted based on the design requirements.

The above-mentioned via hole model is a via hole model suitable for the above-mentioned transmission line model and used for connecting different transmission line model line segments. The type of the via pattern is the same as the type of the transmission pattern described above. For example, if the transmission line model is a differential transmission line model, the via model is a differential via model.

The number of the via hole models is determined according to the number of PCB layers which need to be crossed by the high-speed serial link corresponding to the high-speed serial link design target. For example, if a high-speed serial link corresponding to a high-speed serial link design target needs to span 3 PCB layers, routing of the link on the 3 PCB layers needs to be implemented by using 2 groups of via holes, and thus 2 groups of via holes in the high-speed serial link need to be simulated by setting 2 via hole models.

In addition, the above-mentioned key structural parameters of the via model are adjustable, and the key structural parameters include at least one of via radius, anti-pad size, and via hole distribution of reflow. That is to say, in the simulation test process, at least one of the via radius, the anti-pad size, and the reflow ground hole distribution of the via model may be adjusted, and via parameter adjustment may be performed in a variable parameter scan adjustment manner. For other via hole parameters, the influence coefficient of the other via hole parameters on the performance of the via hole and the link is small, so that the parameters are directly set to be fixed values or theoretical optimal values, and the parameters are set to be in an unadjustable state in the simulation test process.

As an exemplary model creation mode, in the embodiment of the present application, the transmission line model is created in ADS simulation software, and meanwhile, a via model is created in HFSS simulation software; then, in ADS simulation software, importing a high-speed connector model through an S parameter of a high-speed connector, and importing a parameter of the created via hole model into the ADS simulation software, so that a via hole model is created in the ADS simulation software; and finally, connecting the transmission line model, the high-speed connector model and the via hole model to form a high-speed serial link model.

The line length of the transmission line model is set according to a final design objective, for example, the final design objective is to design a high-speed serial link with a total transmission line length (including the total length of all transmission lines on different PCB layers or different PCB boards) of 1 meter, and then the line length of the transmission line model is set to 1 meter. The number of the high-speed connector models and the number of the via hole models are the same as the number of the high-speed connectors and the number of the via holes in the high-speed serial link corresponding to the final design target. And the connection relation among the transmission line model, the high-speed connector model and the via hole model can be flexibly adjusted.

For example, assume that the high speed serial link design goal is to design a transmission line assembly of 2 meters and would span two PCB boards, and a total of 3 PCB layers of high speed serial links on the two PCB boards. It can be determined by analysis that the link requires 1 connector, 2 sets of vias, and a transmission line of 2 meters in total length. Based on the design requirements, the embodiment of the application creates a transmission line model with a line length of 2 meters, and creates 1 high-speed connector model and 2 via hole models. Based on the above models, a high-speed serial link model as shown in fig. 4 can be constructed.

In the high-speed serial link model shown in fig. 4, the positions and the mutual positional relationship of the respective models are not limited as long as the number of the respective models matches the actual design requirement.

In the embodiment of the present application, when the high-speed serial link model is built in step S301, only the link structure having a large performance influence coefficient on the high-speed serial link is built in the link model, and the parameter of each link structure that has a significant influence on the link performance is set in an adjustable state, so that the complexity of the link model can be reduced. The performance of the whole link can be obviously changed only by adjusting the key link structure and the main parameters of the key link structure, so that the aim of quickly adjusting the performance of the link is fulfilled.

Moreover, when the high-speed serial link model is built, the number of each link structure is considered emphatically, the connection relation of each link structure is not limited (because the position relation of each link structure does not influence the overall performance of the link, and the number of the link structures has direct influence on the overall performance of the link), so that the built high-speed serial link model can be independent of the ideal high-speed serial link structure, the building efficiency of the high-speed serial link model is further improved, and the overall design efficiency of the high-speed serial link is favorably improved.

S302, determining the via hole parameters meeting the design requirements by measuring the impedance of the high-speed serial link model under different via hole parameters.

And/or the presence of a gas in the gas,

and S303, determining the transmission line length meeting the design requirement according to the active simulation eye pattern of the high-speed serial link model in different transmission line lengths.

In theory, a qualified high-speed serial link should ensure that its impedance in a passive state (when no signal is transmitted) meets design requirements, and at the same time, ensure that its signal integrity in an active state (when signal is transmitted) meets design requirements.

Therefore, in order to achieve the purpose of designing the high-speed serial link, the embodiments of the present application respectively perform a passive simulation test and an active simulation test on the high-speed serial link model, so as to determine each link parameter that enables the high-speed serial link model to meet the design requirement.

When the passive simulation test is carried out, the impedance of the high-speed serial link model is mainly measured, and the impedance of the high-speed serial link model meets the target impedance of the design requirement by adjusting the structural parameters of the high-speed serial link model.

Experiments and comparative analysis show that the via hole of the high-speed serial link is a key factor influencing the impedance of the high-speed serial link in a passive state. Therefore, in the passive simulation test process, when the impedance of the high-speed serial link model does not meet the target impedance of the design requirement, the structural parameters of the via hole model in the high-speed serial link model are adjusted until the via hole parameters which can enable the impedance of the high-speed serial link model to meet the target impedance of the design requirement are determined and serve as the via hole parameters meeting the design requirement.

Similarly, during active simulation testing, a signal eye diagram (namely, an active simulation eye diagram) of a signal transmitted in a high-speed serial link model is mainly measured through an oscilloscope, and the signal integrity of the signal transmitted in the high-speed serial link model is observed through the signal eye diagram, so that whether the signal integrity meets the design requirement is judged. And if not, adjusting the structural parameters of the high-speed serial link model until a signal eye pattern meeting the design requirement is obtained.

Tests and comparative analysis show that the transmission line loss of the high-speed serial link is a key factor influencing the signal integrity in an active state. Therefore, in the active simulation test process, when the signal integrity of the signal transmitted in the high-speed serial link model does not meet the design requirement, the transmission line loss is adjusted.

Based on the above description, in the high-speed serial link constructed in the embodiment of the present application, the loss of the transmission line is positively correlated to the line length of the transmission line, so that the purpose of adjusting the loss of the transmission line can be achieved by adjusting the length of the transmission line. When the adjusted length of the transmission line enables the integrity of the signal transmitted in the high-speed serial link model to meet the design requirement, the adjustment is stopped, and the length of the transmission line is determined to be the length of the transmission line meeting the design requirement.

The passive simulation test and the active simulation test can be executed respectively and independently or sequentially. In the embodiment of the present application, the high-speed serial link model is exemplarily subjected to a simulation test according to the passive simulation test scheme, and then an active simulation test is performed on the high-speed serial link model after the passive simulation test and parameter optimization (i.e., after the optimization of the via hole parameters) is completed, and the parameters (i.e., the length of the transmission line) of the high-speed serial link model are continuously optimized.

It can be understood that the parameters of the via holes and the lengths of the transmission lines determined based on the simulation test can make the impedance and the signal integrity of the high-speed serial link model meet the design requirements. And designing an actual high-speed serial link according to the high-speed serial link model to obtain the high-speed serial link meeting the design requirement.

It can be seen from the above description that, the high-speed serial link design method provided in the embodiment of the present application can determine via hole parameters meeting design requirements by measuring the impedance of the high-speed serial link model under different via hole parameters, and can determine the length of a transmission line meeting design requirements according to the active simulated eye pattern of the high-speed serial link model during different lengths of the transmission line, thereby achieving the purpose of determining link parameters before designing the high-speed serial link, and facilitating designing the high-speed serial link meeting design requirements.

The design method grasps key factors influencing the link performance, and can quickly optimize the link performance by adjusting the parameters of the key structure of the high-speed serial link model, thereby quickly determining the link parameters enabling the link performance to meet the design requirements. Specifically, the impedance of the link in the passive state meets the design requirements by adjusting the via hole parameters directly influencing the impedance of the link, and the signal integrity of the link in the active state meets the design requirements by adjusting the length of the transmission line directly influencing the signal integrity.

Different from the traditional link test method, the link design method provided by the application directly concentrates the key points of simulation test on the specific structure of the link, thereby avoiding the problem points from being checked globally from the link when the test does not pass, and improving the link design efficiency.

In addition, the high-speed serial link model constructed in order to realize the high-speed serial link design in the embodiment of the application is not a link structure strictly consistent with the design target of the high-speed serial link, but is constructed by key structure models influencing the link performance, and parameters of each key structure model are optimized, and only the parameter with a large influence coefficient on the link performance is kept in an adjustable state. The high-speed serial link model is lower in complexity and smaller in scale, and the purpose of designing a more complex high-speed serial link can be achieved based on the relatively simpler high-speed serial link model, so that the link design efficiency is further improved.

As an exemplary embodiment, according to the high-speed serial link design method provided by the present application, when the via hole parameter meeting the design requirement is determined through a passive simulation test performed on the high-speed serial link model, the via hole parameter making the impedance of the high-speed serial link model meet the design requirement may be determined specifically by adjusting the via hole parameter of the high-speed serial link model and measuring the impedance consistency of the high-speed serial link model under different via hole parameters.

The impedance consistency of the high-speed serial link refers to the consistency of the impedance at different positions of the high-speed serial link. Ideally, the smaller the difference between the impedances at different positions of the high-speed serial link is, i.e. the better the impedance consistency is, the smaller the energy loss of the signal during transmission in the high-speed serial link is, the better the signal integrity is. Therefore, in the design requirement of the high-speed serial link, the signal transmission performance of the link can be ensured to reach the standard by a mode of specifying the impedance consistency requirement of the high-speed serial link.

Based on the link design concept, when the passive simulation test is performed on the built high-speed serial link model, the impedance consistency of the link is used as the test content, the impedance consistency of the link meets the design requirement as the target, the parameters of the via holes in the link are adjusted, and the via hole parameters which enable the impedance consistency of the link to meet the design requirement are determined.

Referring to fig. 5, the above-mentioned via parameter determination process includes the following processing steps:

s501, measuring impedance consistency of the high-speed serial link model.

Illustratively, the impedance consistency of the high-speed serial link may be determined by measuring the impedance at various different locations of the high-speed serial link model. The measured impedance consistency can be expressed as a percentage difference between impedances at different positions of the link.

The measurement of the impedance consistency of the high-speed serial link model can be realized by an impedance consistency measurement function of simulation software for building the high-speed serial link model, or by an impedance measurement function of the simulation software, the impedance consistency of the high-speed serial link model can be calculated and determined by measuring the impedances at different positions of the high-speed serial link model.

S502, judging whether the impedance consistency of the high-speed serial link model meets the target impedance or not.

The target impedance means that the impedance difference of the links does not exceed a set threshold. For example, if the impedance difference of each part of the link is not more than 10% as the target impedance, it can be considered that the impedance consistency of the link meets the target impedance when the impedance difference of each part of the high-speed serial link is not more than 10% as determined by measurement. At this time, the process jumps to step S504.

If the impedance does not meet the target impedance, for example, the impedance difference of each part of the high-speed serial link exceeds 10%, it is considered that the impedance consistency of the link does not meet the target impedance, and then step S503 is executed to adjust the via hole parameter of the high-speed serial link model.

After the via hole parameter is adjusted, the process returns to step S501, in which the impedance consistency of the high-speed serial link is re-measured, and the subsequent step S502 is executed, and if the determination of step S502 does not pass, the process continues to step S503.

And repeating the processing of S501-S503, measuring the impedance consistency of the high-speed serial link model under different via hole parameters, and stopping the repeated process until the impedance consistency of the high-speed serial link model meets the target impedance.

When the impedance consistency of the high-speed serial link model meets the target impedance after the via hole parameter is adjusted for a certain time, step S504 is executed to determine the via hole parameter when the impedance consistency of the high-speed serial link model meets the target impedance as the via hole parameter which enables the impedance of the high-speed serial link model to meet the design requirement.

In the processing process, the impedance consistency of the link is enabled to meet the design requirement by adjusting the via hole parameters in the high-speed serial link model. The optimization design of the link impedance by adjusting the key link structure is realized, the optimization of the via hole parameters is completely based on the impedance consistency of the link, and the via hole parameters are optimized only when the impedance consistency of the link is failed, so that the invalid excessive optimization of the via hole can be avoided, and the simulation test and design efficiency is ensured.

When the length of the transmission line meeting the design requirement is determined according to the signal eye diagram of the active simulation test by performing the active simulation test on the high-speed serial link model, the length of the transmission line which enables the signal transmission quality of the high-speed serial link model to meet the design requirement is determined by specifically adjusting the length of the transmission line of the high-speed serial link model and measuring the eye height and the eye width of the active simulation eye diagram of the high-speed serial link model at different transmission line lengths.

The signal eye diagram is a common method for analyzing the signal transmission performance of a system, and the method is used for observing the influence of signal waveform type analysis intersymbol interference and noise in the system on the system performance through an oscilloscope. The image on the oscilloscope is called an "eye diagram" because it looks like a human eye. Generally, an eye pattern in binary signal transmission shows only one "eye", and a ternary signal transmission shows two "eyes". In an ideal channel without intersymbol interference and noise, because the waveform is undistorted and each code element is overlapped, an image on an oscilloscope is an eye with a thin and clear trace, and the eye is opened to the maximum at the moment; when intersymbol crosstalk occurs, the traces of the eye pattern are not as sharp due to distortion of the waveform and incomplete overlapping of the symbols, resulting in partial closure of the "eye", which, if combined with the effects of noise, blurs the lines of the eye pattern and opens less. The degree to which the "eye" is closed reflects the magnitude of the signal distortion and can also be used to indicate the integrity of the signal transmitted over the high speed serial link.

The degree of closure of the "eyes" in the signal eye diagram is generally quantified by the eye height and eye width of the "eyes", and the larger the values of the eye height and eye width are, the larger the "eyes" are opened, the better the signal quality is, and conversely, the smaller the values of the eye height and eye width are, the smaller the "eyes" are opened, the worse the signal quality is.

Based on the above theory, when performing an active simulation test on the high-speed serial link model, the embodiment of the present application determines the signal transmission quality by acquiring a signal eye diagram in the link and analyzing the eye height and eye width of the signal eye diagram, and then adjusts link parameters based on the signal transmission quality, specifically, adjusts the length of a signal transmission line of the link until the signal transmission quality of the link is determined to meet the design requirement through the signal eye diagram analysis, and records the length of the signal transmission line of the link, where the length of the transmission line is the length of the transmission line that enables the signal transmission quality of the high-speed serial link model to meet the design requirement.

Referring to fig. 6, the above-mentioned determination of the transmission line length for making the signal transmission quality of the high-speed serial link model meet the design requirement can be specifically realized by performing the following steps:

s601, respectively adding a sending end and a receiving end at two ends of the high-speed serial link model, and carrying out signal transmission simulation on the high-speed serial link model based on the sending end and the receiving end.

The transmitting terminal TX and the receiving terminal RX are respectively added to the head and the tail of the high-speed serial link model shown in fig. 4, so that the high-speed serial link model active simulation circuit model shown in fig. 7 can be obtained. The transmitting end is used for transmitting high-speed serial signals, and the receiving end is used for receiving the high-speed serial signals transmitted by the high-speed serial link model. The sending end and the receiving end may adopt a signal transmitter and a signal receiver with any parameters and any performance, for example, a transmitter model and a receiver model may be directly imported from ADS simulation software, and are respectively connected with the head and the tail of the high-speed serial link model, so as to obtain the active simulation circuit model shown in fig. 7. In addition, an oscilloscope is connected to the receiving end RX, which can be used to observe the waveform of the signal received by the receiving end RX, so as to determine the signal transmission quality according to the signal waveform.

Based on the circuit model shown in fig. 7, when an active simulation test is performed, a sending terminal TX sends out a high-speed serial signal, and the high-speed serial signal is transmitted through a high-speed serial link model and then received by a receiving terminal RX, so that the simulation of the whole signal transmission process is realized.

S602, acquiring a simulated eye pattern for carrying out signal transmission simulation on the high-speed serial link model, and judging whether the simulated eye pattern meets the preset eye height and eye width requirements.

Specifically, as shown in fig. 7, an oscilloscope arranged at the receiving end RX may be used to acquire an eye pattern of a signal transmitted through the high-speed serial link model, so as to obtain a simulated eye pattern.

The preset eye height and eye width requirements refer to preset values of eye height and eye width. When the actually acquired values of the eye height and the eye width of the simulated eye pattern are larger than the preset values of the eye height and the eye width, the simulated eye pattern is considered to meet the preset requirements of the eye height and the eye width.

Illustratively, by using a parameter measurement function of the ADS simulation software, the eye height and eye width values of the simulated eye pattern acquired by the oscilloscope can be determined, and then whether the eye height and eye width of the simulated eye pattern meet the preset requirements of the eye height and eye width can be judged.

If the preset eye height and eye width requirements are met, step S604 is executed.

And if the eye height and the eye width do not meet the preset requirements, executing the step S603, and at least adjusting the length of the transmission line of the high-speed serial link model.

Then, the step S602 is executed again, a simulated eye diagram for performing signal transmission simulation on the high-speed serial link model is obtained, and whether the simulated eye diagram meets the preset eye height and eye width requirements is judged.

And repeatedly executing the steps S602 and S603, and measuring the eye height and the eye width of the simulated eye pattern of the high-speed serial link model in different transmission line lengths until the simulated eye pattern for carrying out signal transmission simulation on the high-speed serial link model meets the preset requirements on the eye height and the eye width.

Specifically, the eye height and the eye width of the simulated eye pattern meet the preset eye height and eye width requirements, which indicates that the signal quality of the signal transmitted by the high-speed serial link model is good, and at this time, the signal transmission quality of the high-speed serial link model can be considered to meet the design requirements, so that the test can be stopped, and the subsequent step S604 is executed.

On the contrary, if the eye height and the eye width of the simulated eye pattern do not meet the preset requirements for the eye height and the eye width, it is indicated that the signal quality of the signal transmitted by the high-speed serial link model is not good enough, and at this time, the signal transmission quality of the high-speed serial link can be considered to be not in accordance with the design requirements, so that the parameters of the high-speed serial link model need to be corrected.

Because the transmission loss of the high-speed serial link is the key influencing the signal transmission quality of the high-speed serial link, and the transmission loss of the link is positively correlated with the length of a transmission line of the link, when a simulation eye diagram of an active simulation test does not meet the preset eye height and eye width requirements, the length of the transmission line of the high-speed serial link model is adjusted, specifically, the length of the transmission line of the high-speed serial link model is shortened, so that the transmission loss of the link is reduced.

Then, the adjusted link is subjected to a signal transmission simulation test again, step S602 is executed to obtain a simulated eye diagram for performing signal transmission simulation on the high-speed serial link model, and it is determined whether the simulated eye diagram meets the requirements of the preset eye height and eye width.

If yes, continuing to execute the subsequent step S604; if not, the transmission line length of the high-speed serial link model is adjusted again by executing step S603, and the process returns to execute step S602.

By repeating the above steps S602 and S603, the transmission line length of the high-speed serial link model is repeatedly adjusted, and the eye height and eye width of the simulated eye pattern of the high-speed serial link model at different transmission line lengths are measured, until the simulated eye pattern for performing signal transmission simulation on the high-speed serial link model meets the preset requirements for eye height and eye width, the above-mentioned repeated process is ended, and the process goes to step S604.

S604, determining the length of a transmission line when the simulated eye pattern for carrying out signal transmission simulation on the high-speed serial link model meets the preset eye height and eye width requirements to be the length of the transmission line which enables the signal transmission quality of the high-speed serial link model to meet the design requirements.

In the signal transmission simulation process, when the eye height and the eye width of the simulated eye pattern are determined to meet the preset requirements through testing, the length of the transmission line of the high-speed serial link is recorded, and the length of the transmission line is determined to be the length of the transmission line which enables the signal transmission quality of the high-speed serial link model to meet the design requirements. It can be understood that the transmission line length of the actual high-speed serial link is designed according to the transmission line length of the high-speed serial link model at this time, so that the signal transmission quality of the actual high-speed serial link can meet the design requirement.

In the active simulation test process, the parameters of the key link structure influencing the signal transmission quality of the link are adjusted, so that the key points of the simulation test are concentrated on the key link structure, the signal transmission quality of the link can be adjusted to a state meeting the design requirement more quickly, and the aim of designing the high-speed serial link meeting the signal transmission quality requirement more efficiently can be fulfilled.

Further, the inventor of the present application found in experiments and practice that the via hole of the high-speed serial link affects the impedance of the high-speed serial link, and further affects the signal transmission quality of the high-speed serial link. Therefore, in the above signal transmission simulation test process, when the eye height and the eye width of the simulated eye pattern for performing signal transmission simulation on the high-speed serial link model do not meet the preset eye height and eye width requirements, the via hole parameters of the high-speed serial link model can be adjusted in addition to adjusting the transmission line length of the high-speed serial link model, and the eye height and the eye width of the simulated eye pattern of the high-speed serial link model during the adjusted transmission line length and via hole parameters are measured.

According to the adjustment mode, the transmission line length and the via hole parameters of the high-speed serial link model are repeatedly adjusted, and the eye height and the eye width of the simulated eye pattern of the high-speed serial link model are measured when the transmission line length and the via hole parameters are different, so that the transmission line length and the via hole parameters which enable the eye height and the eye width of the signal transmission simulated eye pattern of the high-speed serial link model to meet the preset eye height and eye width requirements are searched, and the transmission line length and the via hole parameters which enable the signal transmission quality of the high-speed serial link model to meet the design requirements are determined.

In addition, the via of the high-speed serial link is a key influencing the impedance consistency of the high-speed serial link. After the passive simulation test, the impedance consistency of the high-speed serial link model is made to meet the design requirement by adjusting the via hole parameter of the high-speed serial link model, and if the via hole parameter is adjusted again in the active simulation test process, the impedance consistency of the high-speed serial link model may not meet the design requirement. In order to make the impedance consistency and the signal transmission quality of the high-speed serial link model meet the design requirements, the impedance consistency of the model and the eye height and eye width of the signal transmission simulation eye pattern can be measured simultaneously in the process of adjusting the transmission line length and the via hole parameters of the high-speed serial link model, and the transmission line length and the via hole parameters which make the impedance consistency of the high-speed serial link model and the eye height and eye width of the simulation eye pattern meet the corresponding design requirements are searched for and used as the finally determined transmission line length and the via hole parameters.

Furthermore, some high-speed serial links need to be applied in different equalization value states at the transmitting end and the receiving end, so a high-speed serial link capable of meeting the signal transmission requirement under a specific equalization value condition at the transmitting end and the receiving end should be designed.

At this time, in the active simulation test process, the equalization values of the transmitting end and the receiving end may also be adjusted, so that the high-speed serial link model performs signal transmission in different states of the equalization values of the transmitting end and the receiving end, and the transmission line length and/or the via hole parameter that makes the signal transmission quality of the high-speed serial link model meet the design requirements are determined according to the design method described in the above embodiment.

The adjustment of the equalization values of the transmitting end and the receiving end can be realized by adjusting the equalization parameters of SerDes inside the transmitting end and the receiving end.

As a more preferred embodiment, after the passive simulation test and the active simulation test are performed, or while the active simulation test is performed, the working margin of the high-speed serial link model may be determined according to the active simulation eye diagrams of the high-speed serial link model at different transmission line lengths and different sending end and receiving end equalization values.

The working margin of the high-speed serial link is used for representing the capacity of the high-speed serial link capable of meeting the signal transmission requirement when the high-speed serial link has different sending end and receiving end equilibrium values. If the high-speed serial link can meet the design requirement of the signal transmission quality when a plurality of different transmitting end and receiving end equilibrium values exist, the working allowance of the high-speed serial link is larger, and conversely, if the high-speed serial link can only meet the design requirement of the signal transmission quality when one or a small number of different transmitting end and receiving end equilibrium values exist, the working allowance of the high-speed serial link is smaller. The size of the working allowance can reflect the performance of the high-speed serial link to a certain extent.

As described above, the transmission line length is a key factor affecting the signal transmission quality of the high-speed serial link. Therefore, when testing the signal transmission quality of the high-speed serial link model at different equilibrium values of the transmitting end and the receiving end, the adjustment of the transmission line length of the link should be combined, and if the signal transmission quality of the high-speed serial link model at a certain equilibrium value state of the transmitting end and the receiving end can meet the design requirement by adjusting the transmission line length of the high-speed serial link model, the high-speed serial link model is considered to meet the signal transmission quality design requirement at the equilibrium value state of the transmitting end and the receiving end.

By way of example, the embodiments of the present application determine the working margin of the high-speed serial link model by measuring the eye height and eye width of the active simulation eye diagram of the high-speed serial link model under different state combinations.

Wherein, the different state combinations are combinations of different transmission line lengths and different equalization values of the transmitting end and the receiving end.

The above different state combinations can be realized by fixing the length of the transmission line and adjusting the balance value of the transmitting end and the receiving end, and can also be realized by fixing the balance value of the transmitting end and the receiving end and adjusting the length of the transmission line.

Specifically, when the signal transmission simulation test is performed on the high-speed serial link model, the length of a transmission line of the link can be set to a certain value, then various balance value combinations of the transmitting end and the receiving end are traversed, an active simulation eye pattern of the high-speed serial link model under various balance value combinations (namely under different state combinations) is obtained through the simulation test, and whether the preset eye height and eye width requirements are met or not is judged through the eye height and eye width of the active simulation eye pattern; after traversing all the balance value combinations of the sending end and the receiving end, the transmission line length of the link is changed, the balance value combination traversing and testing process is executed again, and the testing result is recorded until all the transmission line lengths are traversed.

Or, the balance value of the sending end and the receiving end is set as a certain combined value, then the length of the transmission line of the high-speed serial link model is changed, an active simulation eye pattern of the high-speed serial link model at different lengths of the transmission line (namely under different state combinations) is obtained through simulation test, and whether the preset eye height and eye width requirements are met or not is judged through the eye height and eye width of the active simulation eye pattern; after traversing all transmission line lengths of the high-speed serial link model, the balance values of the sending end and the receiving end are changed, the test process is executed again, and the test result is recorded until all balance value combinations of the sending end and the receiving end are traversed.

Through the simulation test process, whether the eye height and the eye width of the simulated eye pattern of the high-speed serial link model under various state combinations meet the preset eye height and eye width requirements can be determined, namely whether the high-speed serial link model can meet the signal transmission quality requirements under various state combinations can be determined.

Furthermore, the number of the simulation eye patterns meeting the preset eye height and eye width requirements obtained in the simulation test process is counted, that is, the working margin of the high-speed serial link model can be determined by counting the number of state combinations of the high-speed serial link model which can meet the signal transmission quality requirements. Specifically, the number of simulated eye patterns meeting the preset eye height and eye width requirements is equal to the working margin of the high-speed serial link model.

For example, assuming that the simulated eye pattern obtained when the high-speed serial link model performs the active simulation test under 20 state combinations meets the preset eye height and eye width requirements, it is described that 20 simulated eye patterns meeting the preset eye height and eye width requirements are obtained in the active simulation test process, and at this time, it may be determined that the working margin of the high-speed serial link model is 20, that is, the high-speed serial link model can meet the signal transmission quality requirements under 20 state combinations. Further, specific combination parameters of 20 state combinations of the high-speed serial link model meeting the signal transmission quality requirement can be recorded, that is, the transmission line lengths corresponding to the 20 state combinations and the balance values of the transmitting end and the receiving end are recorded, so that the ideal signal transmission effect of the high-speed serial link model under which state combinations can be obtained can be more clearly determined.

It can be seen from the above description that the design method of the high-speed serial link provided in the embodiment of the present application can not only perform testing and parameter adjustment for the key structure of the link, so as to determine the structural parameters of the high-speed serial link meeting the design requirements more quickly, that is, design the high-speed serial link meeting the design requirements more quickly, but also determine the working margin of the designed high-speed serial link, and specify which states the designed high-speed serial link can meet the design requirements, thereby further improving the design efficiency of the high-speed serial link.

Exemplary devices

Corresponding to the design method of the high-speed serial link described above, an embodiment of the present application further provides a design apparatus of a high-speed serial link, as shown in fig. 8, the apparatus includes:

the link building module 100 is used for building a high-speed serial link model consisting of a transmission line model, a high-speed connector model and a via hole model;

the test verification module 110 is configured to determine a via parameter meeting design requirements by measuring impedances of the high-speed serial link model under different via parameters; and/or determining the transmission line length meeting the design requirement according to the active simulation eye pattern of the high-speed serial link model in different transmission line lengths.

The design device of the high-speed serial link can be exemplarily applied to the intelligent processing equipment, so that the intelligent processing equipment has the function of automatically designing the high-speed serial link.

The intelligent processing equipment can be various types of electronic equipment with data processing functions, such as a computer, an intelligent terminal, a single chip microcomputer and the like. In the embodiment of the present application, the above-mentioned intelligent processing device is specifically a device having a high-speed serial link design capability and a high-speed serial link simulation test capability. The high-speed serial link design capability enables the intelligent processing equipment to build high-speed serial links with different structures and different parameters or to adjust the structures and the parameters of the existing high-speed serial links; the high-speed serial link simulation test capability enables the intelligent processing equipment to perform simulation test on the built high-speed serial link, and the specific simulation test item is a conventional high-speed serial link simulation test item. For example, the intelligent processing device may call or control simulation software, and implement high-speed serial link model building and model simulation testing by performing model building and model simulation testing operations.

As an exemplary embodiment, the determining, by the test and verification module, via parameters meeting design requirements by measuring impedances of the high-speed serial link model under different via parameters includes:

As an exemplary embodiment, determining the via hole parameter that makes the impedance of the high-speed serial link model meet the design requirement by adjusting the via hole parameter of the high-speed serial link model and measuring the impedance consistency of the high-speed serial link model under different via hole parameters includes:

As an exemplary embodiment, the determining, by the test and verification module, the transmission line length meeting the design requirement according to the active simulated eye diagram of the high-speed serial link model at different transmission line lengths includes:

and determining the transmission line length which enables the signal transmission quality of the high-speed serial link model to meet the design requirement by adjusting the length of the transmission line of the high-speed serial link model and measuring the eye height and the eye width of the active simulation eye pattern of the high-speed serial link model when the high-speed serial link model is in different transmission line lengths.

As an exemplary embodiment, determining the transmission line length that makes the signal transmission quality of the high-speed serial link model meet the design requirement by adjusting the length of the transmission line of the high-speed serial link model and measuring the eye height and eye width of the active simulated eye pattern of the high-speed serial link model at different transmission line lengths comprises:

As an exemplary embodiment, adjusting at least the transmission line length of the high-speed serial link model and measuring the eye height and eye width of the simulated eye pattern of the high-speed serial link model at different transmission line lengths includes:

correspondingly, the test verification module is further configured to:

As an exemplary embodiment, the test validation module is further configured to:

and determining the working allowance of the high-speed serial link model according to the active simulation eye pattern of the high-speed serial link model under different transmission line lengths and different balanced values of the transmitting end and the receiving end.

As an exemplary embodiment, determining an operating margin of the high-speed serial link model according to an active simulation eye diagram of the high-speed serial link model at different transmission line lengths and different equalization values of a transmitting end and a receiving end includes:

As an exemplary embodiment, determining the working margin of the high-speed serial link model by measuring the eye height and eye width of the active simulation eye diagram of the high-speed serial link model under different state combinations comprises:

and determining the working allowance of the high-speed serial link model according to the number of the simulated eye patterns meeting the preset eye height and eye width requirements.

As an exemplary embodiment, the line length and the transmission loss of the transmission line model are positively correlated.

As an exemplary embodiment, the via parameter includes at least one of a via radius, an anti-pad size, and a via distribution of reflow.

The design apparatus for a high-speed serial link provided in this embodiment belongs to the same application concept as the design method for a high-speed serial link provided in the embodiments of the present application, can execute the design method for a high-speed serial link provided in any of the embodiments of the present application, and has functional modules and beneficial effects corresponding to the execution of the design method for a high-speed serial link. For details of the technology that is not elaborated in this embodiment, reference may be made to specific processing contents of the design method of the high-speed serial link provided in the foregoing embodiments of the present application, and details are not described herein again.

Exemplary electronic device

Another embodiment of the present application further provides an electronic device, as shown in fig. 9, the electronic device includes:

a memory 200 and a processor 210;

wherein, the memory 200 is connected to the processor 210 for storing programs;

the processor 210 is configured to implement the design method of the high-speed serial link disclosed in any of the above embodiments by running the program stored in the memory 200.

Specifically, the electronic device may further include: a bus, a communication interface 220, an input device 230, and an output device 240.

The processor 210, the memory 200, the communication interface 220, the input device 230, and the output device 240 are connected to each other through a bus. Wherein:

a bus may include a path that transfers information between components of a computer system.

The processor 210 may be a general-purpose processor, such as a general-purpose Central Processing Unit (CPU), microprocessor, etc., an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of programs in accordance with the present disclosure. But may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components.

The processor 210 may include a main processor and may also include a baseband chip, modem, and the like.

The memory 200 stores programs for executing the technical solution of the present application, and may also store an operating system and other key services. In particular, the program may include program code comprising computer operating instructions. More specifically, memory 200 may include a read-only memory (ROM), another type of static storage device that may store static information and instructions, a Random Access Memory (RAM), another type of dynamic storage device that may store information and instructions, a magnetic disk storage, a flash, and so forth.

The input device 230 may include a means for receiving data and information input by a user, such as a keyboard, mouse, camera, scanner, light pen, voice input device, touch screen, pedometer or gravity sensor, etc.

Output device 240 may include equipment that allows output of information to a user, such as a display screen, a printer, speakers, and the like.

Communication interface 220 may include any device that uses any transceiver or the like to communicate with other devices or communication networks, such as an ethernet network, a Radio Access Network (RAN), a Wireless Local Area Network (WLAN), etc.

The processor 210 executes the program stored in the memory 200 and invokes other devices, which can be used to implement the steps of any one of the methods for designing a high-speed serial link provided in the above embodiments of the present application.

Exemplary computer program product and storage Medium

In addition to the above-described methods and apparatus, embodiments of the present application may also be a computer program product comprising computer program instructions that, when executed by a processor, cause the processor to perform the steps in the method of designing a high speed serial link described in the "exemplary methods" section of this specification above.

The computer program product may be written with program code for performing the operations of embodiments of the present application in any combination of one or more programming languages, including an object oriented programming language such as Java, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device, or entirely on the remote computing device or server.

Furthermore, an embodiment of the present application may also be a storage medium on which a computer program is stored, the computer program being executed by a processor to perform the steps in the design method of the high-speed serial link described in the "exemplary method" section described above in this specification.

The detailed operation content of each part of the electronic device, and the detailed processing procedure when the computer program product and the computer program in the storage medium are executed by the processor can be referred to the description of the embodiment of the design method of the high-speed serial link, and the description of the embodiment of the present application is not repeated.

While, for purposes of simplicity of explanation, the foregoing method embodiments have been described as a series of acts or combination of acts, it will be appreciated by those skilled in the art that the present application is not limited by the order of acts or acts described, as some steps may occur in other orders or concurrently with other steps in accordance with the application. Further, those skilled in the art will recognize that the embodiments described in this specification are preferred embodiments and that acts or modules referred to are not necessarily required for this application.

It should be noted that, in this specification, each embodiment is described in a progressive manner, and each embodiment focuses on differences from other embodiments, and portions that are the same as and similar to each other in each embodiment may be referred to. For the device-like embodiment, since it is basically similar to the method embodiment, the description is simple, and reference may be made to the partial description of the method embodiment for relevant points.

The steps in the methods of the embodiments of the present application may be sequentially adjusted, combined, and deleted according to actual needs, and technical features described in the embodiments may be replaced or combined.

The modules and sub-modules in the device and the terminal of the embodiment of the application can be combined, divided and deleted according to actual needs.

In the several embodiments provided in the present application, it should be understood that the disclosed terminal, apparatus and method may be implemented in other manners. For example, the above-described terminal embodiments are merely illustrative, and for example, the division of a module or a sub-module is only one logical division, and there may be other divisions when the terminal is actually implemented, for example, a plurality of sub-modules or modules may be combined or integrated into another module, or some features may be omitted or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or modules, and may be in an electrical, mechanical or other form.

The modules or sub-modules described as separate parts may or may not be physically separate, and parts that are modules or sub-modules may or may not be physical modules or sub-modules, may be located in one place, or may be distributed over a plurality of network modules or sub-modules. Some or all of the modules or sub-modules can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, each functional module or sub-module in the embodiments of the present application may be integrated into one processing module, or each module or sub-module may exist alone physically, or two or more modules or sub-modules may be integrated into one module. The integrated modules or sub-modules may be implemented in the form of hardware, or may be implemented in the form of software functional modules or sub-modules.

Those of skill would further appreciate that the various illustrative components and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the components and steps of the various examples have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software unit executed by a processor, or in a combination of the two. The software cells may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for designing a high-speed serial link, comprising:

determining via hole parameters meeting design requirements by measuring the impedance of the high-speed serial link model under different via hole parameters, and/or determining the length of a transmission line meeting design requirements according to an active simulation eye pattern of the high-speed serial link model under different transmission line lengths;

2. The method of claim 1, wherein when the method performs the step of determining via parameters that meet design requirements by measuring impedance of the high speed serial link model at different via parameters, the determining via parameters that meet design requirements by measuring impedance of the high speed serial link model at different via parameters comprises:

3. The method of claim 2, wherein determining via parameters that make the impedance of the high-speed serial link model meet design requirements by adjusting the via parameters of the high-speed serial link model and measuring the impedance consistency of the high-speed serial link model under different via parameters comprises:

measuring the impedance consistency of the high-speed serial link model, and judging whether the impedance consistency of the high-speed serial link model meets a target impedance or not;

4. The method of claim 1, wherein when the method performs the step of determining the length of the transmission line that meets the design requirements based on the active simulated eye diagrams of the high speed serial link model at different lengths of the transmission line, the determining the length of the transmission line that meets the design requirements based on the active simulated eye diagrams of the high speed serial link model at different lengths of the transmission line comprises:

5. The method of claim 4, wherein determining the transmission line length that conforms the signal transmission quality of the high-speed serial link model to design requirements by adjusting the length of the transmission line of the high-speed serial link model and measuring the eye height and eye width of the active simulated eye diagram of the high-speed serial link model at different transmission line lengths comprises:

if the requirements of the preset eye height and the preset eye width are not met, at least adjusting the length of a transmission line of the high-speed serial link model and measuring the eye height and the eye width of a simulated eye pattern of the high-speed serial link model at different transmission line lengths until the simulated eye pattern for carrying out signal transmission simulation on the high-speed serial link model meets the requirements of the preset eye height and the preset eye width;

6. The method of claim 5, wherein adjusting at least transmission line lengths of the high-speed serial link model and measuring eye height and eye width of the simulated eye pattern of the high-speed serial link model at different transmission line lengths comprises:

the method further comprises the following steps:

7. The method of claim 1, wherein determining the operating margin of the high speed serial link model by measuring the eye height and eye width of an active simulated eye diagram of the high speed serial link model under different combinations of states comprises:

8. The method according to any one of claims 1 to 7, characterized in that the line length and the transmission loss of the transmission line model are positively correlated.

9. The method of any of claims 1-7, wherein the via parameters include at least one of via radius, anti-pad size, and reflow hole distribution.

10. An apparatus for designing a high-speed serial link, comprising:

the test verification module is used for determining the via hole parameters meeting the design requirements by measuring the impedance of the high-speed serial link model under different via hole parameters, and/or determining the length of the transmission line meeting the design requirements according to the active simulation eye pattern of the high-speed serial link model under different transmission line lengths; determining the working margin of the high-speed serial link model by measuring the eye height and the eye width of the active simulation eye pattern of the high-speed serial link model under different state combinations; the different state combinations are combinations of different transmission line lengths and different equalization values of the transmitting end and the receiving end.

11. An electronic device, comprising:

a memory and a processor;

the processor is configured to implement the method for designing a high-speed serial link according to any one of claims 1 to 9 by executing the program stored in the storage.

12. A storage medium having stored thereon a computer program which, when executed by a processor, implements a method of designing a high speed serial link according to any one of claims 1 to 9.