CN115983189A - Analog integrated circuit layout wiring method and system for self-adaptive grid - Google Patents
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Abstract
The invention discloses a method and a system for wiring a self-adaptive grid analog integrated circuit layout, wherein the method comprises the following steps: the method comprises the steps that the wiring width of a port is considered, path grid lines are explored on the basis of a self-adaptive grid of line exploration, and a three-dimensional path node grid is obtained; carrying out constraint check on the three-dimensional path node grid through a Floird algorithm and a Primem algorithm, and selecting a wiring path to be optimized according to a check result; and optimizing the wiring path to be optimized based on the resistance constraint and the time delay constraint to obtain the optimized wiring path. The system comprises: the device comprises an acquisition module, a constraint module and an optimization module. By using the invention, the priority of the wiring can be determined according to the information required by the wiring so as to carry out linear wiring. The invention is used as a method and a system for wiring a self-adaptive grid analog integrated circuit layout, and can be widely applied to the technical field of automatic wiring of computer aided design.
Description
Technical Field
The invention relates to the technical field of computer aided design automatic wiring, in particular to a method and a system for wiring a self-adaptive grid analog integrated circuit layout.
Background
Since the first transistor appeared in the fifties of the twentieth century, the manufacturing process of integrated circuits has been rapidly developed, the semiconductor processing process has entered the nanometer era, the integration scale has reached a very large scale, the functions are more and more diversified, so that a System-on-Chip (SoC) becomes possible, a digital circuit and an analog circuit can be integrated on one Chip, the digital circuit and the automatic design technology thereof have become mature day by day, and the automatic design of a large-scale and very high-complexity layout can be realized; compared with a wiring method of a digital integrated circuit layout, the wiring method based on channel distribution needs to reserve space for wiring channels in advance, and in order to guarantee DRC requirements (physical design rule requirements) among the wiring channels, the interval between the channels in the channels is far, so that the method needs to occupy extra layout area and is not applicable to an analog integrated circuit; the existing mainstream wiring method for simulating the layout wiring of the integrated circuit is a wiring method with a grid model and a wiring method without the grid model, wherein the wiring method with the grid model is developed relatively mature, such as a labyrinth wiring algorithm, an A-start wiring algorithm belongs to the wiring method with the grid, the construction of the grid is uniform, the advancing step length of the wiring is limited by the size of the grid, the DRC (physical design rule) check of the wiring and the surrounding obstacles is influenced if the grid is too large, and the wiring speed is influenced if the grid is too small, so the size selection of the grid is also a problem to be faced, and in the non-grid model, a wiring area has no limit, all units, modules and nets are expressed into polygons, all units and nets are described by means of vertex coordinates of the polygons, but defects exist in the non-grid model, and due to the lack of geometrical constraint, the most important symmetric constraint in the simulation circuit is difficult to process by a wiring system; meanwhile, due to the lack of foresight, the wire mesh path under the condition of multiple ports cannot be effectively processed.
Disclosure of Invention
In order to solve the above technical problems, an object of the present invention is to provide a method and a system for routing an analog integrated circuit layout of an adaptive grid, which can determine the priority of routing according to information required for routing to perform linear routing.
The first technical scheme adopted by the invention is as follows: a method for wiring a self-adaptive grid analog integrated circuit layout comprises the following steps:
the method comprises the steps that the wiring width of a port is considered, path grid lines are explored on the basis of a self-adaptive grid of line exploration, and a three-dimensional path node grid is obtained;
carrying out constraint check on the three-dimensional path node grid through a Floird algorithm and a Primem algorithm, and selecting a wiring path to be optimized according to a check result;
and optimizing the wiring path to be optimized based on the resistance constraint and the time delay constraint to obtain the optimized wiring path.
Further, the step of obtaining a three-dimensional path node mesh by exploring the path mesh line based on the line exploration adaptive mesh in consideration of the wiring width of the port specifically includes:
setting a port with a self-iteration function by considering the wiring width of the ports and the jump layer and length of connecting wires among the ports;
considering the influence of wiring obstacles, setting connection points according to the ports with the self-iteration function, wherein the connection points have the self-adjustment function;
searching the connection points based on the routing search direction and the routing rule to generate path grid lines;
embedding path grid lines into three-dimensional path node grid management to generate path nodes of different connection points;
and carrying out communication processing on path nodes generated by exploring different connection points to obtain a three-dimensional path node grid.
Further, the track exploring direction specifically includes:
setting a corresponding routing exploration direction according to the layer number property of the wiring;
for single-layer wiring, four routing exploration directions of east, south, west and north are set;
for the multilayer wiring, the east, south, west, north, upper and lower trace exploration directions are set.
Further, the routing rule specifically includes:
presetting a wiring path in a ray form from a starting point coordinate to a specified direction for exploration;
determining the farthest position where the direction can reach through DRC rule constraint and a wiring map environment, and determining the coordinates of optional nodes of a path;
and generating path grid lines according to the coordinates of the optional nodes of the path.
Further, the step of embedding the path grid lines into the three-dimensional path node grid management to generate the path nodes specifically includes:
judging the path grid lines from the path grid lines to the three-dimensional path node grid;
judging that orthogonal nodes exist among path grid lines on the same layer, and selecting orthogonal node coordinates as path nodes;
and judging that orthogonal nodes exist between the grid lines of the adjacent layers of paths, and selecting the positions of the orthogonal nodes to set a new layer-hopping path and the corresponding layer-hopping path grid lines.
Further, the step of performing constraint check on the three-dimensional path node mesh through a freouard algorithm and a primum algorithm, and selecting a wiring path to be optimized according to a check result specifically includes:
simplifying the three-dimensional path node grid to obtain a two-port wiring path;
setting a path scoring rule, wherein the path scoring rule adopts a Floeider algorithm;
selecting a two-port wiring path which meets a path scoring rule, and generating a shortest two-port wiring path;
based on the Polemm algorithm, the path node of the shortest two-port wiring path is used as a graph argument point, and the grid line of the shortest two-port wiring path is used as a complete graph, so that the wiring path to be optimized is obtained.
Further, the path scoring rules include a resistance constraint, a capacitance constraint, and an area constraint, wherein:
the method comprises the steps of taking the path resistance value meeting a reference resistance as a condition, and constraining the line widths of all parts of a path through resistance information;
and on the premise that the resistance value of the path meets the reference resistance, considering capacitance constraint and taking the capacitance constraint condition or the area constraint condition of the path as a scoring reference.
Further, the step of optimizing the wiring path to be optimized based on the resistance constraint and the delay constraint to obtain an optimized wiring path specifically includes:
taking as variables factors that affect the wiring path resistance, including the resistance of the metal portion and the resistance of the via portion;
acquiring the line width of a wiring path in a matrix calculation mode based on DRC rule constraint;
regulating and controlling the resistance of the wiring path according to the line width of the wiring path, so that the resistance of the wiring meets a preset resistance value;
and based on an Elmore model, performing matrix operation on the line width of the wiring path to obtain the line width variable of the optimal delay, so as to obtain the optimized wiring path.
Further, optimizing the wiring path to be optimized further includes optimizing the shape of the port, which specifically includes:
judging the position information of the through hole and the port;
judging that the through hole is placed in the port, reducing the ground coupling capacitance generated by the through hole, and optimizing the through hole according to the shape of the port;
when the through hole is judged not to be placed in the port, optimization of the row and the column of the through hole is carried out according to the constraint that the superposition area of the through hole and the port is maximum
The second technical scheme adopted by the invention is as follows: an adaptive-grid analog integrated circuit layout routing system, comprising:
the acquisition module is used for exploring a path grid line based on a self-adaptive grid of line exploration by considering the wiring width of the port to acquire a three-dimensional path node grid;
the constraint module is used for carrying out constraint check on the three-dimensional path node grid through a Floird algorithm and a Primem algorithm and selecting a wiring path to be optimized according to a check result;
and the optimization module is used for optimizing the wiring path to be optimized based on the resistance constraint and the time delay constraint to obtain the optimized wiring path.
The method and the system have the beneficial effects that: the invention explores the route mesh lines based on the self-adaptive grids of the line exploration, does not need to construct grids in advance, reduces the occupation of memory resources, carries out DRC rule (physical design rule) check on a directly preset metal route, can place the metal route in the most compact mode, carries out constraint check on a three-dimensional route node grid through a Floeard algorithm and a Primem algorithm, simplifies the three-dimensional route node grid, considers the resistance of the route between ports in a routing route with excellent performance, and optimizes the routing route to be optimized through resistance constraint and time delay constraint, calculates the optimal time delay line width variable, obtains better time delay performance and completes the route optimization under time delay constraint in order to obtain a reasonable multi-port line network, thereby simplifying the routing problem into the graph theory problem.
Drawings
FIG. 1 is a flow chart of the steps of a method for routing an analog integrated circuit layout for an adaptive grid according to the present invention;
FIG. 2 is a block diagram of the layout and wiring system of an adaptive grid analog integrated circuit of the present invention;
FIG. 3 is a flow chart of the analog integrated circuit layout wiring method of the adaptive grid of the present invention;
FIG. 4 is a schematic diagram of port connection point setup and adaptation according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of an embodiment path node grid;
FIG. 6 is a schematic diagram of corresponding routing path combinations according to groups of two ports in accordance with the present invention;
FIG. 7 is a diagram illustrating a structure of a SMTP spanning Steiner tree calculated by the Prime algorithm according to the present invention;
FIG. 8 is a schematic diagram of a path net in the form of a Steiner tree of the present invention;
FIG. 9 is a diagram of an example of a resistance constrained precision optimized path in accordance with an embodiment of the present invention;
FIG. 10 is a diagram of an example of a delay constrained precision optimized path in accordance with an embodiment of the present invention;
FIG. 11 is a diagram of an example of via optimization according to an embodiment of the present invention;
FIG. 12 is a diagram of an example of a multi-level layout test of an actual IC layout according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the figures and the specific embodiments. The step numbers in the following embodiments are provided only for convenience of illustration, the order between the steps is not limited at all, and the execution order of each step in the embodiments can be adapted according to the understanding of those skilled in the art.
Referring to fig. 1 and 3, the invention provides a method for routing a self-adaptive grid analog integrated circuit layout, comprising the following steps:
s1, preprocessing wiring information;
specifically, before wiring, firstly, the order of wiring needs to be determined, and the ports are sequenced according to port information for wiring, in an integrated circuit layout, the shape of each port is generally a polygon, a reasonable port connection point is calculated by referring to a common centroid of the ports with the same connection relation, and the next step is carried out, as shown in fig. 4, according to the positions of a connection point 200 and a connection point 201 determined by a port 204 and a port 205; meanwhile, considering the influence of obstacles during wiring, a connection point can have a function of self-adjusting the position of the connection point during wiring, as shown in fig. 4, the obstacle 206 interferes with the routing, the position of the path node 202 generated according to the adaptive grid 206 is a more reasonable connection point, and the connection point of the port 204 is updated from the connection point 200 to the connection point 202 during wiring;
further, setting the line width of a port leading-out wire according to the position of the connection point determined by the port; meanwhile, the influence of layer jump and detour of a path on the path length during wiring is considered, the line width of the port leading-out wiring has a self-iteration function, and the line width of the port leading-out wiring can be updated again by using the completed path information in wiring iteration.
S2, constructing a self-adaptive grid model based on line exploration;
specifically, before conducting routing exploration, firstly, the direction and rule of routing exploration need to be determined;
the trace exploration direction is set as: on a single-layer plane, the exploration directions are set to be east, south, west and north; in a multilayer plane, on the basis of plane wiring, increasing exploration directions in an upward direction and a downward direction;
the routing rule is set as follows: presetting a metal path in a ray form from a starting point coordinate to a specified direction for searching, determining the farthest position which can be reached in the direction after checking the front distance and the side distance between DRC (physical design rule check) and an obstacle, determining the optional node coordinate of the path, checking the obstacle which is positioned near the starting point and is opposite to the searching direction, and limiting the reachable farthest distance searched by a line according to the DRC (physical design rule); generating a path optional node and simultaneously generating a path grid line with a starting point pointing to an end point, as shown in fig. 5, searching a connection point v0, a connection point v1 and a connection point v2 of a port 300, a port 301 and a port 302 in a set direction like a periphery, wherein the connection point v1 searches in a north direction to meet an obstacle 303, and a reachable coordinate point v10 is determined according to a DRC rule (physical design rule); searching v4 from v10 in the east direction, wherein the farthest distance d4 is constrained by d3 according to DRC rules (physical design rules);
incorporating the path selectable nodes and path grid lines generated by the line exploration into three-dimensional path node grid management, and meanwhile, if the path grid lines on the same layer are orthogonal, setting new path nodes at the orthogonal coordinate position; if the path grid lines of adjacent layers are orthogonal, setting a new layer-jumping path and a corresponding layer-jumping path grid line at the orthogonal coordinate position, wherein any point in the generated path node grid can reach an appointed path node through limited transfer, and the grid path lines of the adjacent layers are orthogonal in projection, setting path nodes at the two adjacent layers at the orthogonal coordinate position, generating a new path grid line to penetrate through the adjacent layers and connect the two path nodes of different layers, as shown in fig. 5, path grid lines v10-v4 are orthogonal to path grid lines v7-v9, and setting a new path node v8 to enable the path node grids to complete communication.
S3, building a graph theory model and calculating a path based on the three-dimensional path node grid;
specifically, a plurality of ports with the same connection relation generally exist, in order to obtain a reasonable multi-port wire network, the wiring problem is simplified into a graph theory problem, the multi-port connection problem is conveniently and efficiently processed from the perspective of the graph theory, and for the multi-port wiring, the wiring between two ports is simplified firstly;
when calculating a wiring path between two ports, a path scoring system used by a Floyd algorithm (a freouard algorithm) is used, and the physical properties of the path are fully considered. Utilizing resistance information to constrain the line widths of all parts of the path, enabling the path to be equal to a resistance calculation approximate formula, considering capacitance constraint under the condition that an equation is established, and calculating the capacitance of the path by using the obtained line width variable as a grading reference; if capacitance constraint does not need to be considered between the ports, and in order to minimize the area resources occupied by the paths, the scoring reference of the paths is corrected into a projection area;
after multi-porting into a plurality of groups of two ports and obtaining corresponding wiring paths, merging path node networks passed by the wiring paths to obtain a path node extracted from a path node grid based on the position of each port as a graph point and a path grid line as a complete graph of edges, obtaining a path Steiner tree by using a Prime algorithm in the complete graph, combining the path nodes according to the corresponding wiring paths of the plurality of groups of two ports into the complete graph of FIG. 6, calculating a minimum spanning tree by using the Prime algorithm in the complete graph, and deleting branches of non-ports to obtain the Steiner tree of FIG. 7. And obtaining a Steiner tree graph according to calculation, extracting the path corresponding to the path node grid, and obtaining the path wire network in the Steiner tree form shown in the figure 8.
S4, wiring iteration and convergence;
specifically, whether the obtained route net in the Steiner tree mode meets the requirement or not is judged according to the wiring information obtained before wiring, and if the route net meets the requirement, the next route optimization is carried out; and if the historical path information does not meet the requirement, entering a historical path information storage container, and recalculating the connection point of the modified port and the line width of the port leading-out routing according to the information in the container.
S5, optimizing a path;
specifically, the resistance of the path between the ports needs to be considered for the routing path with excellent performance, the delay condition of the path transmission information needs to be considered for the path passing through the signal, and the path is optimized under the constraint condition for obtaining the routing path with excellent performance, and the optimization mode is as follows:
the method for accurately optimizing the path under the resistance constraint comprises the following steps: the resistance of the path consists of the resistance of a metal part and the resistance of a through hole part, in order to accurately regulate and control the resistance value of the path, the line width of each section of metal of the path is used as a variable, the through hole is set to be constrained by the line width of adjacent sections of metal, DRC rule constraint (physical design rule constraint) is used as a supplement condition, the line width of each section of metal is solved through matrix operation, the aim of accurately regulating and controlling the resistance of the path is achieved, and a solution set with the minimum discrete degree is selected under the condition that a plurality of solution sets exist; as shown in fig. 9, the paths are connected to two ports, the resistances required by the two paths are distributed according to the current proportion according to the information obtained before wiring, the line width of each metal is used as a variable, and the line width of each metal is solved by matrix calculation, so that each metal meets the distributed resistance value;
the method for accurately optimizing the path under the time delay constraint comprises the following steps: in a two-port path under the condition of delay constraint, the line width of segmented metal can influence the delay between ports, the line width of each segment of metal is taken as a variable, the optimal delayed line width variable is calculated through matrix operation and condition constraint on the basis of an Elmore model, and path optimization under the delay constraint is completed; as shown in fig. 10, the line width of the path is taken as a variable, based on the Elmore model, according to the delay formula and DRC rule (physical design rule constraint) constraint, such as that the DRC constraint minimum line width in the figure is 0.1u, and a line width solution set is obtained through matrix calculation, where the line widths of two sections of metal in the figure are set to be 0.18u and 0.1u, so that a better delay performance is obtained;
the method for optimizing the through hole comprises the following steps: the through holes are optimized according to the shapes of the ports, when the through holes cannot be completely placed in the ports, the rows and the columns of the through holes are modified according to the constraint that the superposition area of the through holes and the port is the largest, as shown in fig. 11, the set through holes are located at the positions of the resistance ports, in order to reduce the ground capacitance of the through holes, the rows and the columns of the through holes are modified, and the through holes are matched with the shapes of the ports firstly under the condition that the number of the through hole arrays is not changed, so that the effect of the largest area superposition is achieved.
And S6, outputting the layout.
Specifically, fig. 12 is a diagram of a multilayer wiring example, in which wiring is performed in a laid-out layout according to the above-described procedure, the overall result is as shown in the figure, and the output GDS layout file is subjected to DRC check and LVS check in Virtuoso.
Referring to fig. 2, an adaptive-mesh analog integrated circuit layout routing system includes:
the acquisition module is used for exploring a path grid line based on a self-adaptive grid of line exploration by considering the wiring width of the port to acquire a three-dimensional path node grid;
the constraint module is used for carrying out constraint check on the three-dimensional path node grid through a Floird algorithm and a Primem algorithm and selecting a wiring path to be optimized according to a check result;
and the optimization module is used for optimizing the wiring path to be optimized based on the resistance constraint and the time delay constraint to obtain the optimized wiring path.
The contents in the above method embodiments are all applicable to the present system embodiment, the functions specifically implemented by the present system embodiment are the same as those in the above method embodiment, and the beneficial effects achieved by the present system embodiment are also the same as those achieved by the above method embodiment.
While the preferred embodiments of the present invention have been illustrated and described, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A method for wiring a self-adaptive grid analog integrated circuit layout is characterized by comprising the following steps:
the method comprises the steps that the wiring width of a port is considered, path grid lines are explored on the basis of a self-adaptive grid of line exploration, and a three-dimensional path node grid is obtained;
carrying out constraint check on the three-dimensional path node grid through a Floird algorithm and a Primem algorithm, and selecting a wiring path to be optimized according to a check result;
and optimizing the wiring path to be optimized based on the resistance constraint and the time delay constraint to obtain the optimized wiring path.
2. The method as claimed in claim 1, wherein the step of obtaining a three-dimensional path node mesh by exploring path mesh lines based on the adaptive mesh for line exploration in consideration of the routing width of the port comprises:
setting a port with a self-iteration function by considering the wiring width of the ports and the jump layer and length of connecting wires among the ports;
considering the influence of wiring obstacles, setting connection points according to the ports with the self-iteration function, wherein the connection points have the self-adjustment function;
searching the connection points based on the routing search direction and the routing rule to generate path grid lines;
embedding path grid lines into three-dimensional path node grid management to generate path nodes of different connection points;
and carrying out communication processing on path nodes generated by exploring different connection points to obtain a three-dimensional path node grid.
3. The method of claim 2, wherein the routing direction comprises:
setting a corresponding routing exploration direction according to the layer number property of the wiring;
for single-layer wiring, four routing exploration directions of east, south, west and north are set;
for the multilayer wiring, the east, south, west, north, upper and lower trace exploration directions are set.
4. The method according to claim 3, wherein the routing rule specifically includes:
presetting a wiring path in a ray form from a starting point coordinate to a specified direction for exploration;
determining the farthest position where the direction can reach through DRC rule constraint and a wiring map environment, and determining the coordinates of optional nodes of a path;
and generating path grid lines according to the coordinates of the optional nodes of the path.
5. The method of claim 4, wherein the step of embedding the path grid lines into the three-dimensional path node grid management to generate the path nodes comprises:
judging the path grid lines from the path grid lines to the three-dimensional path node grid;
judging that orthogonal nodes exist among path grid lines on the same layer, and selecting orthogonal node coordinates as path nodes;
and judging that orthogonal nodes exist between the grid lines of the adjacent layers of paths, and selecting the positions of the orthogonal nodes to set a new layer-hopping path and the corresponding layer-hopping path grid lines.
6. The method as claimed in claim 5, wherein the step of performing constraint check on the three-dimensional path node mesh by using a Flouard algorithm and a Primem algorithm and selecting the wiring path to be optimized according to the check result specifically comprises:
simplifying the three-dimensional path node grid to obtain a two-port wiring path;
setting a path scoring rule, wherein the path scoring rule adopts a Floeider algorithm;
selecting a two-port wiring path which meets a path scoring rule, and generating a shortest two-port wiring path;
based on the Polemm algorithm, the path node of the shortest two-port wiring path is used as a graph argument point, and the grid line of the shortest two-port wiring path is used as a complete graph, so that the wiring path to be optimized is obtained.
7. The method of claim 6, wherein the path scoring rules include resistance constraints, capacitance constraints, and area constraints, and wherein:
the method comprises the steps of taking the path resistance value meeting a reference resistance as a condition, and constraining the line widths of all parts of a path through resistance information;
and on the premise that the resistance value of the path meets the reference resistance, considering capacitance constraint and taking the capacitance constraint condition or the area constraint condition of the path as a scoring reference.
8. The method according to claim 7, wherein the step of optimizing the routing path to be optimized based on the resistance constraint and the delay constraint to obtain the optimized routing path comprises:
taking as variables factors that affect the wiring path resistance, including the resistance of the metal portion and the resistance of the via portion;
acquiring the line width of a wiring path in a matrix calculation mode based on DRC rule constraint;
regulating and controlling the resistance of the wiring path according to the line width of the wiring path, so that the resistance of the wiring meets a preset resistance value;
and based on an Elmore model, performing matrix operation on the line width of the wiring path to obtain the line width variable of the optimal delay, so as to obtain the optimized wiring path.
9. The method according to claim 8, wherein the optimizing the routing path to be optimized further comprises optimizing a shape of the port, which specifically comprises:
judging the position information of the through hole and the port;
judging that the through hole is placed in the port, reducing the ground coupling capacitance generated by the through hole, and optimizing the through hole according to the shape of the port;
and when the through hole is judged not to be placed in the port, optimizing the row of the through hole according to the constraint that the superposition area of the through hole and the port is the largest.
10. A grid-adaptive analog integrated circuit layout wiring system is characterized by comprising the following modules:
the acquisition module is used for exploring a path grid line based on a self-adaptive grid of line exploration by considering the wiring width of the port to acquire a three-dimensional path node grid;
the constraint module is used for carrying out constraint check on the three-dimensional path node grid through a Floird algorithm and a Primem algorithm and selecting a wiring path to be optimized according to a check result;
and the optimization module is used for optimizing the wiring path to be optimized based on the resistance constraint and the time delay constraint to obtain the optimized wiring path.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116757144A (en) * | 2023-07-07 | 2023-09-15 | 上海韬润半导体有限公司 | Method, system and storage medium for optimizing power supply network and saving winding resources |
| CN117217156A (en) * | 2023-08-31 | 2023-12-12 | 中山大学 | Radio frequency circuit layout iteration method, equipment and medium based on Bayesian optimization |
| CN117688899A (en) * | 2024-02-02 | 2024-03-12 | 深圳华强电子网集团股份有限公司 | Wiring analysis optimizing system based on high-density integrated circuit |
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