CN112733486A - Intelligent wiring method and system for chip design - Google Patents
Intelligent wiring method and system for chip design Download PDFInfo
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Abstract
The invention relates to an intelligent wiring method and system for chip design, which mainly comprises the steps of wiring components which are arranged in advance, namely, firstly obtaining a binary image of a chip which is not wired, automatically wiring by utilizing a wire searching mechanism according to the connection relation between the preset components and corresponding connection pins to obtain a wiring diagram, and then training the wired chip through a constructed neural network model to realize the wiring of the chip to be wired; the invention can better determine the connection between two components through the set search wiring mechanism, realizes automatic wiring, and can realize the wiring of a large batch of chips by combining with a neural network model.
Description
Technical Field
The invention relates to an intelligent wiring method and system for chip design, and belongs to the field of automatic wiring of integrated circuits.
Background
With the rapid development of integrated circuit technology, integrated circuits enter an ultra-deep submicron era, so that the characteristic size of electronic devices is smaller and smaller, the scale of chips is larger and larger, more and more components can be integrated on a single chip, the complexity is increased sharply, the wiring method in a layout cannot meet the design requirement of the integrated circuits by a manual wiring method, and the automatic wiring of a computer occupies a larger and larger proportion in layout design wiring. The routing algorithm has an extremely important influence on the speed and efficiency of routing, and how to design an algorithm which requires less time and space, has lower complexity and higher efficiency becomes a huge problem faced by semiconductor computer aided design. For detailed wiring, a conventional planar wiring Algorithm, such as the Lee's Maze Routing Algorithm (Lee's Maze Routing Algorithm), is usually used for determining a shortest path for connection between two points of a layout, specifically, the shortest path is obtained by dividing the layout into grids, starting from a starting grid, numbering all unused adjacent grids in an ascending order, and finally searching for a termination grid. However, the breadth-first traversal algorithm is adopted, the algorithm efficiency is not high, and meanwhile, the divided grids need to be numbered, so that the method is complex.
Disclosure of Invention
The invention aims to provide an intelligent wiring method and an intelligent wiring system for chip design, which are used for solving the problems of complex method and low efficiency in the existing chip design.
In order to solve the problems, the invention adopts the following technical scheme:
an intelligent wiring method for chip design comprises the following steps:
the method comprises the following steps: acquiring an image of a non-wiring chip, wherein the image of the non-wiring chip is a binary image;
step two: automatically wiring by utilizing a search wiring mechanism according to the preset connection relation between the components and the corresponding connection pins to obtain a wiring diagram;
step three: constructing a wiring network model, and training the wiring network model to obtain a trained network model;
step four: inputting a test wiring diagram to be wired into the trained network model, and outputting the test wiring diagram;
the process of searching the wiring mechanism is as follows:
1) taking a connection point of a component in the binary image as an initial point PNConnected to as a target point PMM and N are serial numbers of pixel points of non-0 elements in the binary image, and the vector pointing from the initial point to the target point is
2) Connection point PNAnd PMJudging whether a point with a pixel value of a exists on the connecting line, if not, using the connecting line as a connecting point PNAnd PMThe lines between the two are arranged and the wiring is carried out; if so, performing step 3);
3) searching matrix A by direction to obtain initial point PNPixel coordinate p ofi,jSearching eight wiring areas near the area where the central point is located, wherein the eight wiring areas respectively take the pixel coordinate as pi+2,j-2,pi-2,j,pi-2,j-2,pi,j-2,pi,j+2,pi+2,j-2,pi+2,j,pi+2,j+2Searching as a central point to obtain a search matrix B corresponding to each central pointnN is 1, …, 8; combining matrix A with matrix BnPerforming point-by-point multiplication and then summing, dividing areas which are continuously searched according to the summing result, and when the summing result is less than or equal to mab and more than or equal to 3ab, and components exist in the direction of the wiring area, the wiring area does not perform wiring, otherwise, determining the wiring area which can perform wiring, and obtaining a representation model of the wiring area of the initial point; wherein, the direction search matrix A and the search matrix BnAre all m x m, wherein m is an odd number;
4) according toObtaining the expression model of the wiring area of the initial point, combining the wiring path rule to obtain the optimal connection point on the wiring area, and performing the initial point PNWiring to the optimal connection point;
5) taking the moved connection point as an initial point, obtaining a vector from the moved connection point to a target point for updating the vector
Repeating the steps 3) -4), and searching a new connecting point until a target point is searched;
6) and after finishing wiring, adjusting the wiring according to the wiring adjustment rule to obtain the wiring of the whole chip.
Further, obtaining a representation model of the routing region includes:
when the wiring area is one, the Gaussian distribution corresponding to the forward search point is set as
As a representative model of the routing area; set the Gaussian distribution corresponding to the search point in the oblique direction as
As a representative model of the routing area; the positive direction search point judgment mode is that the search point coordinate has only the change of i or j compared with the initial point coordinate, otherwise, the search point is an oblique direction search point, namely the search point coordinate has the change compared with the initial point coordinate i and j;
when two wiring areas are adjacent, connecting two Gaussian distribution peak points corresponding to the two wiring areas, and taking an outer edge line as a representation model of the two adjacent points; and when the two wiring areas are not adjacent, forming a representation model according to the Gaussian distribution acquired by the single search point mode.
Further, the routing path rule includes the steps of:
step A, obtaining a vector
Relative to the angle of the zero direction, taking the angle as a mean value mu and taking the sigma as mu, and obtaining a representation model of the reference direction
Step B, according to the obtained representation model of the reference direction
Representation model for initial point
Correcting to obtain a corrected model
Step C, representing the model by the initial point
The corresponding angles at the positions of mu, mu +/-sigma, mu +/-2 sigma and mu +/-3 sigma are used as pre-search directions to correct the model
Is calculated to obtain
Will be provided with
And taking the direction under the corresponding angle as a search direction, taking the pixel point closest to the search direction in the search area as a connection point along the search direction, and wiring the initial point and the connection point.
Further, the expression of the correction model is as follows:
wherein the content of the first and second substances,
and
for modifying the reference-direction representation model for modifying the coefficients
The influence on the final representation model, theta being the angle of the representation model at the initial point,
to represent a model
K is an adjustment coefficient.
Further, in the second step, after the target point is searched, the method further comprises the step of wiring in a reverse direction:
taking the target point as an initial point, carrying out wiring search according to the steps 3) to 6), obtaining reverse wiring from the target point to the initial point, judging whether the wiring direction from the initial point to the target point is intersected with the reverse wiring, and if so, forming wiring from the initial point to the intersection point and wiring from the target point to the intersection point into wiring of the initial point and the target point; if the two directions are not intersected, the nearest neighbor direction except the searched direction is selected from the pre-search directions to be used as a new search direction.
Further, the wiring adjustment rule includes adjustment of superposition of wiring, adjustment of a line pitch, adjustment of a pitch between a line and a component, and adjustment of a wiring corner.
The invention also comprises an intelligent wiring system for chip design, which comprises a memory and a processor, wherein the processor executes the scheme of the intelligent wiring method for chip design stored in the memory.
The invention has the beneficial effects that:
according to the invention, pre-arranged components are wired, namely, a binary image of a non-wired chip is firstly obtained, and automatic wiring is carried out by utilizing a search wiring mechanism according to the preset connection relation between the components and corresponding connection pins to obtain a wiring diagram; the searching mechanism can well determine the connection between the two components, and automatic wiring is realized.
Meanwhile, the invention can train the wired chip through the constructed network model, realizes the wiring of the chip to be wired and improves the wiring efficiency.
Drawings
In order to more clearly illustrate the technical solution of the embodiment of the present invention, the drawings needed to be used in the embodiment will be briefly described as follows:
fig. 1 is a schematic flowchart of an embodiment of an intelligent wiring method for chip design according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be described below with reference to the drawings in the embodiments of the present invention. In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
It should be noted that the specific scenario targeted by the present invention is a wiring scenario of chip design, that is, wiring simulation is performed during signal integrity simulation, and an object of the present invention is an ideal simulation image in which components are already pre-arranged, that is, no situation that the components are arranged unreasonably, and the present invention can be directly used for a subsequent simulation image of component wiring.
The invention provides an intelligent wiring method for chip design, which comprises the following steps as shown in figure 1:
the method comprises the following steps: acquiring an image of a non-wiring chip, wherein the image of the non-wiring chip is a binary image;
in the embodiment, the actual sizes of the components are arranged in the simulation image in advance according to a proportion, then, the component images are collected, the values of the pixel points of the components in the collected component images are set to a, a belongs to (0, 255), and the values of other pixel points are set to 0, so that the chip images without wiring are obtained.
Step two: automatically wiring by utilizing a search wiring mechanism according to the preset connection relation between the components and the corresponding connection pins to obtain a wiring diagram;
the connection relationship between the components is known and determined for the connection relationship between the components in the designed chip circuit, that is, the relationship between the pins of each component and the pins of the components to be connected is determined.
The automatic wiring process of the search wiring mechanism comprises the following steps:
1) taking a connection point of a component in the binary image as an initial point PNConnected to as a target point PMM and N are serial numbers of pixel points of non-0 elements in the binary image, and the vector pointing from the initial point to the target point is
2) Connection point PNAnd PMJudging whether a point with a pixel value of a exists on the connecting line, if not, using the connecting line as a connecting point PNAnd PMThe lines between the two are arranged and the wiring is carried out; if so, performing step 3);
the pixel value a in this embodiment is 1, which makes the subsequent calculation simpler.
3) Searching matrix A by direction to obtain initial point PNPixel coordinate p ofi,jSearching eight wiring areas near the area where the central point is located, wherein the eight wiring areas respectively take pixel coordinates aspi+2,j-2,pi-2,j,pi-2,j-2,pi,j-2,pi,j+2,pi+2,j-2,pi+2,j,pi+2,j+2Searching as a central point to obtain a search matrix B corresponding to each central pointnN is 1, …, 8; combining matrix A with matrix BnPerforming point-by-point multiplication and then summing, dividing areas which are continuously searched according to the summing result, and when the summing result is less than or equal to mab and more than or equal to 3ab, and components exist in the direction of the wiring area, the wiring area does not perform wiring, otherwise, determining the wiring area which can perform wiring, and obtaining a representation model of the wiring area of the initial point; wherein, the direction search matrix A and the search matrix BnAll m × m, where m is an odd number, in this embodiment, 3, and each element of the directional search matrix a is b, and the value range is 1 to 255.
The process of obtaining the representation model of the routing area at the initial point in the above embodiment is as follows:
it should be noted that, there may be one or more routing areas defined in the above embodiments; the wiring areas with different numbers and in different directions have different representation models, and the specific analysis is as follows:
when the determined wiring area capable of wiring is one, the Gaussian distribution corresponding to the wiring area is taken as the representation model, and the Gaussian distribution corresponding to the forward search point is
Gaussian distribution of point correspondences for search in oblique directions
The positive direction search point judgment mode is that the search point coordinate has only the change of i or j compared with the initial point coordinate, otherwise, the search point is an oblique direction search point, namely the search point coordinate has the change compared with the initial point coordinate i and j;
when the determined wiring areas capable of wiring are at least two, the following cases are distinguished:
when the number of the wiring areas is two, the wiring areas are divided into adjacent areas and non-adjacent areas; when two wiring areas are adjacent, the Gaussian distributions obtained in the single search point mode are combined to form a representation model of two adjacent points, specifically, two Gaussian distributions are respectively generated for the two search points, the peak points of the two Gaussian distributions are connected, and an outer edge line is used as the representation model of the two adjacent points; when the two wiring areas are not adjacent, a representation model is formed according to the Gaussian distribution obtained by the single search point mode;
when the number of the wiring areas is at least three, the wiring areas can be divided into the situations of full adjacency, non-full adjacency and non-adjacency, the non-full adjacency situation can be regarded as being composed of a plurality of full adjacency and single search points, and the full adjacency search points are constructed according to the construction mode of the adjacent search points;
4) according to the representation model of the wiring area for obtaining the initial point, combining the wiring path rule to obtain the optimal connection point on the wiring area, and carrying out the initial point pi,jWiring to the optimal connection point;
the routing path rule in this embodiment is:
step A, obtaining a vector
With respect to the angle of the zero direction, taking the angle as the mean value mu and the sigma as pi, a representation model of the reference direction is obtained
Step B, according to the obtained representation model of the reference direction
Representation model for initial point
Correcting to obtain a representation model of the actual wiring direction;
wherein, the expression of the correction model is as follows:
wherein the content of the first and second substances,
and
for modifying the reference-direction representation model for modifying the coefficients
The influence on the final representation model, theta is an angle value,
is a Gaussian distribution
The distribution mean value of (1) is k, which is an adjustment coefficient, and the range is [0, + ∞), and in this application, k is 1, and the implementer can adjust the influence adjustment coefficient k according to the actual situation, and the closer the k value is to 0, the greater the influence of the reference direction on the final representation model is.
Step C, representing the model by the initial point
The angles corresponding to the positions of mu, mu +/-sigma, mu +/-2 sigma and mu +/-3 sigma are used as pre-search directions, and the representation model of the actual wiring direction is carried out
Is calculated to obtain
According to the number of wiring regions, and
and taking the direction under the corresponding angle as a search direction, taking the pixel point which is closest to the search direction in the search area in the search direction as a connection point, and wiring the initial point and the connection point.
The zero direction in the above embodiments is defined as pi,jPoint of direction pi,j+2The vector of (1) is in the zero direction, and the included angle between each search point and the zero direction is distributed in [0,2 pi ].
The scheme in the above embodiment is to select 7 angular directions of gaussian distribution in order to reduce the amount of calculation; of course, as another embodiment, more angles may be selected in order to more accurately obtain the actual wiring direction.
It should be noted that, if the distances between the multiple pixel points in the search area and the search direction are the same, the pixel point farthest from the initial point is selected as the connection point, and if the pixel point farthest from the initial point is not one, one of the pixel points is randomly selected as the connection point.
As another embodiment, in this embodiment, the movement of multiple pixels may be performed at a time, specifically, the number m (m) of pixels to be moved is set>1) Starting from the initial point, let it represent the model as
Selecting a direction corresponding to a maximum representation value in the representation model to search a nearest pixel point, and then using the representation model of the pixel point
Continuing the search, repeating the process until a representation model is obtained
Multiplying all the representation models in the period to obtain a final representation model F, taking the maximum value in the final representation model F, and representing the maximum value as Max (F), and selecting the angle corresponding to the maximum value, wherein the angle is the direction from the initial point to the final search point;
5) taking the moved connecting point as an initial point to obtain the initial point to a targetVector of punctuation for updating the vector
Repeating the step 3), and searching a new target point P4Until the target point is searched;
further, in order to ensure the accuracy of wiring, in the invention, after the target point is searched, the wiring search can be carried out by taking the target point as an initial point according to the steps 3) -6), reverse wiring from the target point to the initial point is obtained, whether the forward wiring direction and the reverse wiring intersect or not is judged, if so, an intersection point is selected, and the forward wiring from the initial point to the intersection point and the reverse wiring from the target point to the intersection point form final wiring; if the two directions are not intersected, the nearest neighbor direction except the searched direction is selected from the pre-search directions to be used as a new search direction.
6) And after finishing wiring, adjusting the wiring according to the wiring adjustment rule to obtain the wiring of the whole chip.
In this embodiment, the wiring adjustment rule after the wiring is completed includes:
1. when a part overlapped after wiring exists, comparing Max (F) and less Max (F) according to two groups of two sections of wiring corresponding to the overlapped part, and selecting the adjustment mode as the correction direction;
2. setting the line width, the line spacing and the spacing between lines and components, and adjusting the wiring; specifically, for line segments which do not meet the conditions, lines far away from the components are adjusted; arranging routing, namely adjusting the lines in the oblique direction into the lines in the positive direction; setting corners, namely adjusting the corner points into a fixed obtuse angle form;
3. and sequentially deleting the less Max (F) wiring in the area which cannot be realized until the condition is met, reserving the wiring which meets the condition after adjustment, and reselecting the direction for wiring the deleted wire until the wiring of all the components meets the wiring optimization requirement.
It should be noted that the wiring adjustment rule can be added, deleted, and modified according to actual requirements.
Step three: constructing a wiring network model, and training the wiring network model to obtain a trained network model;
the wiring network model constructed in this embodiment is a neural network model, and a specific training process is not described herein too much because it is the prior art.
Wherein, the training of the wiring network model is based on the wiring diagram which is already wired as output and the chip diagram which is not wired as input; therefore, according to the wiring diagram which is wired well, the wiring of the same chip in large batch can be realized, and the efficiency is improved.
Step four: and inputting the test wiring diagram to be wired into the trained network model, and outputting the test wiring diagram.
In this embodiment, in order to implement batch chip wiring, the network model can be trained by an artificial intelligence learning method according to the labeled training template, so as to implement batch chip wiring.
As another embodiment, the present invention further includes a step of evaluating the wiring of the test wiring diagram, specifically, the training set is artificially labeled and evaluated, a corresponding evaluation level is determined, then a neural network model is constructed and trained, the wiring diagram is output to the trained neural network model, and the corresponding wiring evaluation level is output.
Based on the same inventive concept as the method, the invention further provides an intelligent wiring system for chip design, which comprises a memory and a processor, wherein the processor executes the embodiment of the intelligent wiring method for chip design stored in the memory.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
Claims (7)
1. An intelligent wiring method for chip design is characterized by comprising the following steps:
the method comprises the following steps: acquiring an image of a non-wiring chip, wherein the image of the non-wiring chip is a binary image;
step two: automatically wiring by utilizing a search wiring mechanism according to the preset connection relation between the components and the corresponding connection pins to obtain a wiring diagram;
step three: constructing a wiring network model, and training the wiring network model to obtain a trained network model;
step four: inputting a test wiring diagram to be wired into the trained network model, and outputting the test wiring diagram;
the process of searching the wiring mechanism is as follows:
1) taking a connection point of a component in the binary image as an initial point PNConnected to as a target point PMM and N are serial numbers of pixel points of non-0 elements in the binary image, and the vector pointing from the initial point to the target point is
2) Connection point PNAnd PMJudging whether a point with a pixel value of a exists on the connecting line, if not, using the connecting line as a connecting point PNAnd PMThe lines between the two are arranged and the wiring is carried out; if so, performing step 3);
3) searching matrix A by direction to obtain initial point PNPixel coordinate p ofi,jSearching eight wiring areas near the area where the central point is located, wherein the eight wiring areas respectively take the pixel coordinate as pi+2,j-2,pi-2,j,pi-2,j-2,pi,j-2,pi,j+2,pi+2,j-2,pi+2,j,pi+2,j+2Searching as a central point to obtain a search matrix B corresponding to each central pointnN is 1, …, 8; combining matrix A with matrix BnPerforming point-by-point multiplication and then summing, dividing areas which are continuously searched according to the summing result, and when the summing result is less than or equal to mab and more than or equal to 3ab, and components exist in the direction of the wiring area, the wiring area does not perform wiring, otherwise, determining the wiring area which can perform wiring, and obtaining a representation model of the wiring area of the initial point; wherein, the direction search matrix A and the search matrix BnAre all m x m, wherein m is an odd number;
4) obtaining the optimal connection point on the wiring area by combining the wiring path rule according to the obtained representation model of the wiring area of the initial point, and carrying out the initial point PNWiring to the optimal connection point;
5) taking the moved connection point as an initial point, obtaining a vector from the moved connection point to a target point for updating the vector
Repeating the steps 3) -4), and searching a new connecting point until a target point is searched;
6) and after finishing wiring, adjusting the wiring according to the wiring adjustment rule to obtain the wiring of the whole chip.
2. The intelligent routing method for chip design according to claim 1, wherein obtaining the representation model of the routing region comprises:
when the wiring area is one, the Gaussian distribution corresponding to the forward search point is set as
As a representative model of the routing area; set the Gaussian distribution corresponding to the search point in the oblique direction as
As a representative model of the routing area; the positive direction search point judgment mode is that the search point coordinate has only the change of i or j compared with the initial point coordinate, otherwise, the search point is an oblique direction search point, namely the search point coordinate has the change compared with the initial point coordinate i and j;
when two wiring areas are adjacent, connecting two Gaussian distribution peak points corresponding to the two wiring areas, and taking an outer edge line as a representation model of the two adjacent points; and when the two wiring areas are not adjacent, forming a representation model according to the Gaussian distribution acquired by the single search point mode.
3. The intelligent routing method for chip design according to claim 2, wherein the routing path rule comprises the following steps:
step A, obtaining a vector
With respect to the angle of the zero direction, taking the angle as the mean value mu and the sigma as pi, a representation model of the reference direction is obtained
Step B, according to the obtained representation model of the reference direction
Representation model for initial point
Correcting to obtain a corrected model
Step C, representing the model by the initial point
The corresponding angles at the positions of mu, mu +/-sigma, mu +/-2 sigma and mu +/-3 sigma are used as pre-search directions to correct the model
Is calculated to obtain
Will be provided with
And taking the direction under the corresponding angle as a search direction, taking the pixel point closest to the search direction in the search area as a connection point along the search direction, and wiring the initial point and the connection point.
4. The intelligent wiring method for chip design according to claim 1, wherein the expression of the modified model is:
wherein the content of the first and second substances,
and
for modifying the reference-direction representation model for modifying the coefficients
The influence on the final representation model, theta being the angle of the representation model at the initial point,
to represent a model
K is an adjustment coefficient.
5. The intelligent routing method for chip design according to claim 1, wherein in step two, after searching for the target point, the method further comprises the step of routing in reverse direction:
taking the target point as an initial point, carrying out wiring search according to the steps 3) to 6), obtaining reverse wiring from the target point to the initial point, judging whether the wiring direction from the initial point to the target point is intersected with the reverse wiring, and if so, forming wiring from the initial point to the intersection point and wiring from the target point to the intersection point into wiring of the initial point and the target point; if the two directions are not intersected, the nearest neighbor direction except the searched direction is selected from the pre-search directions to be used as a new search direction.
6. The intelligent wiring method for chip design according to claim 1, wherein the wiring adjustment rules comprise adjustment of registration of wiring, adjustment of pitch of wires, adjustment of pitch between wires and components, and adjustment of corners of wiring.
7. An intelligent wiring system for chip design, comprising a memory and a processor, wherein the processor executes a program of an intelligent wiring method for chip design according to claims 1-6 stored in the memory.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113514475A (en) * | 2021-06-25 | 2021-10-19 | 深圳格芯集成电路装备有限公司 | Method for generating reference template for chip detection and related equipment |
| CN114065939A (en) * | 2021-11-22 | 2022-02-18 | 北京百度网讯科技有限公司 | Training method, device and equipment for quantum chip design model and storage medium |
| CN115238639A (en) * | 2022-09-23 | 2022-10-25 | 深圳鸿芯微纳技术有限公司 | Global wiring prediction method, device, equipment and storage medium |
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