CN114065939A

CN114065939A - Training method, device and equipment for quantum chip design model and storage medium

Info

Publication number: CN114065939A
Application number: CN202111387819.4A
Authority: CN
Inventors: 晋力京; 王子潇; 尹凯峰
Original assignee: Beijing Baidu Netcom Science and Technology Co Ltd
Current assignee: Beijing Baidu Netcom Science and Technology Co Ltd
Priority date: 2021-11-22
Filing date: 2021-11-22
Publication date: 2022-02-18
Anticipated expiration: 2041-11-22
Also published as: CN114065939B

Abstract

The disclosure provides a training method, a training device, equipment and a storage medium of a quantum chip design model, and relates to the field of quantum computing, in particular to the field of quantum chip design. The specific implementation scheme is as follows: obtaining a design parameter sample value of a sample quantum chip and a corresponding chip performance sample value; establishing an initial network model; inputting the chip performance sample value into the initial network model to obtain a design parameter predicted value; and training the initial network model according to the difference between the predicted value of the design parameter and the sample value of the design parameter to obtain a quantum chip design model, wherein the quantum chip design model is used for determining a corresponding target value of the design parameter according to a target value of the chip performance of a target quantum chip. Compared with the method that the design parameter target value is obtained by relying on artificial experience, the optimal design parameter can be found more quickly by utilizing the parameter target value obtained by the trained model, and the time and resource cost of quantum chip design are greatly reduced.

Description

Training method, device and equipment for quantum chip design model and storage medium

Technical Field

The disclosure relates to the field of quantum computing, in particular to the field of quantum chip design, and specifically relates to a training method and device for a quantum chip design model, an electronic device and a storage medium.

Background

As the logic necessity of breaking through the classical physical limit of the chip size and the symbolic technology of the post-Moore times, the quantum computation and the related technology thereof have attracted great attention. Nowadays, quantum computing is advanced to some extent from an application level, an algorithm level or a hardware level, and meanwhile, various difficulties and challenges are faced. Particularly, in a quantum hardware level, in a quantum chip design process, multiple specific sizes of capacitors on a chip all affect the overall energy value of the quantum chip, but at the same time, the design of each specific size has a large degree of freedom and does not form a unified specification, so that in the existing design scheme, designers need to give multiple groups of size values by experience, and then the optimal size result is finally obtained through repeated testing and optimization of simulation experiments.

Disclosure of Invention

The present disclosure provides a method and apparatus for training a quantum chip design model, a device (also referred to as an electronic device), and a storage medium.

According to a first aspect of the present disclosure, there is provided a method for training a quantum chip design model, including:

obtaining a design parameter sample value of a sample quantum chip and a corresponding chip performance sample value;

establishing an initial network model;

inputting the chip performance sample value into the initial network model to obtain a design parameter predicted value;

and training the initial network model according to the difference between the predicted value of the design parameter and the sample value of the design parameter to obtain a quantum chip design model, wherein the quantum chip design model is used for determining a corresponding target value of the design parameter according to a target value of the chip performance of a target quantum chip.

According to a second aspect of the present disclosure, there is provided a method of designing a quantum chip, comprising:

obtaining a chip performance target value corresponding to a target quantum chip;

and inputting the chip performance target value into a quantum chip design model obtained by pre-training to obtain a first design parameter target value corresponding to the target quantum chip.

According to a third aspect of the present disclosure, there is provided a training apparatus for a quantum chip design model, comprising:

the device comprises a first acquisition module, a second acquisition module and a third acquisition module, wherein the first acquisition module is used for acquiring a design parameter sample value of a sample quantum chip and a corresponding chip performance sample value;

the establishing module is used for establishing an initial network model;

the prediction module is used for inputting the chip performance sample value into the initial network model to obtain a design parameter prediction value;

and the training module is used for training the initial network model according to the difference between the predicted value of the design parameter and the sample value of the design parameter so as to obtain a quantum chip design model, wherein the quantum chip design model is used for determining a corresponding target value of the design parameter according to a chip performance target value of a target quantum chip.

According to a fourth aspect of the present disclosure, there is provided a design apparatus of a quantum chip, including:

the second acquisition module is used for acquiring a chip performance target value corresponding to the target quantum chip;

and the first design parameter obtaining module is used for inputting the chip performance target value into a quantum chip design model obtained by pre-training to obtain a first design parameter target value corresponding to the target quantum chip.

According to a fifth aspect of the present disclosure, there is provided an electronic device comprising:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,

the memory stores instructions executable by the at least one processor to cause the at least one processor to perform a method according to any one of the embodiments of the present disclosure.

According to a sixth aspect of the present disclosure, there is provided a non-transitory computer readable storage medium having stored thereon computer instructions for causing a computer to perform a method in any of the embodiments of the present disclosure.

According to a seventh aspect of the present disclosure, there is provided a computer program product comprising computer programs/instructions, characterized in that the computer programs/instructions, when executed by a processor, implement the method in any of the embodiments of the present disclosure.

The disclosed technology can train a network model based on the design parameters of the quantum chip and the corresponding chip performance, and the trained model can be used for determining the corresponding design parameter target value according to the chip performance target value of the target quantum chip. Compared with the method that the design parameter target value is obtained by relying on artificial experience, the optimal design parameter can be found more quickly by utilizing the parameter target value obtained by the trained model, and the time and resource cost of quantum chip design are greatly reduced.

It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present disclosure, nor do they limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description.

Drawings

The drawings are included to provide a better understanding of the present solution and are not to be construed as limiting the present disclosure. Wherein:

FIG. 1 is a schematic diagram of an X-mon qubit configuration in accordance with an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a training method of a quantum chip design model according to an embodiment of the present disclosure;

fig. 3 is a schematic diagram of a design method of a quantum chip according to an embodiment of the present disclosure;

fig. 4 is a schematic diagram of a design method of a quantum chip according to another embodiment of the present disclosure;

FIG. 5 is a process flow diagram according to an embodiment of the present disclosure;

FIGS. 6(a) and 6(b) are schematic diagrams of relationships between chip performance sample values and design parameter sample values according to an embodiment of the present disclosure;

FIGS. 7(a) and 7(b) are schematic diagrams of a comparison of design values to actual values according to an embodiment of the present disclosure;

FIG. 8 is a schematic diagram of a training apparatus for a quantum chip design model according to an embodiment of the present disclosure;

fig. 9 is a schematic diagram of a design apparatus for a quantum chip according to an embodiment of the present disclosure;

fig. 10 is a schematic diagram of a design apparatus for a quantum chip according to another embodiment of the present disclosure;

fig. 11 is a block diagram of an electronic device for implementing a training method of a quantum chip design model of an embodiment of the present disclosure.

Detailed Description

Exemplary embodiments of the present disclosure are described below with reference to the accompanying drawings, in which various details of the embodiments of the disclosure are included to assist understanding, and which are to be considered as merely exemplary. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.

As the logic necessity of breaking through the classical physical limit of the chip size and the symbolic technology of the post-Moore times, the quantum computation and the related technology thereof have attracted great attention. Nowadays, quantum computing makes great progress from an application level, an algorithm level or a hardware level, and meanwhile, a plurality of problems and challenges are faced. At the quantum hardware level, taking the superconducting circuit widely accepted and used by the industry at present as an example, the charge qubit (charge qubit) configuration produced in 1999 has a coherence time of only 1 nanosecond, and the current configuration can reach 100 microseconds or even milliseconds. Furthermore, chips with superconducting qubits on the order of 50-100 have also grown in size. In a quantum chip, a qubit is a basic unit for implementing quantum computation, and superconducting qubits have various configurations, such as charge qubits, phase qubits, flux qubits, and so on. In recent years, quantum chips of Transmon, X-mon, etc. configuration have been proposed in order to improve the coherence time of superconducting qubits. Wherein, X-mon is an important quantum bit structure, the quantum chip based on X-mon is a chip type which attracts attention in recent years, and the superconducting circuit for realizing quantum dominance for the first time is realized based on X-mon.

X-mon is composed of two parts: a josephson junction and a capacitor connected in parallel therewith. Correspondingly, the key parameters determining the performance of X-mon are the values of the inductance of the josephson junction and the parallel capacitance, respectively. The parameter value of the parallel capacitor is determined by the specific geometric dimension of the capacitor, and meanwhile, the parameter value of the capacitor is influenced by a plurality of dimension parameters in the design process of the planar capacitor, so that the design of the size of the capacitor has larger degree of freedom, a unified specification is not formed, and the design is not beneficial to the standardized design of the X-mon capacitor.

When designing qubit X-mon in a superconducting chip, the industry often uses a qualitative method to find the required size and josephson junction inductance by relying on experimental experience, and simulates the geometric size, and further optimizes design parameters by combining experimental measurement results, and finally calculates the specific eigenfrequency and non-harmonic frequency corresponding to the design parameters. Then, after the actual flow sheet, the design parameters need to be verified by using a complex measurement and control system in the low-temperature environment of the dilution refrigerator, which causes relatively expensive resource and cost investment.

The quantification and the high efficiency of the design parameters of the quantum device break through the logic necessity of further improving the quantum bit scale, and are also the foundation for realizing the quantum large-scale integrated circuit. However, in the existing design scheme, the size of the inductance of the josephson junction mainly depends on the prior knowledge, and no clear analytical formula is used for determining the proper inductance value; the design of the planar capacitor is related to the configuration, only an approximate analytical formula of a single parameter on the influence of the capacitor is given at present, and only a limited effect can be played in the process of guiding the design of the capacitor structure. In summary, no mature and effective design method is currently formed in determining the sizes of the major parameters of the X-mon qubit, namely the josephson inductance and the parallel capacitance.

Fig. 1 shows the configuration of an X-mon qubit, and it can be seen that the structure of X-mon consists of a josephson junction and a shunt large capacitance in the shape of a cross (X, cross, etc.) in parallel. The grey shaded part of fig. 1 is metallic aluminum or other metal layer with superconducting property, which enters into superconducting state at low temperature, the white part is substrate, the substrate material is generally high-resistance silicon or sapphire, and the 101 part is josephson junction structure. As shown in fig. 1, the dimensions of the parallel capacitor include: capacitance length (X _ xsize, also called capacitance conductor length or parallel capacitance conductor length), capacitance height (X _ ysize), capacitance conductor width (X _ width), trench width (channel _ width), capacitance half height (X _ up). The sizes of the capacitors determine the parameter value of the X-mon capacitor, and therefore the performance of the chip.

The present disclosure provides a method for training a quantum chip design model, and specifically refers to fig. 2, which is a flowchart of a method for training a quantum chip design model provided in an embodiment of the present disclosure. The method may comprise the steps of:

step S201: obtaining a design parameter sample value of a sample quantum chip and a corresponding chip performance sample value;

in one example, the design parameter sample value is obtained first, and then the corresponding chip performance sample value is calculated according to the design parameter sample value. In general, the lower limit of the value range of the design parameter sample value is 0, and the upper limit is 2-3 times of the typical value of the same kind of chip.

In one example, the design parameter sample value includes an inductance value and a geometric parameter value, wherein the inductance value may be a josephson inductance value, and the value of the inductance value ranges from 0nH to 25 nH. The value range is determined by repeated experiments according to the empirical value of the existing quantum chip with successful flow sheet, the range covers the main range of the inductance value of the Josephson junction used for the quantum chip, and reasonable Josephson inductance value can be obtained by taking the value in the range.

In one example, the geometric parameter values in the design parameter sample values include a parallel capacitor conductor length value (corresponding to X _ xsize in fig. 1) and a trench width value (corresponding to X _ width in fig. 1), the parallel capacitor conductor length value ranges from 0mm to 2mm, the trench width value ranges from 0mm to 0.05mm, which are two key characteristic geometric parameters, and other characteristic geometric parameters can be given by the above parameters in combination with constraints. The value range is obtained by repeated tests according to the actual experience value of the existing tape-out, the range can cover the main value range of the chip, the data points are taken from the range to generate sample values, the geometric attributes of the actual chip can be better reflected, and the trained neural network model is more accurate.

In one example, N data points are respectively taken at equal intervals in three ranges according to given ranges of values of josephson inductance, parallel capacitor conductor length and trench width, and N × N training data samples are formed.

It should be emphasized that although X-mon has a plurality of geometric design parameters as shown in fig. 1, in the training, the training is performed based on at least three values of josephson inductance, capacitor conductor length and trench width, since these three values have the most direct influence on X-mon, and the remaining parameters can be calculated by combining constraints based on the three values. Therefore, in order to improve the efficiency of model training, only the three values are generally selected for training. More parameters can be selected for training if more accurate results are desired.

In one example, the chip performance sample values include the eigenfrequency values and anharmonic frequency values of the qubits. Eigenfrequency, which is sometimes also referred to as eigenfrequency, natural frequency, local oscillator frequency, etc., is a parameter that represents an intrinsic property of the object under study. The eigenfrequency and the non-harmonic frequency can represent the performance of the quantum chip and are specific indexes for testing quantum chip products. The intrinsic frequency value and the anharmonic frequency value are utilized to determine the performance index of the quantum chip more intuitively, in the actual design, a performance index is often given, and then the quantum chip is tested to see whether the performance index can be met. Therefore, in the method, the intrinsic frequency value and the anharmonic frequency value are selected as the input of the trained neural network, and the trained neural network can be better and directly applied to the design of the quantum chip.

In one example, on the basis of determining the design parameter sample value, the corresponding chip performance sample value is obtained by the following two methods:

the first step of calculating the value of the chip performance sample comprises the following steps:

obtaining a design parameter sample value; calculating a Hamilton quantity by using the design parameter sample value; and calculating the chip performance sample value by using the Hamilton quantity.

Specifically, in an ideal case, considering only a single qubit, regardless of the coupling between the qubit and the read resonator, the hamiltonian describing the superconducting qubit can be represented by equation (1).

Wherein E_CRepresents a capacitance energy, E_JRepresenting the josephson coupling energy, both values may be generated from the design parameter sample values. The nonlinear part of the Hamiltonian is contributed by cos function, and the phase of two sides of Josephson junction

Correlation, taking into account its lowest order nonlinear term, yields equation (2).

The above formula is represented by generating annihilation operators by using a quadratic quantization method, and Hamiltonian writing is performed under the spin-wave approximation:

wherein, ω is_q，α_qRepresenting the frequency and anharmonic frequency values of the qubit. In addition to this, the present invention is,

respectively representing the lifting operator of the qubit. For X-mon, the general design requirement E is to suppress noise_J＞＞E_CAt the level of the equivalent circuit ω_q，α_qCan be solved analytically. Eigenfrequency

Generally 3-6GHz, non-harmonic frequency alpha_q＝-E_CTypically 100-300 MHz. With equations (1) - (3) above, the frequency and anharmonic frequency values of the qubits, i.e., corresponding chip performance sample values, may be generated based on the design parameter sample values. Through the Hamilton quantity, the corresponding chip performance sample value can be quickly obtained, the calculation process is simple, and the operation is easy.

The second step of calculating the chip performance sample value comprises:

obtaining a design parameter sample value; and calculating the performance sample value of the chip by finite element analysis and an energy distribution and comparison method based on the design parameter sample value.

Specifically, for a given chip performance sample value, the eigenfrequency ω can be obtained by finite element analysis_qElectric and magnetic field energy distribution ε_elecAnd ε_magCurrent I through the Josephson junction_mj. And obtaining the off-harmonic frequency by an energy-partitioning-ratio (EPR) method, wherein the energy-partitioning ratio is calculated by the following method:

the off-harmonic frequency is calculated as follows:

by the second method, more accurate eigenfrequency and anharmonic frequency results can be obtained than by the first method, although the calculation steps are more complicated.

In summary, any of the above methods can be selected to calculate the chip performance sample value according to the accuracy requirement of the actual calculation force on the result.

It is added that if the calculated frequency is negative, or not at all (e.g. 10 larger) the order of magnitude is not correct³Double, or discontinuous results of chip performance sample values calculated with respect to the parameter sample values) are not used as the abnormal samples.

Step S202: establishing an initial network model;

in one example, the initial network model is built using a log-linear relationship between the design parameter sample values and the chip performance sample values. In particular, due to the eigenfrequency, the non-harmonic frequency and the design parameter sample value (in this example with the parallel capacitance conductor length L, and the Josephson inductance L)_iFor example) is monotonic. Because the dependence relationship of the eigenfrequency and the non-harmonic frequency is a product relationship, the logarithm of the product relationship is approximately linear, and a training model is constructed:

matrix form of equation (6):

in practice, the scimit-learn of Python language is used for machine learning applications. The data call train _ test _ split is split. Obtaining a slope parameter w by utilizing a Linear regression (). fit method,

matrix sum sectionAnd b. Therefore, the relation between the eigen frequency, the non-harmonic frequency and the design parameter sample value can be quickly obtained by using the formula (7), and the basic framework of the neural network is quickly initialized.

It should be noted that the groove width value, the eigenfrequency and the non-harmonic frequency also satisfy the above logarithmic linear relationship, and a corresponding formula of the groove width may be established by referring to the above formula, which is not described herein again.

Step S203: inputting the chip performance sample value into the initial network model to obtain a design parameter predicted value;

step S204: and training the initial network model according to the difference between the predicted value of the design parameter and the sample value of the design parameter to obtain a quantum chip design model, wherein the quantum chip design model is used for determining a corresponding target value of the design parameter according to a target value of the chip performance of a target quantum chip.

In summary, in the above scheme, the design parameter sample value corresponding to the sample quantum chip is taken from the preset range, then the corresponding chip performance sample value is calculated, then the initial network model is established, then the neural network model is trained by using the design parameter sample value and the chip performance sample value, so as to obtain the quantum chip design model, the quantum chip design model can input the chip performance target value of the target quantum chip, and output the corresponding design parameter target value, and the scheme has the following beneficial effects:

1. in the traditional method, design parameters can be verified only after actual flow sheets in the low-temperature environment of the dilution refrigerator by using a complex measurement and control system, and relatively expensive resources and cost investment are required. In contrast, the present disclosure uses neural networks to obtain satisfactory design parameters, greatly reducing time and resource costs.

2. In the process of designing a superconducting quantum chip, design parameters are very various, for example, the geometric size of a capacitor is simultaneously determined by a plurality of parameters, and meanwhile, the parameters influence the coherence time of a qubit, so that it is difficult to determine the constraint conditions of the parameters by an analytic method to realize high coherence time. The neural network model trained by the method can measure the influence degree of each design parameter on the target characteristic parameter, and provides an important reference basis for further optimizing the design parameters.

3. The traditional method obtains the approximate range of the design parameters by experience, but in fact, all performance values do not have a unique set of design parameters, so that the data of a large number of sample quantum chips are obtained for training, the finally trained neural network can obtain the spatial range of the design parameters according to the input chip performance target value, and the existence of the design parameters is prior. Further, aiming at the problem that a plurality of sets of design parameter solutions satisfying performance values exist, only one solution can be found in the traditional method, all design parameters in a solution space can be obtained by using a trained neural network model in the method, more consideration factors can be further introduced, and the optimal solution can be selected.

The present disclosure provides a design method of a quantum chip, and specifically refers to fig. 3, which is a flowchart of the design method of the quantum chip provided in the embodiment of the present disclosure. The method may comprise the steps of:

step S301: obtaining a chip performance target value corresponding to a target quantum chip;

in one example, the chip performance target values include eigenfrequency values and anharmonic frequency values.

Step S302: and inputting the chip performance target value into a quantum chip design model obtained by pre-training to obtain a first design parameter target value corresponding to the target quantum chip.

In one example, the first design parameter target values include josephson inductance values, parallel capacitor conductor length values, and trench width values. The target value of the first design parameter is directly obtained from the trained neural network and is consistent with the sample when the model is trained, that is, if the model is trained by selecting the josephson inductance value, the capacitance conductor length value and the groove width value, the direct output of the trained neural network model is also the three values, and if more parameter values are selected when the model is trained, the design parameter corresponding to the output of the trained model will also change.

In one example, the first design parameter target value may be a set of values, i.e., a range that gives a spatial solution. In the method, all design parameters in a solution space can be obtained by using a trained neural network model, and more consideration factors can be further introduced to select the optimal solution.

After the first design parameter target value is obtained, a design drawing of the quantum chip can be generated according to the first design parameter target value. The quantum chip design is carried out by adopting the neural network method, and the method has the following beneficial effects:

first, it is simple, intuitive and efficient. Based on the method, the trained neural network can be used for very efficiently providing the design parameters of the quantum device X-mon in the superconducting quantum circuit, and compared with the design parameter sample values obtained by 'trying' through the experience of a designer, the method can greatly reduce the time and resource cost and has very good application value.

And secondly, the method has universality and inspiration. The method has guiding significance for parameter design of other superconducting circuits. The method provided by the scheme can be popularized to various superconducting devices, namely the method can be popularized to quantum chips of other basic architectures, such as a Transmon quantum chip, by taking an X-mon quantum chip as an example, and a neural network model can be trained by using the relation between design parameters and performance, and then the model can obtain expected design parameters according to target performance parameters.

Thirdly, the expandability is strong. In the scheme of the disclosure, the design flow of the qubit X-mon is considered emphatically. Of course, other similar devices are considered, and even the initialization problem of the multi-quantum bit circuit and the automatic initialization of the coupling capacitance between bits are solved based on the solving idea of the Hamilton quantity, finite element analysis and energy distribution ratio. In addition, the method can also be expanded in application scenes. The idea provided by the scheme of the invention can also support other more complex superconducting circuit automatic designs.

Finally, the accuracy is higher. Compared with an empirical method, the scheme of the disclosure can provide a design scheme of the quantum device, and can also obtain the influence degree of each design parameter on the performance of the quantum device by comparing a plurality of groups of design parameters.

The present disclosure further provides a design method of a quantum chip, and specifically please refer to fig. 4, which is a flowchart of the design method of the quantum chip provided in the embodiment of the present disclosure. The method may comprise the steps of:

step S401: obtaining a chip performance target value corresponding to a target quantum chip;

step S402: inputting the chip performance target value into a quantum chip design model obtained by pre-training to obtain a first design parameter target value corresponding to the target quantum chip;

step S403: and determining a second design parameter target value according to the length value of the parallel capacitor conductor and the width value of the groove.

The steps S401-S402 are substantially the same as the steps S301-S302, and are not described herein again. After the first design parameter target value is obtained, the remaining dimension parameters may be determined according to the length value of the parallel capacitor conductor and the width value of the trench in the first design parameter target value, including:

capacitance height (X _ ysize): for X _ ysize, the effect is the same as that of X _ xsize, and the same value as that of X _ xsize can be taken to obtain the same result;

capacitance conductor width (X _ width): for X _ width, the influence on the eigen frequency and the off-harmonic frequency is small, but it is influenced by other factors, mainly the geometrical size limitation of the josephson junction, and the small size introduces complex boundary conditions, which causes the electromagnetic field distribution at the boundary to be very concentrated and the dissipation of energy to be generated, and is influenced by these factors, and the value can generally take the range of about 20%, namely 0.20-0.30. According to design experience, the two X _ width/X _ channel _ width are kept equal or changed in proportion, and the two are equivalent, so that only one parameter is trained.

Capacitance half height (X _ up): for X _ up, the result is of little impact, its size is determined by the spatial layout of the device, and may take the size 0-X _ size.

In summary, the size of a reasonable and comprehensive parallel capacitor can be quickly obtained through the above mode, and a target quantum chip can be obtained based on the size of the parallel capacitor and the Josephson inductance value.

Application example:

as shown in fig. 5, a processing flow of an embodiment of the present disclosure includes six steps, which specifically include: the method comprises the steps of manufacturing a training set, constructing a training model, processing data, constructing a loss function, solving gradient descent and verifying an output result, wherein design parameters are equivalent to design parameter sample values, and simulation characteristic parameters are corresponding chip performance sample values.

The most important steps include "making a training set", "constructing a training model", and "verifying an output result", which will be explained in detail below:

firstly, generating a training set

Regarding the construction of the training set, three key characteristic parameters are selected to be combined to construct the training set, which respectively are as follows: josephson inductor L_jX _ xsize of the parallel capacitor, and trench width channel _ width of the capacitor.

Although 5 size parameters are listed in fig. 1, only 3 of them were subjected to data set generation at the time of training. The reason for this is because of the size parameters, X _ ysize/X _ xsize (here, we mean parallel, non-dividing) are equivalent because of symmetry, so only X _ xsize is traversed to obtain sample values; the X _ up parameter determines the relative position of two arms of the cross-shaped capacitor, does not influence the change of the capacitor and is only used as an adjusting parameter of the structural shape. The two X _ width/channel _ width are usually kept equal or proportional according to design experience, and are equivalent, so only one of the parameters is trained, and channel _ width is selected here.

The training set is constructed based on existing design experience (such as the design parameters in the IBM Qiskit metal) as a reference, taking two to three times the typical value. Wherein the Josephson inductor L_jThe training range can be set to [0nH,25nH]The X _ xsize training range of the parallel capacitor can be set to 0mm and 2mm]Channel width training rangeCan be set to be [0mm,0.05mm]The above range may be changed according to specific design requirements, and is not fixed. In the three parameter ranges, 50 data points are respectively taken at equal intervals to form 50 × 50 training data samples, and then the corresponding eigenfrequency and non-harmonic frequency are obtained according to the electromagnetic simulation method introduced in the above description in combination with the EPR method or by calculating the hamilton and other methods.

It can be known that X _ ysize/X _ xsize is a key factor affecting the capacitance design because the symmetry is equivalent, so the training ranges of the two are the same, and the dimension reduction processing can be performed assuming that the two are the same.

Furthermore, both X _ width/channel _ width remain equal or proportional, and are also equivalent, but these two structural parameters affect not only the value of the capacitance parameter, but also other characteristic parameters of X-mon, such as the coherence time, so that these two parameters can be varied only slightly.

Based on the method, the design parameter sample value and the chip performance sample value corresponding to the sample quantum chip can be obtained as shown in the following table:

TABLE 1 design parameter sample values and chip Performance sample values

The eigen frequency and the off-harmonic frequency in the table are calculated based on the design parameter sample value, and the specific calculation step refers to the description in step S201.

After the sample set is obtained, it can be divided into two parts, one part is used for training and called training set, and the other part is used for training and testing and called testing set.

Secondly, constructing a training model and starting training by utilizing a training set

In the above steps, obtaining the design parameter sample value and the chip performance sample value has been completed as the training set for machine learning. The training set is initially analyzed and selected to more intuitively understand the relationship between the twoTwo design parameters (X-mon parallel large capacitor length X _ xsize is denoted as L in the figure, and Josephson inductance L_j) For example, the relationship between the chip performance sample value and the design parameter sample value is plotted using the continuously sampled data points, as shown in FIG. 6. Wherein, fig. 6(a) shows the dependence of the eigenfrequency (in GHz) on the length L (in mm) of the parallel capacitance conductor and the josephson inductance L _ j (in nH); fig. 6(b) shows the dependence of the detuning frequency (in MHz) on the parallel capacitor conductor length L (in mm) and the josephson inductance L _ j (in nH).

It can be seen that the eigenfrequency, the off-harmonic frequency and the length L of the parallel capacitive conductor, and the Josephson inductance L_jIs monotonic. And drawing a conclusion that the dependence relationship of the eigenfrequency and the non-harmonic frequency is a product relationship, wherein the logarithm of the product relationship is approximately linear, and constructing an initial network model based on the conclusion. The form of the network model is shown above in equations (7), (8).

After an initial network model is constructed, machine learning application is carried out by using scimit-lean of Python language. The data call train _ test _ split is split. Obtaining a slope parameter w by utilizing a Linear regression (). fit method,

matrix and intercept b.

Starting training based on an initial network model, and inputting chip performance sample values in a training set into the initial network model to obtain a design parameter predicted value; training the initial network model according to the difference between the predicted value and the sample value of the design parameter to obtain the final quantum chip design model

Thirdly, verifying and evaluating the trained model by utilizing a verification set

In order to verify whether the model is trained well, the score method is utilized to test the performance of the machine learning result, the closer the value is to 1, the better the training result is, and generally the value is more than 0.9, the model training can be considered to be finished; for the training set, score was 0.952926 and score was 0.957908 for the test set. The demonstration model is trained and the feasibility of the disclosed solution is fully verified from another perspective.

To demonstrate the results more directly, we demonstrate fixing several design parameters:

for design parameter sample values X _ ysize is 0.25mm, X _ width is 0.025mm, X _ channel _ width is 0.0025mm, and X _ up is 0.085mm, the corresponding performance sample values are calculated: the eigenfrequency ω is 6 GHz.

The capacitance conductor lengths and josephson inductances for different off-harmonic values are shown in fig. 7, where the scatter point is the actual value and the straight line is the result obtained with the scheme of the present disclosure. As can be seen from the figure, the values modeled by the present disclosure are not much different from the actual values, i.e., the model trained by the present disclosure can be well used to design the superconducting quantum bit X-mon.

In an embodiment, a chip performance sample value ω is 4.5GHz and α is 250MHz, and the chip performance sample value ω and α are input to a trained neural network to obtain a corresponding design parameter sample value, as shown in the following table:

after the other design parameters are supplemented, all design parameter sample values are obtained as shown in the following table:

the procedure to supplement the remaining involved parameters is as follows: under the condition of obtaining a trained neural network, inputting a characteristic parameter to obtain corresponding X _ xsize and Josephson inductance L_jThen, for X _ ysize, the same effect as X _ xsize can be obtained, and the same result can be obtained by taking the same value as X _ xsize. The dimension parameter X _ width, which has little effect on the eigen frequency and the anharmonic frequency, is affected by other factors, mainly the geometrical limitation of the josephson junction, and the small dimension introduces complicated boundary conditions, which leads to very concentrated electromagnetic field distribution at the boundary and dissipation of energy, and is affected by these factors,the value can be in the range of 20%, namely 0.020-0.030. For X _ up, the result is of little impact, its size is determined by the spatial layout of the device, and may take the size 0-X _ size.

The verification result is obtained by adopting a finite element simulation method, namely the simulation method closest to the actual flow sheet mentioned in the foregoing, and the eigenfrequency is obtained: ω ═ 4.665GHz, with a relative error of 3.67%. The non-harmonic frequency is obtained by adopting the energy distribution method: the relative error is 7.03 percent when alpha is 267.56MHz, and the error is within the allowable range from the initially set chip performance target value, so that the feasibility of designing the quantum chip through a neural network model in the disclosure is fully verified.

As shown in fig. 8, an embodiment of the present disclosure provides a training apparatus 800 for a quantum chip design model, the apparatus including:

a first obtaining module 801, configured to obtain a design parameter sample value of a sample quantum chip and a corresponding chip performance sample value;

an establishing module 802 for establishing an initial network model;

a prediction module 803, configured to input the chip performance sample value into the initial network model to obtain a design parameter prediction value;

a training module 804, configured to train the initial network model according to a difference between the predicted value of the design parameter and the sample value of the design parameter, so as to obtain a quantum chip design model, where the quantum chip design model is configured to determine a corresponding target value of the design parameter according to a chip performance target value of a target quantum chip.

The first obtaining module 801 is configured to:

obtaining a design parameter sample value;

calculating a Hamilton quantity by using the design parameter sample value;

and calculating the chip performance sample value by using the Hamilton quantity.

The first obtaining module 801 is configured to:

obtaining a design parameter sample value;

and calculating the performance sample value of the chip by finite element analysis and an energy distribution and comparison method based on the design parameter sample value.

Wherein the establishing module 802 is configured to:

and establishing the initial network model by utilizing the logarithmic linear relation between the design parameter sample value and the chip performance sample value.

The design parameter sample value comprises a Josephson inductance value, and the value range of the Josephson inductance value is 0 nH-25 nH.

The design parameter sample value comprises a length value of the parallel capacitor conductor and a groove width value, the length value of the parallel capacitor conductor ranges from 0mm to 2mm, and the groove width value ranges from 0mm to 0.05 mm.

Wherein the chip performance sample values include an eigenfrequency value and an anharmonic frequency value.

As shown in fig. 9, an embodiment of the present disclosure provides a quantum chip designing apparatus 900, including:

a second obtaining module 901, configured to obtain a chip performance target value corresponding to the target quantum chip;

a first design parameter obtaining module 902, configured to input the chip performance target value into a quantum chip design model obtained through pre-training, so as to obtain a first design parameter target value corresponding to the target quantum chip.

Wherein, the chip performance target value comprises an intrinsic frequency value and an anharmonic frequency value; the first design parameter target values include a josephson inductance value, a parallel capacitor conductor length value, and a trench width value.

As shown in fig. 10, another design apparatus 1000 of a quantum chip is provided in the embodiments of the present disclosure, the apparatus including:

a second obtaining module 1001, configured to obtain a chip performance target value corresponding to a target quantum chip;

a first design parameter obtaining module 1002, configured to input the chip performance target value into a quantum chip design model obtained through pre-training, so as to obtain a first design parameter target value corresponding to the target quantum chip;

a second design parameter obtaining module 1003, configured to determine a second design parameter target value according to the length value of the parallel capacitor conductor and the width value of the trench.

In the technical scheme of the disclosure, the acquisition, storage, application and the like of the personal information of the related user all accord with the regulations of related laws and regulations, and do not violate the good customs of the public order.

The present disclosure also provides an electronic device, a readable storage medium, and a computer program product according to embodiments of the present disclosure.

The functions of each module in each apparatus in the embodiments of the present disclosure may refer to the corresponding description in the above method, and are not described herein again.

FIG. 11 shows a schematic block diagram of an example electronic device 1100 that may be used to implement embodiments of the present disclosure. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be examples only, and are not meant to limit implementations of the disclosure described and/or claimed herein.

As shown in fig. 11, the device 1100 comprises a computing unit 1101, which may perform various appropriate actions and processes according to a computer program stored in a Read Only Memory (ROM)1102 or a computer program loaded from a storage unit 1108 into a Random Access Memory (RAM) 1103. In the RAM 1103, various programs and data necessary for the operation of the device 1100 may also be stored. The calculation unit 1101, the ROM 1102, and the RAM 1103 are connected to each other by a bus 1104. An input/output (I/O) interface 1105 is also connected to bus 1104.

A number of components in device 1100 connect to I/O interface 1105, including: an input unit 1106 such as a keyboard, a mouse, and the like; an output unit 1107 such as various types of displays, speakers, and the like; a storage unit 1108 such as a magnetic disk, optical disk, or the like; and a communication unit 1109 such as a network card, a modem, a wireless communication transceiver, and the like. The communication unit 1109 allows the device 1100 to exchange information/data with other devices through a computer network such as the internet and/or various telecommunication networks.

The computing unit 1101 can be a variety of general purpose and/or special purpose processing components having processing and computing capabilities. Some examples of the computing unit 1101 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various dedicated Artificial Intelligence (AI) computing chips, various computing units running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, and the like. The computational unit 1101 performs the various methods and processes described above, such as methods to train a quantum chip design model. For example, in some embodiments, the method training the quantum chip design model may be implemented as a computer software program tangibly embodied in a machine-readable medium, such as storage unit 1108. In some embodiments, part or all of the computer program may be loaded and/or installed onto device 1100 via ROM 1102 and/or communication unit 1109. When the computer program is loaded into RAM 1103 and executed by computing unit 1101, one or more steps of training a quantum chip design model by the method described above may be performed. Alternatively, in other embodiments, the computing unit 1101 may be configured by any other suitable means (e.g., by means of firmware) to perform a method training the quantum chip design model.

Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuitry, Field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), Application Specific Standard Products (ASSPs), system on a chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs that are executable and/or interpretable on a programmable system including at least one programmable processor, which may be special or general purpose, receiving data and instructions from, and transmitting data and instructions to, a storage system, at least one input device, and at least one output device.

Program code for implementing the methods of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the program codes, when executed by the processor or controller, cause the functions/operations specified in the flowchart and/or block diagram to be performed. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic, speech, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a back-end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), Wide Area Networks (WANs), and the Internet.

The computer system may include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server may be a cloud server, a server of a distributed system, or a server with a combined blockchain.

It should be understood that various forms of the flows shown above may be used, with steps reordered, added, or deleted. For example, the steps described in the present disclosure may be executed in parallel, sequentially, or in different orders, as long as the desired results of the technical solutions disclosed in the present disclosure can be achieved, and the present disclosure is not limited herein.

The above detailed description should not be construed as limiting the scope of the disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made in accordance with design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A training method of a quantum chip design model comprises the following steps:

establishing an initial network model;

and training the initial network model according to the difference between the predicted value and the sample value of the design parameter to obtain a quantum chip design model, wherein the quantum chip design model is used for determining a corresponding target value of the design parameter according to a target value of the chip performance of a target quantum chip.

2. The method of claim 1, wherein obtaining parameter sample values and corresponding chip performance sample values for a sample quantum chip design comprises:

acquiring the design parameter sample value;

calculating a Hamilton quantity by using the design parameter sample value;

3. The method of claim 1, wherein obtaining parameter sample values and corresponding chip performance sample values for a sample quantum chip design comprises:

acquiring the design parameter sample value;

and calculating the chip performance sample value by finite element analysis and an energy distribution ratio method based on the design parameter sample value.

4. The method of claim 1, wherein building an initial network model comprises:

5. The method of claim 1, wherein the design parameter sample value comprises a josephson inductance value ranging from 0nH to 25 nH.

6. The method of claim 1, wherein the design parameter sample value comprises a parallel capacitance conductor length value and a trench width value, the parallel capacitance conductor length value ranging from 0mm to 2mm, the trench width value ranging from 0mm to 0.05 mm.

7. The method of any of claims 1-6, wherein the chip performance sample values include eigen frequency values and anharmonic frequency values.

8. A design method of a quantum chip comprises the following steps:

9. The method of claim 8, wherein the chip performance target values include eigenfrequency values and anharmonic frequency values; the first design parameter target values include a josephson inductance value, a parallel capacitance conductor length value, and a trench width value.

10. The method of claim 9, further comprising:

and determining a second design parameter target value according to the length value of the parallel capacitor conductor and the width value of the groove.

11. A training device for a quantum chip design model comprises:

the establishing module is used for establishing an initial network model;

and the training module is used for training the initial network model according to the difference between the predicted value of the design parameter and the sample value of the design parameter to obtain a quantum chip design model, wherein the quantum chip design model is used for determining a corresponding target value of the design parameter according to a chip performance target value of a target quantum chip.

12. The apparatus of claim 11, wherein the first obtaining means is configured to:

acquiring the design parameter sample value;

calculating a Hamilton quantity by using the design parameter sample value;

13. The apparatus of claim 11, wherein the first obtaining means is configured to:

acquiring the design parameter sample value;

14. The apparatus of claim 11, wherein the establishing means is configured to:

15. The apparatus of claim 11, wherein the design parameter sample value comprises a josephson inductance value ranging from 0nH to 25 nH.

16. The apparatus of claim 11, wherein the design parameter sample value comprises a parallel capacitance conductor length value and a trench width value, the parallel capacitance conductor length value ranging from 0mm to 2mm, the trench width value ranging from 0mm to 0.05 mm.

17. The apparatus of any of claims 11-16, wherein the chip performance sample values include eigen frequency values and anharmonic frequency values.

18. A design device of quantum chip includes:

19. The apparatus of claim 18, wherein the chip performance target values comprise eigenfrequency values and anharmonic frequency values; the first design parameter target values include a josephson inductance value, a parallel capacitance conductor length value, and a trench width value.

20. The apparatus of claim 19, further comprising:

and the second design parameter obtaining module is used for determining a second design parameter target value according to the length value of the parallel capacitor conductor and the width value of the groove.

21. An electronic device, comprising:

at least one processor; and

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-10.

22. A non-transitory computer readable storage medium having stored thereon computer instructions for causing the computer to perform the method of any one of claims 1-10.

23. A computer program product comprising a computer program which, when executed by a processor, implements the method according to any one of claims 1-10.