CN113097207B - Redundant local loop insertion method based on process window - Google Patents

Redundant local loop insertion method based on process window Download PDF

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CN113097207B
CN113097207B CN202110372285.1A CN202110372285A CN113097207B CN 113097207 B CN113097207 B CN 113097207B CN 202110372285 A CN202110372285 A CN 202110372285A CN 113097207 B CN113097207 B CN 113097207B
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CN113097207A (en
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屈通
韦亚一
粟雅娟
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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Abstract

The invention relates to a redundant local loop insertion method based on a process window, which solves the problems that the manufacturability requirement is difficult to meet due to lack of consideration of the process window in the prior art. The method comprises the following steps: inputting an original layout, and extracting to obtain all through hole information and all available RLL insertion schemes; calculating a process window and a cost corresponding to each RLL insertion scheme; calculating an objective function by utilizing each cost function and each process window, and obtaining an optimal RLL insertion scheme according to the objective function; and performing redundant local loop insertion based on the optimal RLL insertion scheme, outputting a final layout, and realizing the manufacturability of the layout based on the process window.

Description

Redundant local loop insertion method based on process window
Technical Field
The invention relates to the technical field of integrated circuit manufacturing, in particular to a redundant local loop insertion method based on a process window.
Background
Photolithography is one of the most important and critical process steps in the manufacture of integrated circuits. With the rapid development of semiconductor technology, patterns are more and more dense, feature sizes are smaller and smaller, and the requirements on the photolithography process are higher and higher. One important performance metric in photolithography is the Process Window (PW). The process window refers to the range of exposure and defocus that ensures that the mask pattern can be properly copied onto the silicon wafer.
In accordance with moore's law, the critical dimensions of integrated circuit chips are becoming smaller and higher, and these challenges have not been able to be met by the manufacturers' own abilities alone. Designers and manufacturers must combine to solve these problems, and the designers must consider the manufacturing problem of design in the design stage, and design a layout convenient for manufacturing according to the specific requirements of the process. A Redundant Local-Loop (RLL) is an efficient Redundant via insertion method for a one-dimensional pattern structure below 10nm, however, the current RLL insertion method only considers the design rule, lacks consideration of the process window, and is difficult to meet the manufacturability requirement.
At present, a Source Mask Optimization (SMO) is a computational lithography technology for a lithography process window of a very small-sized pattern, and a light Source and a Mask in the lithography process window are cooperatively optimized to improve the lithography process window in a very small-sized node and enhance optical performance. The idea of SMO is divided into two categories, one of which is to alternate the global optimization light source and the optimization mask until the result meets the requirement, i.e. alternate optimization algorithm. The other method is that the local mask and the light source are cooperatively optimized, and the coupling effect between the two is fully considered to obtain the optimized light source, namely a cooperative optimization algorithm.
Although the SMO simulation approach may result in more accurate source and mask layouts, it is time consuming. The simulation operation time is positively correlated with the size of the layout, and taking the 1mm by 1mm layout as an example, the simulation time is about 50 minutes. At the early stages of design (e.g., routing and redundant via insertion), we only need some of the key parameters to measure manufacturability of the design, and do not need accurate light source and mask layout. With the development of integrated circuit technology, the layout scale of advanced nodes becomes increasingly large, and when designing a layout, the time cost required for judging the manufacturability of different design methods by using an SMO simulation method is unacceptable.
Therefore, a layout process window simulation method based on a machine learning algorithm is lacked in the prior art, and a redundant local loop insertion algorithm which considers the process window and satisfies manufacturability is designed by means of the model.
Disclosure of Invention
In view of the foregoing analysis, embodiments of the present invention are directed to a process window-based redundant local loop insertion method for solving the problem that the existing design lacks consideration of the process window and is difficult to satisfy the manufacturability requirement.
In one aspect, an embodiment of the present invention provides a method for inserting a redundant local loop based on a process window, including:
inputting an original layout, and extracting to obtain all through hole information and all available RLL insertion schemes;
calculating a process window and a cost corresponding to each RLL insertion scheme;
calculating an objective function by utilizing each cost function and each process window, and obtaining an optimal RLL insertion scheme according to the objective function;
and performing redundant local loop insertion based on the optimal RLL insertion scheme, and outputting a final layout.
Further, the objective function is expressed as:
Figure BDA0003009752270000031
wherein x isiInsert the corresponding binary variable, x, for the ith RLLiE {0,1 }; delta, epsilon and zeta are weight parameters; n isiThe number of vias contained for the ith RLL insertion scheme; c. CiInserting a cost corresponding to the scheme for the ith RLL; p is a radical of formulaiAnd inserting the corresponding process window for the ith RLL.
Further, the calculating a process window corresponding to each RLL insertion scheme includes:
determining key region layout slices and all layout slices corresponding to each RLL insertion scheme according to the original layout, and obtaining a process window actual value corresponding to each key region layout slice through simulation;
slicing and pixelating all the critical area layouts, and converting the critical area layouts into a two-dimensional matrix form;
performing data enhancement on the critical area layout data in the two-dimensional matrix form to obtain enhanced two-dimensional matrix data;
performing CNN model training by using the enhanced two-dimensional matrix data and the process window actual value to obtain a trained process window prediction model;
converting all layout slices corresponding to each RLL insertion scheme of the original layout into corresponding two-dimensional matrix data, and sequentially inputting the two-dimensional matrix data into the trained process window prediction model to obtain process windows of all the layouts corresponding to the RLL insertion schemes;
and determining the process windows corresponding to the RLL insertion scheme by the process windows of all the layouts corresponding to the RLL insertion scheme.
Further, the key region layout slice pixelation includes:
dividing the layout slice of the key area into rectangular grids;
and obtaining the state that the grid corresponding to the geometric shape is full or empty based on the geometric shape of the graph in the layout slice of the key area, and obtaining the two-dimensional matrix form corresponding to the graph in the layout slice of the key area based on the state of each grid.
Further, the data enhancement comprises that the two-dimensional matrix corresponding to the graph in the key region layout slice is respectively turned over according to an X axis, turned over according to a Y axis, rotated by 90 degrees, rotated by 180 degrees and rotated by 270 degrees to obtain enhanced two-dimensional matrix data.
Further, pixelating all layout slices corresponding to each RLL insertion scheme of the original layout to obtain two-dimensional matrix data of all the layout slices corresponding to the RLL insertion scheme, sequentially inputting the two-dimensional matrix data into the trained process window prediction model to obtain process windows of all the layouts corresponding to the RLL insertion scheme, and determining a process window P (P) corresponding to each RLL insertion scheme by the process windows of all the layouts corresponding to the RLL insertion scheme1,p2,…pi… } in which piAnd inserting the process window corresponding to the ith RLL inserting scheme.
Further, the weight parameter ζ of the process window corresponding to each RLL insertion scheme in the objective function is expressed as:
Figure BDA0003009752270000041
wherein d and m are control parameters, piAnd inserting the corresponding process window for the ith RLL.
Further, it is characterized by also comprising: extracting all through hole information, all RLL insertion schemes and the number J of metal layer layers in the original layout according to the original layout to obtain the number N of through holes contained in each RLL insertion scheme, wherein the number N of through holes is N1,n2…ni… } and by RLL insertion schemeThe number v of redundant through holes introduced on the k layer through hole layeri,k，niThe number of vias contained for the ith RLL insertion scheme.
Further, the cost corresponding to each RLL insertion scheme is calculated by using the following cost function:
Figure BDA0003009752270000042
wherein, the number of the metal layer layers is J, the number of the through hole layer layers is J-1, ciCost of the ith RLL insertion scheme, αjCost weight parameter, m, for the jth metal layeri,jTrace length, beta, introduced on jth metal layer for ith RLL insertion schemekCost weight parameter, v, for the k-th via layeri,kThe number of redundant vias introduced on the kth via layer for the ith RLL insertion scheme.
In another aspect, an embodiment of the present invention provides a semiconductor physical design method for inserting a redundant local loop based on a process window, including:
inputting an initial circuit layout, and partitioning the initial circuit layout to obtain a plurality of sub-circuits;
planning the positions and the geometric shapes of chips in the plurality of sub-circuits, and carrying out position layout and wiring treatment on the planned plurality of sub-circuits to obtain a first layout;
performing redundant local loop insertion in the first layout according to the optimal redundant local loop insertion scheme to obtain an output layout;
and preparing the semiconductor hardware circuit by using the output layout.
Compared with the prior art, the invention can realize at least one of the following beneficial effects:
1. inputting an original layout, extracting and obtaining all through hole information and all available RLL insertion schemes, and ensuring the comprehensiveness of the RLL insertion schemes and the reasonability of each RLL;
2. a layout pixelation method is used in the calculation process of the process window, so that a small amount of storage space can be used for recording the information of the layout, and the operation amount of data can be effectively reduced without losing the characteristics of the layout after a reasonable sampling window is selected according to the actual situation; then, machine learning is adopted to replace an EDA tool for calculation, so that the calculation is easy, the speed is high, and a good experiment effect is achieved;
3. the CNN network extracts the characteristics of the layout, the training speed is high, the generalization capability is strong, and the model can be suitable for different application scenes after being trained by corresponding data sets;
4. calculating a process window and a cost corresponding to each RLL insertion scheme, and then calculating an objective function by using each cost function and each process window to ensure that the performance of each RLL insertion scheme is comprehensively considered;
5. the insertion rate, the insertion cost and the process window are comprehensively considered, the weights of the insertion rate, the insertion cost and the process window can be adjusted according to needs, the process window is improved under the condition of the same insertion rate, redundant local loop insertion is carried out based on the optimal RLL insertion scheme, and the manufacturability of the design is effectively improved.
In the invention, the technical schemes can be combined with each other to realize more preferable combination schemes. Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and drawings.
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The drawings are only for purposes of illustrating particular embodiments and are not to be construed as limiting the invention, wherein like reference numerals are used to designate like parts throughout.
FIG. 1 is a flow chart of a process window based redundant local loop insertion method according to one embodiment of the present application;
FIG. 2 is a schematic diagram of various RLL insertion schemes shown in one embodiment of the present application;
FIG. 3 is a flowchart illustrating the process window acquisition sub-step according to one embodiment of the present application;
FIG. 4 is a diagram illustrating pixelation of a layout slice according to an embodiment of the present application;
fig. 5 is a flowchart of a semiconductor physical design method of a process window based redundant local loop insertion method according to another embodiment of the present application.
Reference numerals
1, a through hole; 2, redundant through holes; 3, a first metal layer; 4, a second metal layer; 5, a second redundant metal layer; 6, a first redundant metal layer; 7, a first RLL insertion scheme; 8, a second RLL insertion scheme; and 9, gridding.
Detailed Description
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate preferred embodiments of the invention and together with the description, serve to explain the principles of the invention and not to limit the scope of the invention.
One embodiment of the present invention discloses a method for inserting a redundant local loop based on a process window, as shown in fig. 1, including:
s10, inputting the original layout, and extracting and obtaining all through hole information and all available RLL insertion schemes;
specifically, an original layout is input, and according to the original layout, all through hole information, all RLL insertion schemes and the number of metal layer layers J in the original layout are extracted to obtain the number N of through holes included in all RLL insertion schemes ═ N1,n2…ni… } and the number of redundant vias v introduced on the k-th via layer by the RLL insertion schemei,k，niThe number of vias contained for the ith RLL insertion scheme.
Specifically, a via layer is sandwiched between two metal layers, so after the number J of metal layers is determined, the number J-1 of via layers can also be determined, and all possible RLL insertion schemes for each via are enumerated according to the information of all vias. Multiple RLL insertion schemes are possible for one via, as shown in FIG. 2, in which FIG. 2 comprises a first metal layer 3, a second metal layer 4, a first redundant metal layer 6, a second redundant metal layer 5, and 2 vias 1; the RLL insertion scheme includes: a first RLL insertion scheme 7 and a second RLL insertion scheme 8, wherein the first RLL insertion scheme 7 includes redundant metal traces with lengths of 3 redundant vias 2 and 5 grids (the length of the redundant metal trace is calculated by the number of redundant metal layer grids in the RLL insertion scheme), and the second RLL insertion scheme 8 includes redundant metal traces with lengths of 2 redundant vias 2 and 3 grids; when the RLL insertion scheme is generated, the comprehensiveness is guaranteed, each RLL scheme is not omitted, the rationality of each RLL is guaranteed, and the running time of the algorithm is reduced. Therefore, when enumerating all RLL insertion schemes, RLL insertion schemes that do not meet the design constraints and duplications are removed.
Specifically, the design constraints in the present application may be:
1) and (3) through hole pattern constraint: at nodes of 10nm and below, the center distance of the lower-layer through hole layer is positioned in the sub-photoetching field, and the self-aligned through hole pattern is the preferred through hole pattern in the sub-photoetching field;
2) and (3) through hole density constraint: as the size of the through hole decreases, the requirements of the through hole etching process and the chemical mechanical polishing process on the density of the through hole become higher, and if the number of redundant through holes in a window range is not controlled, the density constraint may be violated, and the yield is reduced. Therefore, a via density constraint needs to be introduced. Dividing a series of grid-shaped square areas on the through hole layer, wherein the width of each square is lambda, the square areas are density windows, and the total number of the through holes in the windows cannot exceed a preset upper limit. Since one may span multiple density windows simultaneously, all density windows should be considered in selecting the RLL insertion scheme.
3) And (3) metal pattern constraint: one-dimensional patterns are easy to manufacture in the field of sublithography, and a grid-based coloring scheme can be used for dividing a layout in multiple exposure stages. Only basic graphical constraints are considered here, including end-to-end spacing rules for line-end control, minimum length rules to avoid metal shorts. There are of course more complex metal pattern rules in the advanced technology nodes that are not taken into account. For example, the self-aligned multiple exposure technique introduces a complex line-end rule that can be considered by disabling this type of line-end position during RLL candidate generation.
S20, calculating a process window and a cost corresponding to each RLL insertion scheme;
specifically, at present, the method of obtaining the process window by using the SMO tool simulation can obtain a more accurate result, but it is time-consuming. The time of the simulation operation is positively correlated with the size of the layout by 1.04x1.04mm2The simulation time of the layout of (2) is about 50 minutes. However, in the design of manufacturability, only some key parameters are needed for measurement, and accurate light source and mask layout are not needed. With the development of integrated circuit technology, the layout scale of advanced nodes becomes larger and larger, each LLC scheme needs to detect its process window, and the time cost required for judging the manufacturability of different LLC schemes by using the above method is unacceptable.
Therefore, in the embodiment, the process window can be calculated in a short time by using the machine learning model, in the embodiment, a Convolution Neural Network (CNN) is adopted to calculate the process window corresponding to each RLL insertion scheme, a design layout is given, a CNN model capable of outputting the process window is trained, and the aim is to minimize the error between the predicted value and the actual value.
Specifically, as shown in fig. 3, the process window is obtained by the following substeps:
s201, determining key region layout slices and all layout slices corresponding to each RLL insertion scheme according to the original layout, and obtaining a process window actual value corresponding to each key region layout slice through simulation;
specifically, the actual value of the process window of the sample required for the CNN training is obtained by the simulation of the EDA business tool, in order to quickly obtain the actual value of the process window of the CNN training data, the embodiment simulates only a partial region in the complete layout, specifically, the area of the simulation region is set reasonably, on one hand, the area is ensured to cover enough features in the region, on the other hand, the total simulation time of all the regions is within an acceptable range, and based on the above consideration, the area of the simulation region in the embodiment is initially determinedIs defined as 1.04X1.04mm2(ii) a In addition, due to the influence of the proximity effect, the patterns around the layout may affect the layout, and the surrounding environment (layout) of the selected layout is considered together during simulation to facilitate obtaining a more accurate result, so that it is finally determined in this embodiment to use 1000 patterns with a size of 5.04 × 5.04mm2The slices (i.e. the upper, lower, left and right sides are respectively increased by 2mm to avoid the influence of the neighbor effect) of (a) are taken as the layout slices to be simulated. Specifically, the present embodiment takes two metal layers as an example, that is, a total of 2000 single-layer layouts to be simulated. In this embodiment, layout slices of all key regions are simulated by using the MO of Tachyon, and a ring light source is selected. Because the parameter setting of some layout simulations is unreasonable, 2x900 groups of data are left after abnormal data are eliminated.
S202, slicing and pixelating all the critical area layouts, and converting the critical area layouts into a two-dimensional matrix form;
specifically, 2x900 groups of data need to be preprocessed before model training, and a critical area layout slice is converted into a two-dimensional matrix form required by a model. The general design layout is in GDS II or OASIS format, which is a coding format in vector form and only stores the coordinates and connection relation of the vertex of the graph. The size of the coding format is not fixed, and the position relation between the graphs cannot be well represented. In this embodiment, the layout is pixelated, and the structural information of the local graph is represented in a two-dimensional matrix manner. In the pixelization process, the geometric figure of the figure in the layout is read firstly and is drawn into a binary picture.
Specifically, the slicing and pixelating of the critical area layout comprises the following steps: dividing the layout slice of the key area into rectangular grids; and obtaining the state of the grid corresponding to the geometric shape based on the geometric shape of the graph in the critical area layout slice, and obtaining the two-dimensional matrix form corresponding to the graph in the critical area layout slice based on the state of each grid. In this embodiment, the uniformly distributed grids are introduced for pixelization of the layout, and the distribution of line width and line spacing is uniform based on the grid wiring model, that is, the critical area layout slice is divided into rectangular grids, as shown in fig. 4, the rectangular grids are divided into individual onesAnd each grid represents one pixel, and the size of each pixel is fixed. Each grid has only two states of full or empty, and the two states are respectively coded as 1 and 0, so that the information of the layout can be recorded by using a small amount of storage space. The size of the grid herein is 20x20nm2Thus, the two-dimensional matrix size after pixelation for each layout slice is 252x 252.
S203, performing data enhancement on the critical area layout data in the two-dimensional matrix form to obtain enhanced two-dimensional matrix data;
specifically, the layout can be directly used for training the CNN model after being converted into the two-dimensional matrix, but more sufficient training data is needed to train a good neural network model. If more data is collected artificially, more manpower and material resources are consumed. In this embodiment, only 2 × 900 groups of samples are obtained, and the efficiency of obtaining data through simulation is low, so that a data enhancement method is provided, that is, the original data is modified, and obtaining more data of the same kind is a simpler method for expanding a data set. Specifically, the data enhancement techniques may be flipping, rotating, scaling, clipping, shifting, and adding noise, among others. Since the symmetrical annular light source is used in the embodiment, the final imaging result is not influenced after the layout is rotated and turned according to a certain angle, and only vertical or horizontal graphs exist in consideration of the characteristics of one-dimensional layout graphs, so that the two-dimensional matrix corresponding to the graphs in the layout slice of the key region in the embodiment is respectively turned according to the X axis, turned according to the Y axis, turned by 90 degrees, rotated by 180 degrees and rotated by 270 degrees, and the data volume of the enhanced two-dimensional matrix is 6 times that of the original two-dimensional matrix.
S204, performing CNN model training by using the enhanced two-dimensional matrix data and the process window actual value to obtain a trained process window prediction model;
specifically, the construction of the convolutional neural network comprises the following steps:
design of the first convolutional layer conv 1: because the input layout is one-dimensional wiring and the wiring direction of each metal layer is completely consistent, the defects are usually line narrowing (pining) and adhesion (bridging) between lines. The size of the two-dimensional matrix after layout pixelation is 252x252, in order to capture the defects, the size of the convolution kernel of the first layer is set to be 5x5, and the step length is 2, so that the convolution kernel is guaranteed to have a sufficient receptive field (receptive field), and data storage and model training are facilitated. The output data size through the first convolutional layer is 124x124x 4. Then, the data size output after passing through a Pooling (Pooling) layer with size 3x3 and step size 2 is 62x62x4 by the ReLu activation function. The purpose of the ReLu activation function is to perform non-linear processing on the feature data so that the model learns complex functions. The pooling layer can reduce the number of features after convolution, facilitating model training. If all the feature data after convolution are input into the next layer network, the number of parameters in the model is increased, and overfitting is easy. It can be seen that the pooling layer reduces the amount of feature data, with data of size 124x124x4 being pooled to a size of 62x62x 4.
Convolutional layer conv2-conv5 design: conv2-conv5 all have 3 convolutional layers, each convolutional layer convolutional core having a size of 2x 2. Each 3 convolutional layers is followed by a ReLu activation function and a pooling layer, which is the same as convolutional layer con 1.
Linear layer FC1-FC3 design: the depth of the feature map deepens after the buildup layer, flattening it out with the first fully connected layer FC 1. However, the output at this time is still high latitude, and the predicted value of the process window corresponding to each layout slice is output after 2 full-connection layers (FC2 and FC3) are added finally.
Specifically, the training parameter configuration: in this embodiment, Adam is used as a gradient descent optimizer for model training, the learning rate is set to 0.01, the batch size is 40, the maximum time is set to 5 minutes, the removal rate (drop) is set to 0.5 to prevent overfitting, and the root Mean Square Error (MSE) is used as a loss function. The calculation formula of MSE is as follows:
Figure BDA0003009752270000121
wherein Q is the total number of input samples，
Figure BDA0003009752270000122
To simulate the actual values obtained using EDA tools,
Figure BDA0003009752270000123
is the predicted value output by the neural network. The Dropout layer randomly ignores the weights of some neural network nodes, plays a role in inhibiting overfitting, and improves the generalization capability, robustness and universality of the model.
In the machine learning model, if the parameters of the model are too many and the training samples are too few, the trained model is easy to generate the phenomenon of overfitting, and the overfitting is specifically shown in the following steps: the model has smaller loss function on the training data and higher prediction accuracy; but the loss function is larger on the test data, and the prediction accuracy is lower. Whether the set maximum time, the maximum step number or the loss function threshold is set or not can be judged in the training process to serve as the stopping condition.
In the embodiment, the training samples adopt a method of sampling according to batches, and the method can combine a plurality of training samples into a batch of small data sets to be trained in parallel, so that the training noise can be effectively inhibited, and the training efficiency can be improved. But the larger the batch size, the better the batch size, and the selection is required according to actual needs.
In this embodiment, the purpose of model training is to minimize the amount of error between the predicted value and the actual value. In the application, 5 minutes are needed for training a CNN model, and the time for predicting a process window by using the CNN model is about 3.2 ms; the time required for obtaining the process window by using software simulation generally exceeds 30 minutes, and the specific time is related to the scale of the simulation layout. Speed improvement of machine learning model method by 5x 105And the time cost is greatly saved. The error of the prediction by the method is about 3.2%. Since most layouts have process windows in the range of 80 to 100, the number of samples less than 80 and greater than 100 is relatively small. Therefore, there is a problem of data imbalance (data interference) in model training. If the model is applied to the occasion with higher precision requirement, the model can be pertinently usedThe accuracy of model prediction is further improved by methods of supplementing data with less sample amount, adjusting the proportion of sample sampling during training or dynamically adjusting the proportion of different samples in a loss function and the like.
S205, converting all layout slices corresponding to each RLL insertion scheme of the original layout into two-dimensional matrix data, and sequentially inputting the two-dimensional matrix data into the trained process window prediction model to obtain process windows of all the layouts corresponding to each RLL insertion scheme.
Specifically, each RLL insertion scheme may correspond to multiple metal layers, so that each RLL insertion scheme corresponds to multiple layout slices, pixelating all the layout slices corresponding to each RLL insertion scheme of the original layout to obtain two-dimensional matrix data of all the layout slices corresponding to the RLL insertion scheme, sequentially inputting the two-dimensional matrix data into the trained process window prediction model to obtain process windows of all the layouts corresponding to the RLL insertion scheme
Figure BDA0003009752270000131
Wherein the content of the first and second substances,
Figure BDA0003009752270000132
and (4) inserting process windows of all layout slices corresponding to the ith RLL inserting scheme.
S206, determining process windows corresponding to the RLL insertion scheme by the process windows of all the layouts corresponding to the RLL insertion scheme;
specifically, the RLL insertion scheme corresponds to a process window P ═ { P ═ P1,p2,…pi… is obtained by weighting the process windows of all layouts corresponding to the RLL insertion scheme, wherein p isiA process window corresponding to the ith RLL insertion scheme, specifically, the process window corresponding to each RLL insertion scheme may be used as the process window of the scheme according to the weighted average, the maximum value, or the minimum value of the process window corresponding to each layout slice in the scheme, and in this embodiment, the minimum value of all the process windows in the scheme is selected as the process window of the scheme, that is, the minimum value is selected as the process window of the scheme, that is, the process window corresponding to the ith RLL insertion scheme is used as the process window of the scheme
Figure BDA0003009752270000141
S30, calculating an objective function by using each cost function and each process window, and obtaining an optimal RLL insertion scheme according to the objective function;
specifically, the entire RLL insertion scheme is obtained in the above step, and the appropriate RLL insertion scheme is selected for each via hole below. In this embodiment, a binary variable x is usediIndicates whether the RLL insertion scheme is selected as the insertion scheme of the redundant via when xiWhen 0, this scheme is not selected, and specifically, the objective function is expressed as:
Figure BDA0003009752270000142
wherein x isiInsert the corresponding binary variable, x, for the ith RLLiE {0,1},; delta, epsilon and zeta are weight parameters; n isiThe number of vias contained for the ith RLL insertion scheme; c. CiInserting a cost corresponding to the ith RLL scheme; p is a radical ofiAnd inserting the corresponding process window for the ith RLL.
First item
Figure BDA0003009752270000143
Is the number of redundant vias introduced, item two
Figure BDA0003009752270000144
Is the sum of costs, the third term
Figure BDA0003009752270000145
Is the sum of the process windows and the parameters δ, ε, ζ are used to balance these three criteria.
Specifically, since the process window is important to a different extent in different regions, such as a <70 region, each reduction may severely compromise manufacturability of the design, while in a safe region, the process window increases or decreases significantly less impact on the design than in the former. The weight parameter ζ of the process window corresponding to each RLL insertion scheme in the objective function in this embodiment is expressed as:
Figure BDA0003009752270000151
wherein p isiFor the process window corresponding to the ith RLL insertion scheme, d and m are control parameters for controlling the slope of the curve, which is the largest at the starting position (smaller process window) and smaller toward the ending position (larger process window). The advantage of this function is that the smaller the process window, the larger the position ζ and the faster the growth, can be flexibly adjusted according to the actual situation, in this embodiment, the value of d is 4, and the value of m is 120.
Specifically, different RLL insertion schemes have different costs, and due to the influence of the manufacturing process, different RLLs have different influences on the yield, and the cost corresponding to each RLL insertion scheme is calculated by using the following cost function:
Figure BDA0003009752270000152
wherein, the number of the metal layer layers is J, the number of the through hole layer layers is J-1, ciCost of the ith RLL insertion scheme, αjCost weight parameter, m, for the jth metal layeri,jTrace length, beta, introduced on jth metal layer for ith RLL insertion schemekCost weight parameter, v, for the k-th via layeri,kThe number of redundant vias introduced on the kth via layer for the ith RLL insertion scheme, specifically, the trace length and the number of redundant vias on metal layers not involved in the RLL insertion scheme are 0.
And S40, performing redundant local loop insertion based on the optimal RLL insertion scheme, and outputting a final layout.
Specifically, in the present embodiment, the insertion rate, the insertion cost, and the process window are considered comprehensively, and the weights of the three may be adjusted as needed. Compared with a method without considering the process window, the method improves the process window under the same insertion rate, and effectively improves the manufacturability of the design.
As shown in fig. 5, another embodiment of the present invention discloses a semiconductor physical design method based on a process window redundant local loop insertion method, which includes:
inputting an initial circuit layout, and partitioning the initial circuit layout to obtain a plurality of sub-circuits;
planning the positions and the geometric shapes of chips in the plurality of sub-circuits, and carrying out position layout and wiring treatment on the planned plurality of sub-circuits to obtain a first layout;
performing redundant local loop insertion in the first layout according to the optimal redundant local loop insertion scheme to obtain an output layout;
and preparing a hardware circuit by using the output layout.
Those skilled in the art will appreciate that all or part of the flow of the method implementing the above embodiments may be implemented by a computer program, which is stored in a computer readable storage medium, to instruct related hardware. The computer readable storage medium is a magnetic disk, an optical disk, a read-only memory or a random access memory.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.

Claims (7)

1. A redundant local loop insertion method based on a process window is characterized by comprising the following steps:
inputting an original layout, and extracting to obtain all through hole information and all available RLL insertion schemes;
calculating a process window and a cost corresponding to each RLL insertion scheme, wherein the process window and the cost comprise the following steps:
determining key region layout slices and all layout slices corresponding to each RLL insertion scheme according to the original layout, and obtaining a process window actual value corresponding to each key region layout slice through simulation; slicing and pixelating all the critical area layouts, and converting the critical area layouts into a two-dimensional matrix form; performing data enhancement on the key region layout data in the two-dimensional matrix form to obtain enhanced two-dimensional matrix data; performing CNN model training by using the enhanced two-dimensional matrix data and the process window actual value to obtain a trained process window prediction model; converting all layout slices corresponding to each RLL insertion scheme of the original layout into corresponding two-dimensional matrix data, and sequentially inputting the two-dimensional matrix data into the trained process window prediction model to obtain process windows of all the layouts corresponding to the RLL insertion schemes; determining process windows corresponding to the RLL insertion scheme by the process windows of all the layouts corresponding to the RLL insertion scheme;
and calculating the cost corresponding to each RLL insertion scheme by using the following cost function:
Figure FDA0003610536670000011
wherein, the number of the metal layer layers is J, the number of the through hole layer layers is J-1, ciCost of the ith RLL insertion scheme, αjCost weight parameter, m, for the jth metal layeri,jThe trace length, beta, introduced on the jth metal layer for the ith RLL insertion schemekCost weight parameter, v, for the k-th via layeri,kThe number of redundant vias introduced on the kth via layer for the ith RLL insertion scheme;
calculating an objective function by using each cost function and each process window, and obtaining an optimal RLL insertion scheme according to the objective function; the objective function is expressed as:
Figure FDA0003610536670000021
wherein x isiInserting the corresponding binary variable of the scheme for the ith RLL，xiE {0,1 }; delta, epsilon and zeta are weight parameters; n isiThe number of vias contained for the ith RLL insertion scenario; c. CiInserting a cost corresponding to the scheme for the ith RLL; p is a radical ofiInserting a process window corresponding to the ith RLL inserting scheme;
and performing redundant local loop insertion based on the optimal RLL insertion scheme, and outputting a final layout.
2. The process window based redundant local loop insertion method of claim 1, wherein the critical area layout slice pixelation comprises:
dividing the layout slice of the key area into rectangular grids;
and obtaining the state that the grid corresponding to the geometric shape is full or empty based on the geometric shape of the graph in the layout slice of the key area, and obtaining the two-dimensional matrix form corresponding to the graph in the layout slice of the key area based on the state of each grid.
3. The process window-based redundant local loop insertion method according to claim 2, wherein the data enhancement comprises respectively turning over a two-dimensional matrix corresponding to a pattern in the critical area layout slice according to an X-axis, turning over according to a Y-axis, rotating by 90 °, rotating by 180 °, and rotating by 270 °, to obtain enhanced two-dimensional matrix data.
4. The process window-based redundant local loop insertion method according to any one of claims 1 to 3, wherein all layout slices corresponding to each RLL insertion scheme of the original layout are pixelated to obtain two-dimensional matrix data of all layout slices corresponding to the RLL insertion scheme, the two-dimensional matrix data are sequentially input into the trained process window prediction model to obtain process windows of all layouts corresponding to the RLL insertion scheme, and the process windows of all the layouts corresponding to the RLL insertion scheme determine that the process window P ═ P corresponding to each RLL insertion scheme1,p2,…pi… } in which piFor the ith RLL insertAnd entering a process window corresponding to the scheme.
5. The method of claim 1, wherein the weight parameter ζ of the process window corresponding to each RLL insertion scheme in the objective function is expressed as:
Figure FDA0003610536670000031
wherein d and m are control parameters, piThe corresponding process window for the ith RLL insertion scheme.
6. The process window based redundant local loop insertion method of claim 1, further comprising: extracting all through hole information, all RLL insertion schemes and the number J of metal layer layers in the original layout according to the original layout to obtain the number N of through holes contained in each RLL insertion scheme, wherein the number N of through holes is N1,n2…ni… } and the number of redundant vias v introduced on the k-th via layer by the RLL insertion schemei,k，niThe number of vias contained for the ith RLL insertion scheme.
7. A method for semiconductor physical design based on process window redundant local loop insertion using the method of any one of claims 1-6, comprising:
inputting an initial circuit layout, and partitioning the initial circuit layout to obtain a plurality of sub-circuits;
planning the positions and the geometric shapes of chips in the plurality of sub-circuits, and carrying out position layout and wiring treatment on the planned plurality of sub-circuits to obtain a first layout;
performing redundant local loop insertion in the first layout according to the optimal redundant local loop insertion scheme to obtain an output layout;
and preparing the semiconductor hardware circuit by using the output layout.
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