CN117148685A

CN117148685A - Regression model-based pilot process photoetching dead pixel detection method

Info

Publication number: CN117148685A
Application number: CN202311106019.XA
Authority: CN
Inventors: 林泽邦; 任堃; 高大为
Original assignee: Zhejiang University ZJU
Current assignee: Zhejiang University ZJU
Priority date: 2023-08-30
Filing date: 2023-08-30
Publication date: 2023-12-01

Abstract

The invention discloses a regression model-based pilot process photoetching dead pixel detection method. The invention adopts a layout generator to generate a virtual layout, and finds out the photoetching dead point through photoetching simulation and performs slicing. Expanding the slice, and then calculating the label of the slice again through lithography simulation. And carrying out frequency domain transformation on the slice, and training a regression model by using coefficients in the frequency domain and labels of the slice as training data. For a design department, the model can be used for determining bad points possibly appearing in the layout and the occurrence probability thereof, and different local constraints are adopted for different areas. For the manufacturing department, the model can be used for rapid dead point detection, and the data set is updated by using the actual simulation result. The method can quickly establish the dead point detection model in the research and development of the leading process node, and reduces the difficulty of design and manufacture.

Description

Regression model-based pilot process photoetching dead pixel detection method

Technical Field

The invention belongs to the technical field of semiconductor manufacturing, and particularly relates to a regression model-based pilot process photoetching dead pixel detection method.

Background

As the feature sizes of integrated circuits continue to shrink, the process difficulty of integrated circuit fabrication increases, and design departments and manufacturing departments need to perform closer communications to establish more accurate constraints, so that design for manufacturing (Design forManufacturing, DFM) and design and process co-optimization (DTCO) are presented, providing a way for two-way communications between the manufacturing departments and the design departments.

Many process defects occur in the manufacture of integrated circuits due to diffraction limitation of optical systems, and photo-lithography defects such as pinch-off (pinchoff) and bridge (bridge) occur, which cause device failure. If one wants to avoid these photolithographic bad spots by tightening the design rules, the difficulty of the design is greatly increased. The high-efficiency and accurate dead pixel detection technology is beneficial to accelerating the publishing period of the layout and reducing the cost of process research and development.

The dead pixel detection commonly used at present mainly comprises model simulation and pattern matching. All bad points on the layout can be detected by the model simulation, but the technology is usually used in combination with other bad point detection technologies because OPC simulation of the whole layout consumes a lot of time. The bad point detection technology based on pattern matching is based on a bad point pattern library. As feature sizes shrink, the library of bad point patterns becomes larger and larger, and the time for detecting bad points becomes longer and longer. Before a new process (i.e., a lead process) is not established, the bad spot pattern library is not complete, and thus a large number of bad spots are introduced during design. With the gradual maturation of the process, the dead pixel graphic library can be gradually perfected, and the ratio of the layout matching area is improved.

Therefore, how to improve the accuracy and flexibility of the photolithography dead spot detection in the pilot process is a problem to be solved.

Disclosure of Invention

The invention aims to overcome the defects of the existing photoetching dead pixel detection technology, and provides a regression model-based pilot process photoetching dead pixel detection method, which realizes that a dead pixel detection model is built before process establishment, does not need to undergo a long accumulation process of dead pixel patterns, and improves the flexibility of design on the premise of ensuring the dead pixel detection accuracy.

The aim of the invention is realized by the following technical scheme:

in a first aspect, the present invention provides a pilot process lithography dead pixel detection model, and the training method of the model includes the following steps:

(1) Constructing a classical graphic library and a standard unit library of a pilot process layout; wherein the lead process refers to an immature process;

(2) Using a layout generator, and combining element designs in a classical graphic library and a standard cell library into a virtual layout of a pilot process;

(3) Resetting a target for the virtual layout according to the required pilot process information, and then performing optical proximity effect correction (Optical Proximity Correction, OPC) to obtain a graph on the photomask; simulating the graph on the photomask by using a photoetching simulation model, and marking the position of a photoetching dead point; slicing the virtual layout according to the position of the photoetching dead point obtained by simulation to obtain a first slice;

the pilot process information comprises etching deviation and photoetching selectivity deviation;

the optical proximity effect correction adopts at least one of inserting a Scattering Bar (Scattering Bar), adding an auxiliary pattern, adjusting the line length of the line pattern, adjusting the line width of the line pattern and the like;

(4) Using a layout generator to carry out diversified expansion on the first slice to obtain a plurality of second slices, wherein the second slices comprise a first slice region and an expansion region; using a layout generator to carry out diversified expansion on a plurality of second slices to obtain a plurality of third slices, wherein the third slices comprise second slice areas and expansion areas; performing reset target and optical proximity effect correction on the third slice;

the optical proximity correction process for the third slice includes the following:

(1) In the first slicing area, adjusting the line width and the line length of the line pattern, and adding auxiliary patterns and scattering bars;

(2) Adding auxiliary patterns and scattering bars to the non-first slice part in the second slice area;

(3) The non-second slice portion within the third slice region is not adjusted;

performing photoetching simulation on the processed third slice, and taking the proportion of the occurrence of photoetching dead pixels of the third slice as the probability that the first slice becomes the dead pixels, namely the label of the first slice;

(5) Downsampling the first slice with the label, then carrying out frequency domain transformation, and enhancing the frequency domain information; a regression model is trained using the low frequency coefficients in the frequency domain of the first slice and its labels.

(6) And (5) utilizing the trained regression model to realize the photoetching dead point detection of the pilot process.

Further, the frequency domain transformation in the step (5) is a discrete cosine transformation (Discrete Cosine Transform, DCT) or a fast fourier transformation (Fast Fourier Transform, FFT).

Further, the regression model in the step (5) is a linear regression model, a random forest regression model or a gradient lifting regression model.

In a second aspect, the present invention provides a lead process lithography dead pixel detection apparatus, including:

the data acquisition module is in charge of acquiring a layout sample;

the data preprocessing module is responsible for resetting a target of a layout sample and then correcting an optical proximity effect to obtain a graph on a photomask; cutting out a slice on a photomask graph by using a sliding window, and carrying out downsampling and frequency domain transformation on the slice to obtain a low-frequency coefficient in a frequency domain of the slice;

and the dead pixel detection module is responsible for inputting the low-frequency coefficient in the frequency domain of the slice into the trained regression model to predict the photoetching dead pixel.

In a third aspect, the present invention provides a method for designing and verifying a pilot process layout, including the steps of:

(1) The design department performs physical verification on the designed pilot process layout to obtain an actual layout;

(2) Resetting the target and correcting the optical proximity effect of the actual layout to obtain a pattern on the photomask;

(3) Cutting out a slice on a photomask graph by using a sliding window, and carrying out downsampling and frequency domain transformation on the slice to obtain a low-frequency coefficient in a frequency domain of the slice; predicting by using a regression model to obtain the probability that each slice on the layout becomes a dead pixel;

(4) If the predicted result meets the manufacturing requirement, the actual layout is delivered to a manufacturing department for chip manufacturing, otherwise, the actual layout is changed, and the processes such as physical verification are carried out again.

Further, the manufacturing requirements in step (4) may place different levels of constraints on critical and redundant designs. Accumulating the probabilities of photoetching dead pixels in different areas, applying strict constraint to key designs, and setting lower local thresholds; relaxed constraints are imposed on the redundant design, setting higher local thresholds.

In a fourth aspect, the present invention provides a method for modifying a pilot process layout, including the steps of:

(1) The manufacturing department resets the target and corrects the optical proximity effect to the actual layout to obtain the graph on the photomask;

(2) Cutting out a slice on a photomask graph by using a sliding window, and carrying out downsampling and frequency domain transformation on the slice to obtain a low-frequency coefficient in a frequency domain of the slice; predicting by using a regression model to obtain the probability that each slice on the layout becomes a dead pixel;

(3) The probability of a dead pixel is ordered in a descending order, and the first n slices are taken for individual optical proximity effect correction;

(4) Performing photoetching simulation on the corrected layout to find out actual photoetching hot spots;

(5) And (3) judging whether the current layout meets the publishing requirement according to the result of the actual simulation, if so, delivering the photomask factory to produce the photomask, otherwise, further correcting the hot spot, and returning to the step (4).

Further, the actual lithography hotspots in the step (4) may slice the layout according to the position thereof, and update the data set of the lithography bad spots to perfect the lithography bad spot data set.

In a fifth aspect, the present invention provides a computer device comprising a memory, a corrector and a computer program stored in said memory and operable on said corrector, said corrector implementing the steps of the above method when said computer program is executed.

In a sixth aspect, the present invention provides a computer readable storage medium storing a computer program which when executed by a corrector performs the steps of the above method.

In the conventional dead pixel detection, the detector is classified into two types for a slice, i.e., a slice is classified into a dead pixel and a non-dead pixel. In practice, whether a slice is dead will depend not only on the slice, but also on the surrounding environment of the slice. For example, the probability that a certain first slice becomes a dead pixel is calculated to be 0.7, and a conventional dead pixel detector classifies the first slice as a dead pixel, so that a designer is prohibited from adopting the design in a layout. Compared with the prior art, the invention has the beneficial effects that: the method can flexibly treat the slice according to the actual situation, if the first slice is used, the design area can be saved, the process deviation can be reduced, and on the premise of ensuring the manufacturability, a designer can contain the first slice in a design area with redundancy. In addition, the regression model is adopted to improve the prediction precision and the generalization capability of the model. For a manufacturer, the optical proximity correction needs to be iterated round by round until the manufacturability of the layout meets the requirements. The most time-consuming link in the optical proximity effect correction flow is photoetching simulation, and the number of times of photoetching simulation can be reduced and the photomask publishing period can be shortened by detecting bad points through the regression model trained by the method and processing the bad points independently.

Drawings

FIG. 1 is a schematic diagram of a regression model-based pilot process lithography dead pixel detection method, including a data set building flow, a model training method, and a model using flow by a design department and a manufacturing department;

FIG. 2 (a) is a schematic diagram of a virtual design generated by a virtual layout generator; (b) A schematic diagram of a photomask pattern corrected by a reset target and optical proximity effect; (c) The photoresist pattern on the wafer after photoetching simulation is a photoresist dead pixel diagram; (d) Schematic diagrams of position slices of lithography dead pixels in the virtual design according to simulation results;

FIG. 3 is a slice expansion result;

fig. 4 (a) shows a first slice of a photo-etched dead pixel with a label; (b) is a density map obtained after downsampling; (c) Schematic representation of frequency domain information after frequency domain transformation;

FIG. 5 is an optical proximity correction flow;

FIG. 6 is a slice expansion and label computation flow.

Detailed Description

The invention will be described in further detail with reference to the drawings and the detailed description.

When a semiconductor fabrication facility wants to further shrink feature sizes, for example, a semiconductor fabrication facility already has mass-produced 55nm technology node products, and a 28nm new process is to be established, then the 28nm process is a precursor process for the semiconductor fabrication facility. In the building flow of the new process, global optimal design rules of the design and the process should be comprehensively planned in order to ensure manufacturability of the final design layout and ensure manufacturing yield. The designer should consider the manufacturing process before designing, and the manufacturer should use a layout similar to the actual design during the development of the pilot process.

As shown in fig. 1. Before the process is established, a classical graphic library and a standard unit library are provided by a design department, a manufacturing department generates a virtual layout through a layout generator, and bad points are found out through simulation. And slicing the dead pixel as a center, changing the environment of the dead pixel, calculating the probability of the slice becoming the dead pixel, and training a regression model through downsampling and frequency domain transformation. In the process of process establishment, the simulation result can be fully utilized to update the data set.

The regression model-based pilot process photoetching dead point detection method uses a layout generator to generate a virtual design, can establish a photoetching dead point detection model under the condition that the pilot process node lacks a real design, can continuously perfect a data set in the subsequent research and development process, and provides a dynamic design rule. Secondly, the detection method calculates the probability of the dead pixel by changing the surrounding environment of the dead pixel slice, and is more accurate than the conventional binary judgment of whether the dead pixel is dead. In addition, the design department can adopt different local constraints for different areas, such as SRAM units, standard cell libraries, analog circuits and the like, so that the flexibility of design is improved, and the difficulty of design is reduced; the manufacturing department can find out hot spots and process the hot spots independently under the condition of no simulation, so that the number of optical proximity correction cycles is reduced, and the publishing speed of the photomask is increased.

The invention provides a regression model-based pilot process lithography dead pixel detection method, which comprises the following steps:

(2) Using a layout generator and a Monte Carlo method, and combining element designs in a classical graph library and a standard cell library into a virtual layout of a pilot process;

the rules generated by the layout generator may be random combinations or user-defined rules, as shown in fig. 2 (a), using classical pattern combinations to generate a virtual layout of the polysilicon gate layer.

(3) Resetting a target (retarget) for the virtual layout according to an etching Bias Table (etching Bias Table) and a photoetching selective Bias algorithm Table (Selected BiasAlgorithm Table), and then inserting a Scattering Bar (Scattering Bar) based on a rule method to perform optical proximity effect correction (Optical Proximity Correction, OPC) of FIG. 5 to obtain a graph on a photomask; simulating the graph on the photomask by using a photoetching simulation model, and marking the position of a photoetching dead point; slicing the virtual layout according to the position of the photoetching dead point obtained by simulation to obtain a first slice;

the reset target is determined according to the process information of the process flows such as lithography and etching, and the optical proximity effect correction can be performed according to an optical proximity effect correction process menu (record) of the previous process technology node, as shown in (b) of fig. 2, and the virtual layout becomes a photomask pattern after being subjected to the reset target and the optical proximity effect correction.

The lithography simulation model comprises an optical model and a photoresist model, and as shown in (c) of fig. 2, after the photomask pattern is subjected to lithography simulation, the position of a lithography dead pixel at the marked position can be marked, wherein the lithography dead pixel adopts darker color marking in the graph.

The bad point slice is a sub-graph cut out from the virtual layout according to the bad point position obtained by photoetching simulation, and as shown in (d) of fig. 2, the slice size is 1 μm by 1 μm.

(4) As shown in fig. 6, the layout generator is used for carrying out diversified expansion on the first slice, so as to obtain a plurality of second slices with the sizes of 3 μm by 3 μm, wherein the second slices comprise a first slice region and an expansion region; using a layout generator to carry out multi-element expansion on a plurality of second slices to obtain a plurality of third slices with the sizes of 9 mu m x 9 mu m, wherein the third slices comprise second slice areas and expansion areas; performing reset target and optical proximity effect correction on the third slice;

as shown in fig. 3, the center points of the different slices are overlapping. A is a first slice which is derived from a slice of the virtual layout, can adjust the line width of the line graph, prolong the line of the line graph and add the graph; b is a second slice, the second slice randomly generates patterns around the first slice to form, and auxiliary patterns or scattering bars can be added; c is a third slice, and the third slice randomly generates a pattern around the second slice to participate in lithography simulation.

(3) The non-second slice portion within the third slice region is not adjusted;

the diversified expansion is similar to the generation of a virtual layout, and auxiliary graphics are added on the basis of the original slicing;

(5) The first slice with the label is downsampled, a data set can be enriched in a data enhancement mode, then frequency domain transformation is carried out, and frequency domain information of the first slice is enhanced; a regression model is trained using the low frequency coefficients in the frequency domain of the first slice and its labels.

The downsampling method is based on density sampling, the size of the downsampled picture is 128pixel, and as shown in (b) of fig. 4, the downsampled picture becomes a gray image of 128 pixel. The dataset may be enhanced with rotation, mirroring, etc. on the density map.

The frequency domain transformation method is discrete cosine transformation, as shown in fig. 4 (c), the frequency domain information of the graph after the frequency domain transformation is effectively enhanced, and the imaging process of the optical system is more satisfied.

The regression model is a random forest regression model, and the data set is calculated according to 4: the ratio of 1 is divided into a training set and a verification set, and parameters such as the number of subtrees, the maximum growth depth of the tree, the minimum sample number of leaves, the minimum sample number of branch nodes, the maximum selection feature number and the like are determined by using grid search.

Example 2: a design and verification method of a pilot process layout comprises the following steps:

(3) Cutting out a slice on a photomask graph by using a sliding window, wherein the window size is 1 μm x 1 μm, the step size is 0.1 μm x 0.1 μm, and performing downsampling and frequency domain transformation on the slice to obtain a frequency domain medium-low frequency coefficient of the slice; predicting by using a regression model to obtain the probability that each slice on the layout becomes a dead pixel;

Example 3: a correction method of a pilot process layout comprises the following steps:

(2) Cutting out a slice on a photomask graph by using a sliding window, wherein the window size is 1 μm x 1 μm, the step size is 0.1 μm x 0.1 μm, and performing downsampling and frequency domain transformation on the slice to obtain a frequency domain medium-low frequency coefficient of the slice; predicting by using a regression model to obtain the probability that each slice on the layout becomes a dead pixel;

(3) Ordering the probability of being dead pixels in a descending order, taking the first n slices for individual optical proximity correction, such as inverse lithography (ILT, inverse Lithography Technology);

The foregoing description of the preferred embodiment(s) is (are) merely intended to illustrate the embodiment(s) of the present invention, and it is not intended to limit the embodiment(s) of the present invention to the particular embodiment(s) described.

Claims

1. A regression model-based pilot process photoetching dead pixel detection method is characterized by comprising the following steps of:

constructing a classical graphic library and a standard unit library of a pilot process layout;

using a layout generator, and combining element designs in a classical graphic library and a standard cell library into a virtual layout of a pilot process;

resetting a target for the virtual layout according to the required pilot process information, and then correcting the optical proximity effect to obtain a graph on the photomask;

simulating the graph on the photomask by using a photoetching simulation model, and marking the position of a photoetching dead point;

slicing the virtual layout according to the position of the photoetching dead point obtained by simulation to obtain a first slice;

using a layout generator to carry out diversified expansion on the first slice to obtain a plurality of second slices; wherein the second slice comprises a first slice region and an expansion region;

using a layout generator to carry out multi-element expansion on a plurality of second slices to obtain a plurality of third slices; wherein the third slice comprises a second slice region and an expansion region;

performing reset target and optical proximity effect correction on the third slice;

performing photoetching simulation on a third slice subjected to the resetting target and the optical proximity effect correction treatment, and taking the proportion of the occurrence of photoetching dead spots of the third slice as the probability that the current first slice becomes the dead spot, namely the label of the current first slice;

downsampling a first slice with a label at present and carrying out frequency domain transformation to obtain a low-frequency coefficient in a frequency domain of the first slice; training a regression model by using the low-frequency coefficient and the label in the frequency domain of the first slice;

and (5) utilizing the trained regression model to realize the photoetching dead point detection of the pilot process.

2. The method of claim 1, wherein the optical proximity correction procedure for the third slice comprises the following:

the line width and the line length of the line pattern are adjusted for the first slicing area, and auxiliary patterns and scattering bars are added;

auxiliary patterns and scattering bars are added to the non-first slice portions within the second slice region.

3. The method of claim 1, wherein the precursor process information includes etch bias, photolithographic selectivity bias;

the optical proximity effect correction adopts at least one of inserting a scattering bar, adding an auxiliary pattern, adjusting the line length of the line pattern and adjusting the line width of the line pattern.

4. The method of claim 1, wherein the frequency domain transform is a discrete cosine transform or a fast fourier transform.

5. The method of claim 1, wherein the regression model is a linear regression model, a random forest regression model, or a gradient lifting regression model.

6. A lead process lithography dead pixel detection apparatus for implementing the method of any one of claims 1-5, comprising:

the data acquisition module is in charge of acquiring a layout sample;

7. The design and verification method of the pilot process layout is characterized by comprising the following steps:

(3) Cutting out a slice on a photomask graph by using a sliding window, and carrying out downsampling and frequency domain transformation on the slice to obtain a low-frequency coefficient in a frequency domain of the slice; predicting by using the regression model trained by the method of any one of claims 1 to 5 to obtain the probability of each slice on the layout becoming a dead pixel;

(4) If the predicted result meets the manufacturing requirement, delivering the actual layout to a manufacturing department for chip manufacturing, otherwise, changing the actual layout, and returning to the step (1).

8. A correction method of a pilot process layout is characterized by comprising the following steps:

(2) Cutting out a slice on a photomask graph by using a sliding window, and carrying out downsampling and frequency domain transformation on the slice to obtain a low-frequency coefficient in a frequency domain of the slice; predicting by using the regression model trained by the method of any one of claims 1 to 5 to obtain the probability of each slice on the layout becoming a dead pixel;

9. A computer device comprising a memory, a corrector and a computer program stored in the memory and operable on the corrector, characterized in that the corrector, when executing the computer program, carries out the steps of the method as claimed in any one of claims 1-5.

10. A computer readable storage medium storing a computer program, characterized in that the computer program when executed by a corrector implements the steps of the method according to any one of claims 1-5.