CN109585419A - Reinforce important area the chip top-layer metal protection layer wiring method of protection - Google Patents
Reinforce important area the chip top-layer metal protection layer wiring method of protection Download PDFInfo
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- CN109585419A CN109585419A CN201811165211.5A CN201811165211A CN109585419A CN 109585419 A CN109585419 A CN 109585419A CN 201811165211 A CN201811165211 A CN 201811165211A CN 109585419 A CN109585419 A CN 109585419A
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- Prior art keywords
- wiring
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- layer
- chip
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/57—Protection from inspection, reverse engineering or tampering
- H01L23/573—Protection from inspection, reverse engineering or tampering using passive means
Abstract
The present invention relates to chip technologies; line density is walked for top wire can be improved using this method in the fields such as information security, reduces the shielding line failure area of key area; increase attacker and analyze circuit difficulty, achievees the purpose that lay special stress on protecting the key area of chip.Attacker be can effectively prevent by photographic analysis reverse engineering, the attack means such as FIB obtain Data within the chip, improve the safety coefficient of chip key area.Thus, the technical solution adopted by the present invention is that, reinforce important area the chip top-layer metal protection layer wiring method of protection, first the protection level according to actual chips size planning wiring area area and each region, is divided into several wiring areas for top-level metallic shielded layer；Each routing cell is subjected to wiring filling further according to the safety coefficient of wiring area, the cabling quantity in each region is incremented by according to the rising of security level.Present invention is mainly applied to chips to manufacture and design occasion.
Description
Technical field
The present invention relates to chip technology, the fields such as information security specifically are related to reinforcing important area the chip of protection
Top-level metallic protective layer wiring method.
Background technique
Currently, information security issue becomes increasingly conspicuous, every field all proposes increasingly higher demands to information security.It is integrated
Circuit chip is as information system core component, safety of the security relationship to entire information system.With microelectronics
Technology is constantly progressive, and is constantly suggested for the physical attacks means of IC chip, chip secure and become safety
One important research proposition in field.
Compared with software security problem, hardware chip is the field for waiting developing safely.The hand of hardware attack chip
Section is gradually diversified, for using image analysis to obtain chip internal structure, uses focused ion beam (FIB, Focused later
Ion beam) modification circuit attack, existing preventive means mainly uses top-level metallic protective layer.It is adopted in the top layer of chip
With one or more layers metal routing, the unit and line of lower section are shielded, hides Key Circuit, and play the role of fascination.And
In top-level metallic cabling, one end is passed through detection signal, and the other end compares detection, can be with if deviation occurs in discovery signal
Illustrate to detect attack.But due to existing top layer wiring metal, in the form of a single, mostly parallel cabling is gone down, it is snakelike
Cabling, the topological structures such as helix, connection relationship is simple, easily by domain photographic analysis or reverse engineering, so that protective layer fails.
For such attack, this patent proposes a kind of new-type metal protection layer placement-and-routing method, in conjunction with the bottom of chip
Layer device layout structure carries out key protection to the important area of chip.Wiring layer is divided into the cloth of several different safety class
Line region, and it is individually designed to the progress of the cabling of different zones, improve the safety of top-level metallic protective layer.
Bibliography
1.Skorobogatov S.Physical attacks and tamper resistance[M]//
Skorobogatov S.In-troduction to Hardware Security and Trust.Springer,2012:
2012:143–173.
2.Samyde D,Skorobogatov S,Anderson R,et al.On a new way to read data
from memory[C].In Security in Storage Workshop,2002.Proceedings.First
International IEEE,2002:65–69.
3. anti-physical attack safety chip key technology research [D] [S.l.] of Xu Min: University Of Tianjin, 2012.
4.Skorobogatov S P.Semi-invasive attacks:a new approach to hardware
security anal-ysis[D].[S.l.]:Citeseer,2005。
Summary of the invention
In order to overcome the deficiencies of the prior art, the present invention is directed to propose a kind of novel chip shielded layer Wiring method, utilizes
This method can be improved top wire and walk line density, reduces the shielding line failure area of key area, increases attacker's analysis
Circuit difficulty achievees the purpose that lay special stress on protecting the key area of chip.Attacker be can effectively prevent by taking pictures point
Reverse engineering is analysed, the attack means such as FIB obtain Data within the chip, improve the safety coefficient of chip key area.For this purpose, this hair
It is bright to adopt the technical scheme that, reinforce important area the chip top-layer metal protection layer wiring method of protection, first according to practical
Chip size plans the protection level of wiring area area and each region, and top-level metallic shielded layer is divided into several wiring regions
Domain；Each routing cell is subjected to wiring filling further according to the safety coefficient of wiring area, the cabling quantity root in each region
It is incremented by according to the rising of security level；It will test signal after the completion to input from the left side certain port of protective layer, completely pass through
Wiring layer carries out the output of detection signal on right side, detects signal integrity, judge whether to receive attack, and judge to be attacked
Region.
Specifically, snakelike cabling, parallel cabling top layer protective layer trace configurations method: can be used in each wiring area
Or random hamiltonian circuit mode carries out wiring filling.
Specifically, key area wiring method: wiring is divided into the region of four pieces of different degree of protection, further according to core
The internal structure of piece, chip module easily break through degree, carry out region division to protective layer, and with A, B, C grade label, come area
Divide the protection level in these regions；Wherein, C region security grade is minimum, and B area safety coefficient is medium, and a-quadrant safety coefficient is most
It is high；After completing layout, metal routing filling is carried out to the region of various wirings security level: by adjacent and security level compared with
Low wiring area merges, and carries out unified wiring to these regions, is filled, is filled with the metal wire of large area
Potential lines quantity is successively successively decreased from high to low with safety coefficient；For the wiring area B area compared with high safety grade, using intensive
Metal wire carry out wiring filling；To the highest a-quadrant of security level, it is routed using random hamiltonian circuit；It is another
Wire laying mode can all be filled all areas using random hamiltonian circuit, but distinguish on the item number of cabling；
It in the region C, is routed using two random hamiltonian circuits, for B area, uses three parallel random hamiltonian circuits
It is routed, for a-quadrant, is routed using four or more random hamiltonian circuits, and its individually designed figure.
Specifically, protective layer connection method: signal send structure send monitoring signals from the several nodes of left margin into
Enter, by the metal routing in each wiring area, the output port for reaching right margin is connected with detection structure, and with input
Original signal compares, that is, can determine whether under attack；If each port persistently has received detection signal, judgement does not have
Have under attack；If there is one or more signal deletion, region under attack is judged according to the route of missing.
The features of the present invention and beneficial effect are:
Top wire wiring is carried out using method proposed by the present invention, so that originally single wiring becomes have multiplicity
Property, the identification difficulty of wiring is increased, while also increasing the difficulty that attacker modifies circuit, which adds protective layers
Safety coefficient.Outside it, there is a plurality of access by cabling in synchronization, increase the identification difficulty of attacker, and can lead to
The safety coefficient for changing the quantity increase region of access is crossed, level of protection is further increased.
Detailed description of the invention:
Fig. 1 chip interior schematic diagram.
The wiring area Fig. 2 divides figure.
Fig. 3 module fills schematic diagram.
Fig. 4 protective layer integrated connection figure.
Specific embodiment
The present invention is directed to the configuration method of traditional top layer metallic layer cabling, has carried out having the evolution and modification stressed, right
It is easy the module of leak data, such as memory module in chip, data/address bus etc. can carry out stressing to protect.
1. top layer protective layer trace configurations method:
Entire wiring layer is divided into multiple wiring areas by the area and degree of protection of the protection according to needed for chip module.
Fig. 1 is a kind of interior layout schematic diagram of chip.Wiring area is divided into several types by the security level of chip internal structure,
In cabling quantity and the security level in region be positively correlated.It can be used snakelike cabling in each wiring area, parallel cabling,
The modes such as random hamiltonian circuit carry out wiring filling.Wherein, the random hamiltonian circuit image degree of disorder is high.Attack can be reduced
Person determines protective layer cabling relationship by means such as image analyses, and decompiling difficulty is greatly improved, to prevent FIB modification protection
Layer is attacked.
2. key area wiring method:
As shown in Fig. 2, the regions of four pieces of different degree of protection is divided into wiring, further according to the internal structure of chip,
Chip module easily breaks through degree, region division is carried out to protective layer, and with A, B, C grade label, to distinguish these regions
Protection level.Wherein, C region security grade is minimum, and B area safety coefficient is medium, a-quadrant safety coefficient highest.Such as Fig. 3 institute
Show, after completing layout, metal routing filling is carried out to the region of various wirings security level.It can will be adjacent and safe etc.
The lower wiring area of grade merges, and carries out unified wiring to these regions, is filled with the metal wire of large area.For compared with
The wiring area of lower security grade can be used less equipotential line and be filled such as the region C in Fig. 3.For compared with high safety
The wiring area of grade such as the B area in Fig. 3 carry out wiring filling using intensive metal wire.To security level highest in Fig. 3
A-quadrant, be routed using complicated random hamiltonian circuit.Another wire laying mode, can be to all areas in Fig. 3
It is all filled using random hamiltonian circuit, but is distinguished on the item number of cabling.In the region C, two random Kazakhstan are used
Close circuit is routed, and for B area in Fig. 3, is routed using three parallel random hamiltonian circuits, in figure
A-quadrant, be routed using four or more random hamiltonian circuits, and its individually designed figure.This method can be with
Very big raising safety coefficient.
3. protective layer connection method:
After the completion of wiring area is planned, top layer regions overall routing figure can be obtained, as shown in Figure 4.Assuming that detection letter
It number transmits from left to right, signal sends the monitoring signals that structure is sent and enters from the several nodes of left margin, passes through each wiring
Metal routing in region, the output port for reaching right margin are connected with detection structure, and carry out pair with the original signal of input
Than can determine whether under attack.If each port persistently has received detection signal, judge not under attack；If
There is one or more signal deletion, region under attack can be judged according to the route of missing.
Before the present invention, the protection level of wiring area area and each region is first planned according to actual chips size,
Top-level metallic shielded layer is divided into several wiring areas.Each routing cell is subjected to cloth further according to the safety coefficient of wiring area
Line is filled, and the cabling quantity in each region is incremented by according to the rising of security level.Signal be will test after the completion from protective layer
The input of left side certain port carry out the output of detection signal completely by wiring layer on right side, detect signal integrity,
It can determine whether to receive attack, and can determine whether the region attacked.
Although invention has been described for the above method, the invention is not limited to above-mentioned specific embodiment, on
The specific embodiment stated is only schematical, rather than restrictive, and those skilled in the art are of the invention
Under enlightenment, many variations can also made without deviating from the spirit of the invention, these input protection of the invention it
It is interior.
Claims (4)
1. the chip top-layer metal protection layer wiring method that a kind of pair of important area reinforces protection, characterized in that first according to practical
Chip size plans the protection level of wiring area area and each region, and top-level metallic shielded layer is divided into several wiring regions
Domain；Each routing cell is subjected to wiring filling further according to the safety coefficient of wiring area, the cabling quantity root in each region
It is incremented by according to the rising of security level；It will test signal after the completion to input from the left side certain port of protective layer, completely pass through
Wiring layer carries out the output of detection signal on right side, detects signal integrity, judge whether to receive attack, and judge to be attacked
Region.
2. reinforcing important area the chip top-layer metal protection layer wiring method of protection, feature as described in claim 1
Be, specifically, top layer protective layer trace configurations method: can be used in each wiring area snakelike cabling, parallel cabling or with
Machine hamiltonian circuit mode carries out wiring filling.
3. reinforcing important area the chip top-layer metal protection layer wiring method of protection, feature as described in claim 1
It is specifically, key area wiring method: wiring to be divided into the region of four pieces of different degree of protection, further according to chip
Internal structure, chip module easily break through degree, region division are carried out to protective layer, and with A, B, C grade label, to distinguish this
The protection level in a little regions；Wherein, C region security grade is minimum, and B area safety coefficient is medium, a-quadrant safety coefficient highest；
After completing layout, metal routing filling is carried out to the region of various wirings security level: adjacent and security level is lower
Wiring area merge, and unified wiring is carried out to these regions, is filled with the metal wire of large area, be filled equal electricity
Gesture line number amount is successively successively decreased from high to low with safety coefficient；For the wiring area B area compared with high safety grade, using intensive
Metal wire carries out wiring filling；To the highest a-quadrant of security level, it is routed using random hamiltonian circuit；Another cloth
Line mode can all be filled all areas using random hamiltonian circuit, but distinguish on the item number of cabling；?
The region C is routed using two random hamiltonian circuits, for B area, using three parallel random hamiltonian circuits into
Row wiring, for a-quadrant, is routed, and its individually designed figure using four or more random hamiltonian circuits.
4. reinforcing important area the chip top-layer metal protection layer wiring method of protection, feature as described in claim 1
It is that specifically, protective layer connection method: signal sends the monitoring signals that structure is sent and enters from the several nodes of left margin, leads to
The metal routing in each wiring area is crossed, the output port for reaching right margin is connected with detection structure, and original with input
Signal compares, that is, can determine whether under attack；If each port persistently has received detection signal, judgement not by
To attack；If there is one or more signal deletion, region under attack is judged according to the route of missing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811165211.5A CN109585419A (en) | 2018-09-30 | 2018-09-30 | Reinforce important area the chip top-layer metal protection layer wiring method of protection |
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| CN201811165211.5A CN109585419A (en) | 2018-09-30 | 2018-09-30 | Reinforce important area the chip top-layer metal protection layer wiring method of protection |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110363032A (en) * | 2019-07-24 | 2019-10-22 | 北京智芯微电子科技有限公司 | The active shield layer circuit of safety chip |
| CN112182667A (en) * | 2020-10-14 | 2021-01-05 | 大唐微电子技术有限公司 | Multilayer metal protection structure, security chip and method for realizing chip protection |
| CN112669544A (en) * | 2020-12-21 | 2021-04-16 | 福建新大陆支付技术有限公司 | Novel safety cover plate wiring method and application thereof |
| CN112733486A (en) * | 2021-01-20 | 2021-04-30 | 河南城建学院 | Intelligent wiring method and system for chip design |
| CN114722767A (en) * | 2022-05-13 | 2022-07-08 | 紫光同芯微电子有限公司 | Method and device for security chip hybrid layout |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080181409A1 (en) * | 2007-01-31 | 2008-07-31 | Zhuqiang Wang | Method for guaranteeing security of critical data, terminal and secured chip |
| CN103646137A (en) * | 2013-12-03 | 2014-03-19 | 北京中电华大电子设计有限责任公司 | Method for designing high-safety chip active shielding physical protection structure |
| CN106227955A (en) * | 2016-07-22 | 2016-12-14 | 天津大学 | A kind of reconstructing method for chip top-layer metal protection layer |
-
2018
- 2018-09-30 CN CN201811165211.5A patent/CN109585419A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080181409A1 (en) * | 2007-01-31 | 2008-07-31 | Zhuqiang Wang | Method for guaranteeing security of critical data, terminal and secured chip |
| CN103646137A (en) * | 2013-12-03 | 2014-03-19 | 北京中电华大电子设计有限责任公司 | Method for designing high-safety chip active shielding physical protection structure |
| CN106227955A (en) * | 2016-07-22 | 2016-12-14 | 天津大学 | A kind of reconstructing method for chip top-layer metal protection layer |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110363032A (en) * | 2019-07-24 | 2019-10-22 | 北京智芯微电子科技有限公司 | The active shield layer circuit of safety chip |
| CN110363032B (en) * | 2019-07-24 | 2021-03-12 | 北京智芯微电子科技有限公司 | Active shielding layer circuit of safety chip |
| CN112182667A (en) * | 2020-10-14 | 2021-01-05 | 大唐微电子技术有限公司 | Multilayer metal protection structure, security chip and method for realizing chip protection |
| CN112669544A (en) * | 2020-12-21 | 2021-04-16 | 福建新大陆支付技术有限公司 | Novel safety cover plate wiring method and application thereof |
| CN112733486A (en) * | 2021-01-20 | 2021-04-30 | 河南城建学院 | Intelligent wiring method and system for chip design |
| CN114722767A (en) * | 2022-05-13 | 2022-07-08 | 紫光同芯微电子有限公司 | Method and device for security chip hybrid layout |
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Application publication date: 20190405 |
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