CN114722767A - Method and device for security chip hybrid layout - Google Patents
Method and device for security chip hybrid layout Download PDFInfo
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- CN114722767A CN114722767A CN202210520681.9A CN202210520681A CN114722767A CN 114722767 A CN114722767 A CN 114722767A CN 202210520681 A CN202210520681 A CN 202210520681A CN 114722767 A CN114722767 A CN 114722767A
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- G06F30/39—Circuit design at the physical level
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- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
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Abstract
The application relates to the technical field of integrated circuit design and discloses a hybrid layout method for a security chip, which comprises the following steps: setting a mixing area for arranging a plurality of cryptographic algorithm modules; each cryptographic algorithm module comprises a plurality of standard units; sequentially arranging each cryptographic algorithm module in the mixing area; wherein, the standard units in each cryptographic algorithm module are uniformly distributed in the mixing area; the blending region boundary is cancelled. The method ensures that the key information of the chip such as the key cannot be easily leaked. The application also discloses a device, electronic equipment and storage medium for the hybrid layout of the security chip.
Description
Technical Field
The present application relates to the field of integrated circuit design technologies, and for example, to a method and an apparatus for secure chip hybrid layout, an electronic device, and a storage medium.
Background
With the rapid development of the internet and information technology, information security topics permeate into various fields of economic and social life, meanwhile, information security problems are increasingly prominent, security events occur frequently, and the demand on security chips is very vigorous particularly in government departments, telecommunication, finance, energy and other industries which have high informatization degree and are sensitive to information.
When the cryptographic algorithm in the chip works, an electromagnetic signal is generated, and automatic layout and wiring design software provided by current chip design manufacturers is used for setting up modules with similar functions in a default manner. The cryptographic algorithm module may suffer from electromagnetic radiation analysis if placed in a cluster, resulting in leakage of key information such as keys.
Disclosure of Invention
The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview nor is intended to identify key/critical elements or to delineate the scope of such embodiments but rather as a prelude to the more detailed description that is presented later.
The embodiment of the disclosure provides a method and a device for hybrid layout of a security chip, an electronic device and a storage device, which can improve the difficulty of electromagnetic radiation analysis and prevent key information such as a secret key of the chip from being easily leaked.
In some embodiments, the method comprises: setting a mixing area for arranging a plurality of cryptographic algorithm modules; each cryptographic algorithm module comprises a plurality of standard units; sequentially arranging each cryptographic algorithm module in the mixing area; wherein, the standard units in each cryptographic algorithm module are uniformly distributed in the mixing area; the blending region boundary is cancelled.
When one of the plurality of cryptographic algorithm modules works independently, the generated noise is relatively dispersed, and the electromagnetic information leakage can be avoided. When a plurality of cryptographic algorithm modules work simultaneously, noise among the cryptographic algorithm modules interferes with each other and is dynamically counteracted, and the purpose of avoiding electromagnetic information leakage is also achieved, so that the electromagnetic radiation analysis difficulty is improved, and key information of a chip cannot be easily leaked.
Optionally, setting a mixing area for laying out a plurality of cryptographic algorithm modules includes: the center of the mixing area is the gravity center of the graph formed by the plurality of cryptographic algorithm modules.
The center of the mixing area is the gravity center of the graph formed by the plurality of cryptographic algorithm modules, so that the mixing area has enough area range and can accommodate all the cryptographic algorithm modules.
Optionally, the standard cells in each cryptographic algorithm module are uniformly arranged in the mixing area in the following manner: respectively setting a corresponding standard unit virtual size for each standard unit in the cryptographic algorithm module; uniformly arranging the virtual sizes of the standard cells in a blank area in the mixed area; all standard cell virtual sizes are deleted within the blending area and all standard cells are retained.
And respectively setting the virtual size of the standard unit for each standard unit in the cryptographic algorithm module, and uniformly inserting the virtual size of the standard unit into the blank area in the mixed area. The standard cells in the cipher algorithm modules can be uniformly distributed in the blank area of the mixing area, and meanwhile, the gaps among the standard cells are reduced. The standard units of different cryptographic algorithm modules are fully mixed in the mixing area, all the space of the mixing area is effectively utilized, and waste of the space is avoided.
Optionally, there is one standard cell within each standard cell virtual dimension.
There is only one standard cell in each virtual dimension, ensuring that each standard cell is well mixed in the mixing region.
Optionally, the virtual size of the standard cell in each cryptographic algorithm module is dynamically set as follows: acquiring a blank area of the mixed area; acquiring the number of standard units and the size of each standard unit in a cryptographic algorithm module; the standard cell virtual size of each standard cell is calculated.
And calculating the virtual size of the standard unit in the cryptographic algorithm module according to the blank area of the mixed area, so that the virtual size can be effectively matched with the blank area of the mixed area, and the waste of the space of the mixed area is avoided.
Optionally, before canceling the boundary of the blending region, the method further includes: and optimally arranging the standard cells by using chip layout software.
After the standard units are arranged in the mixing area, the standard units are optimally arranged through the chip layout software, so that the space can be more reasonably arranged, and other subsequent standard units can fully utilize the space of the mixing area.
Optionally, after the boundary of the blending region is cancelled, the method further includes: and placing the standard units of other functional modules in the space between the standard units.
After the boundary of the mixing area is cancelled, standard units of other functional modules are placed among the standard units of the mixing area, so that the space of the mixing area is fully utilized.
In some embodiments, the apparatus comprises: a processor and a memory storing program instructions, the processor being configured to, upon execution of the program instructions, perform the method for secure chip hybrid layout described above.
In some embodiments, the electronic device comprises: the device for the security chip hybrid layout is described above.
In some embodiments, the storage medium comprises: the program instructions, when executed, perform the above-described method for secure chip hybrid layout.
The foregoing general description and the following description are exemplary and explanatory only and are not restrictive of the application.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the accompanying drawings and not in limitation thereof, in which elements having the same reference numeral designations are shown as like elements and not in limitation thereof, and wherein:
FIG. 1 is a diagram of a default layout of standard cells within a cryptographic algorithm module;
FIG. 2 is a schematic layout diagram of standard cells of each cryptographic algorithm module in a mixing area;
FIG. 3 is a flowchart of a method for secure chip hybrid layout according to an embodiment of the present disclosure;
FIG. 4 is a flowchart of the processing steps of a method for a hybrid layout of a security chip according to an embodiment of the present disclosure;
FIG. 5 is a diagram illustrating a standard cell layout state of a method for hybrid layout of a security chip according to an embodiment of the present disclosure;
fig. 6 is a schematic diagram of an apparatus for a secure chip hybrid layout according to an embodiment of the present disclosure.
Detailed Description
So that the manner in which the features and elements of the disclosed embodiments can be understood in detail, a more particular description of the disclosed embodiments, briefly summarized above, may be had by reference to the embodiments, some of which are illustrated in the appended drawings. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may be practiced without these details. In other instances, well-known structures and devices may be shown in simplified form in order to simplify the drawing.
The terms "first," "second," and the like in the description and in the claims, and the above-described drawings of embodiments of the present disclosure, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the present disclosure described herein may be made. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions.
The term "plurality" means two or more unless otherwise specified.
In the embodiment of the present disclosure, the character "/" indicates that the preceding and following objects are in an or relationship. For example, A/B represents: a or B.
The term "and/or" is an associative relationship that describes objects, meaning that three relationships may exist. For example, a and/or B, represents: a or B, or A and B.
The term "correspond" may refer to an association or binding relationship, and a corresponds to B refers to an association or binding relationship between a and B.
Referring to fig. 1, a schematic diagram of a default layout of standard cells inside a cryptographic algorithm module includes: in the rectangular frame representing the design boundary of the chip, the remaining blank area of the chip except the input/output unit ring and the IP (interactive performance) position is a logic area. The design software defaults to standard cells within an oval area, with standard cells of the same cryptographic algorithm within the same oval area. The standard cells labeled STD-a, STD-b, STD-c are clustered in different ellipses, respectively. Such an arrangement may suffer from electromagnetic radiation analysis, resulting in leakage of critical information such as cryptographic keys.
With reference to fig. 2, a schematic layout diagram of each standard unit of the cryptographic algorithm module in the mixing area includes: and a mixed area with standard units in the logic area of the chip, wherein the mixed area has different standard units of the cryptographic algorithm marked as STD-a, STD-b and STD-c. The STD-a, STD-b and STD-c standard units are cross-mixed with each other and uniformly distributed in the same area. This arrangement allows the noise generated by a cryptographic module to be relatively distributed when operating independently. When a plurality of cryptographic algorithm modules work simultaneously, noise among the cryptographic algorithm modules interferes with each other and is dynamically offset. Therefore, the key information of the chip cannot be easily leaked.
Referring to fig. 3, a main flow chart of a method for a secure chip hybrid layout according to an embodiment of the present disclosure includes:
s01, the cryptographic algorithm arrangement software sets a blending area for laying out a plurality of cryptographic algorithm modules, wherein each cryptographic algorithm module includes a plurality of standard cells.
And S02, arranging the cryptographic algorithm modules in the mixing area in sequence by the cryptographic algorithm arrangement software, wherein the standard cells in each cryptographic algorithm module are uniformly distributed in the mixing area.
S03, the cryptographic algorithm placement software cancels the blending region boundary.
When a plurality of cryptographic algorithm modules are mixed in one region and are uniformly distributed, if one cryptographic algorithm module works independently, the generated noise is relatively dispersed, and electromagnetic information leakage can be avoided. If a plurality of cryptographic algorithm modules work simultaneously, noise among the cryptographic algorithm modules interferes with each other and is dynamically offset, and the purpose of avoiding electromagnetic information leakage is also achieved.
Optionally, in step S01, setting a mixing area for laying out a plurality of cryptographic algorithm modules includes: the center of the mixing area is the gravity center of the graph formed by the plurality of cryptographic algorithm modules.
Thus, the center of the mixing area is the center of gravity of the graph formed by the plurality of cryptographic algorithm modules, and the mixing area can have enough area range so as to accommodate all the cryptographic algorithm modules.
Optionally, in step S02, the standard cells in each cryptographic algorithm module are uniformly arranged in the mixing area as follows: respectively setting a corresponding standard unit virtual size for each standard unit in the cryptographic algorithm module; uniformly arranging the virtual sizes of the standard cells in a blank area in the mixed area; all standard cell virtual sizes are deleted within the blending area and all standard cells are retained.
In this way, the virtual size of the standard unit is set for each standard unit in each cryptographic algorithm module, and the virtual size of the standard unit is uniformly inserted into the blank area in the mixing area. The standard units in the cipher algorithm modules can be uniformly arranged in the blank area of the mixing area, and meanwhile, the gaps among the standard units are reduced. The standard units of different cryptographic algorithm modules are fully mixed in the mixing area, and waste of space is avoided.
Optionally, there is one standard cell in each of the standard cell virtual dimensions.
Thus, only one standard cell is in the virtual size of each standard cell, and each standard cell is guaranteed to be fully mixed in the mixing area.
Optionally, the virtual size of the standard unit in each cryptographic algorithm module is dynamically set as follows: acquiring a blank area of the mixed area; acquiring the number of standard units and the size of each standard unit in a cryptographic algorithm module; the standard cell virtual size of each standard cell is calculated.
Therefore, the virtual size of the standard unit in the cryptographic algorithm module is calculated according to the blank area of the mixed area, so that the virtual size can be effectively matched with the blank area of the mixed area, and the waste of the space of the mixed area is avoided.
Optionally, in step S03, before canceling the blending region boundary, the method further includes: and optimally arranging the standard cells by using chip layout software.
Therefore, after the standard units are arranged in the mixing area, the standard units are optimally arranged through the chip layout software, and the space can be more reasonably arranged.
Optionally, in step S03, after the blended region boundary is cancelled, the method further includes: and placing the standard units of other functional modules in the space between the standard units.
In this way, after the boundary of the mixing area is cancelled, the standard cells of other functional modules are arranged among the standard cells of the mixing area, so that the space of the mixing area is conveniently and fully utilized.
Referring to fig. 4, a flowchart of processing steps of a method for hybrid layout of security chips according to an embodiment of the present disclosure includes:
and S001, calculating the default placing positions of the n cryptographic algorithm modules by using chip layout software.
And S002, calculating the central position and the boundary of the mixing area by the cipher algorithm arrangement software according to the default placement positions of the n cipher algorithm modules.
And S003, judging whether i < n, executing the step S004 if the conditions are met, and otherwise executing the step S009.
S004, the password algorithm arrangement software calculates blank areas of the mixed areas.
And S005, calculating the number of standard units and the size of each standard unit in the ith cryptographic algorithm module by the cryptographic algorithm arrangement software, and calculating the virtual size of each standard unit.
S006, the cryptographic algorithm arrangement software uniformly arranges the standard cell virtual size in the blank in the mixing area.
And S007, deleting the virtual sizes of all the standard cells in the mixed region by the cryptographic algorithm arrangement software, and reserving all the standard cells.
S008, i + +, and re-performs step S003.
And S009, optimally arranging the standard cells by using chip layout software.
And S010, the cipher algorithm arrangement software cancels the boundary of the mixing area.
The standard unit mixed layout of each cryptographic algorithm module is realized through the steps.
Referring to fig. 5, a schematic diagram of a standard cell layout state of a method for hybrid layout of a security chip according to an embodiment of the present disclosure includes:
s10, a virtual size larger than the actual size is set for the actual size of all standard cells in the cryptographic algorithm b.
In this way, it is ensured that the virtual size of the standard cells arranged in the mixing region can fill the entire mixing region uniformly.
S11, arranging the standard cell virtual size in the cryptographic algorithm b in the mixed area.
Thus, since the positions of the standard cells of the cryptographic algorithm a are fixed, they are not moved. The virtual sizes of the standard cells in the cryptographic algorithm module b can be uniformly inserted between the standard cells in the cryptographic algorithm module a.
S12, remove the setting of the virtual size of the standard cell in the cryptographic algorithm b, and fix the standard cell.
In this way, the blank area remaining within the mixed area can be arranged with the subsequent standard cells.
As shown in fig. 6, an apparatus for a secure chip hybrid layout according to an embodiment of the present disclosure includes a processor (processor) 100 and a memory (memory) 101. Optionally, the apparatus may also include a Communication Interface (Communication Interface) 102 and a bus 103. The processor 100, the communication interface 102, and the memory 101 may communicate with each other via a bus 103. The communication interface 102 may be used for information transfer. The processor 100 may call logic instructions in the memory 101 to perform the method for secure chip hybrid layout of the above embodiment.
In addition, the logic instructions in the memory 101 may be implemented in the form of software functional units and stored in a computer readable storage medium when the logic instructions are sold or used as independent products.
The memory 101 is a storage medium and can be used for storing software programs, computer executable programs, such as program instructions/modules corresponding to the methods in the embodiments of the present disclosure. The processor 100 executes functional applications and data processing by executing program instructions/modules stored in the memory 101, i.e., implements the method for secure chip hybrid layout in the above-described embodiments.
The memory 101 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the terminal device, and the like. In addition, the memory 101 may include a high-speed random access memory, and may also include a nonvolatile memory.
The embodiment of the disclosure provides an electronic device, which includes the above device for the hybrid layout of the security chips.
Embodiments of the present disclosure provide a storage medium storing computer-executable instructions configured to perform the above-described method for secure chip hybrid layout.
The storage medium described above may be a transitory computer-readable storage medium or a non-transitory computer-readable storage medium.
The technical solution of the embodiments of the present disclosure may be embodied in the form of a software product, where the computer software product is stored in a storage medium and includes one or more instructions for enabling a computer device (which may be a personal computer, etc.) to execute all or part of the steps of the method of the embodiments of the present disclosure. The storage medium may be a non-transitory storage medium or a transitory storage medium.
The above description and drawings sufficiently illustrate embodiments of the disclosure to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. The examples merely typify possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in or substituted for those of others. Furthermore, the words used in the specification are words of description only and are not intended to limit the claims. As used in the description of the embodiments and the claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Similarly, the term "and/or" as used in this application is meant to encompass any and all possible combinations of one or more of the associated listed. Furthermore, the terms "comprises" and/or "comprising," when used in this application, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Without further limitation, an element defined by the phrase "comprising an …" does not exclude the presence of additional identical elements in the process, method or apparatus comprising the element. In this document, each embodiment may be described with emphasis on differences from other embodiments, and the same and similar parts between the respective embodiments may be referred to each other. For methods, products, etc. of the embodiment disclosures, reference may be made to the description of the method section for relevance if it corresponds to the method section of the embodiment disclosure.
Those of skill in the art would appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software may depend upon the particular application and design constraints imposed on the technical solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments. It can be clearly understood by the skilled person that, for convenience and simplicity of description, the specific working processes of the above-described systems, apparatuses, and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the embodiments disclosed herein, the disclosed methods, products (including but not limited to devices, apparatuses, etc.) may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative.
The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. In the description corresponding to the flowcharts and block diagrams in the figures, operations or steps corresponding to different blocks may also occur in different orders than disclosed in the description, and sometimes there is no specific order between the different operations or steps. For example, two sequential operations or steps may in fact be executed substantially concurrently, or they may sometimes be executed in the reverse order, depending upon the functionality involved. Each block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
Claims (10)
1. A method for secure chip hybrid layout, comprising:
setting a mixing area for arranging a plurality of cryptographic algorithm modules; each cryptographic algorithm module comprises a plurality of standard units;
sequentially arranging each cryptographic algorithm module in the mixing area; wherein, the standard units in each cryptographic algorithm module are uniformly distributed in the mixing area;
the blending region boundary is cancelled.
2. The method of claim 1, wherein providing a mixing area for laying out a plurality of cryptographic algorithm modules comprises:
the center of the mixing area is the gravity center of the graph formed by the plurality of cryptographic algorithm modules.
3. The method of claim 1, wherein the standard cells in each cryptographic algorithm module are uniformly arranged in the mixing region as follows:
respectively setting a corresponding standard unit virtual size for each standard unit in the cryptographic algorithm module;
uniformly arranging the virtual sizes of the standard cells in a blank area in the mixed area;
all standard cell virtual sizes are deleted within the blending area and all standard cells are retained.
4. The method of claim 3, wherein there is one standard cell within each standard cell virtual dimension.
5. The method of claim 3, wherein the standard cell virtual size in each cryptographic algorithm module is dynamically set as follows:
acquiring a blank area of the mixed area;
acquiring the number of standard units and the size of each standard unit in a cryptographic algorithm module;
the standard cell virtual size of each standard cell is calculated.
6. The method of any of claims 1 to 5, wherein before canceling the blending region boundary, further comprising: and optimally arranging the standard cells by using chip layout software.
7. The method according to any one of claims 1 to 5, wherein after canceling the blending region boundary, further comprising: and standard units of other functional modules are placed in the spaces among the standard units.
8. An apparatus for secure chip hybrid layout, comprising a processor and a memory storing program instructions, characterized in that the processor is configured to perform the method for secure chip hybrid layout according to any of claims 1 to 7 when executing the program instructions.
9. An electronic device comprising the apparatus for secure chip hybrid layout of claim 8.
10. A storage medium storing program instructions which, when executed, perform a method for secure chip hybrid layout according to any of claims 1 to 7.
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