CN117688899A - Wiring analysis optimizing system based on high-density integrated circuit - Google Patents
Wiring analysis optimizing system based on high-density integrated circuit Download PDFInfo
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Abstract
The invention relates to the technical field of wiring analysis of high-density integrated circuits, which is used for solving the problems of unobvious wiring optimization effect and poor performance of the high-density integrated circuits caused by insufficient resource utilization, unreasonable wiring state, inaccurate wiring optimization regulation scheme in the existing wiring analysis optimization mode of the high-density integrated circuits.
Description
Technical Field
The invention relates to the technical field of wiring analysis of high-density integrated circuits, in particular to a wiring analysis optimizing system based on a high-density integrated circuit.
Background
With the rapid development of electronic information technology, integrated circuits play a vital role in modern electronic devices. Wiring technology in integrated circuits is one of the key elements of circuit implementation.
However, in the existing wiring analysis optimization method for the high-density integrated circuit, the problems of insufficient resource utilization, unreasonable via layout, unclear wiring state, inaccurate wiring optimization regulation scheme and the like exist, and the problems can affect the wiring optimization effect and performance of the high-density integrated circuit.
In order to solve the above-mentioned defect, a technical scheme is provided.
Disclosure of Invention
The invention aims to provide a wiring analysis optimizing system based on a high-density integrated circuit, so as to solve the problems in the background technology;
the aim of the invention can be achieved by the following technical scheme: a wiring analysis optimization system based on a high density integrated circuit, comprising:
the wiring data analysis module is used for analyzing the wiring resource data parameters of the high-density integrated circuit to obtain the wiring resource data parameters of the high-density integrated circuit, wherein the wiring resource data parameters comprise: total wire length value, average wire width value, average wire spacing value, total via number, average pitch value;
the wiring reasonable state analysis module is used for analyzing the wiring reasonable state of the high-density integrated circuit, so as to output the wiring state of the high-density integrated circuit, wherein the wiring state comprises a reasonable wiring state and an unreasonable wiring state, and if the wiring state of the high-density integrated circuit is marked as the unreasonable wiring state, a wiring optimization instruction is triggered;
the wiring optimization analysis module is used for performing simulation optimization on wiring of the high-density integrated circuit based on the received wiring optimization instruction, so as to obtain a wiring optimization regulation scheme of the high-density integrated circuit;
the wiring optimization verification module is used for carrying out simulation verification analysis on the performance running state of the high-density integrated circuit after wiring optimization based on the wiring optimization regulation scheme of the output high-density integrated circuit, so as to output a simulation verification passing signal or a simulation verification failing signal;
the execution terminal is used for executing corresponding operation based on a wiring optimization regulation scheme of the high-density integrated circuit based on the output simulation verification passing signal, so that wiring optimization analysis of the high-density integrated circuit is completed;
and the execution terminal is also used for analyzing physical constraint conditions of the high-density integrated circuit based on the simulation verification failure signal to obtain a regulating width factor corresponding to the wiring optimization regulating scheme of the high-density integrated circuit, and executing corresponding width regulating operation on the wiring optimization regulating scheme of the high-density integrated circuit based on the outputted regulating width factor, thereby completing wiring optimization analysis of the high-density integrated circuit.
Preferably, the analyzing the wiring resource data parameters of the high-density integrated circuit specifically includes the following steps:
by collecting length information of each wire of high density integrated circuit, extracting length value of each wire from length information of each wire, and recording it as cd i Wherein i is denoted as the number of each wire, and i=1, 2,3, … n; summing the length values of all wires in the high-density integrated circuit, and calculating according to the formula:thereby obtaining a total wire length value zcd in the high-density integrated circuit; average calculation is carried out on the length values of all wires in the high-density integrated circuit, and the following formula is adopted:obtaining an average wire length value cd' in the high-density integrated circuit;
by collecting width information of each wire of high density integrated circuit, extracting width value of each wire from the width information of each wire, and recording it as kd i The width values of all wires in the high-density integrated circuit are calculated averagely according to the formula:thereby obtaining an average wire width value kd' in the high-density integrated circuit;
by acquiring the distance between two adjacent wires of the high-density integrated circuit, the distance value between two adjacent wires in the high-density integrated circuit is obtained and is recorded as sv j J represents the number of pitches of two adjacent wires, j=1, 2,3 … n-1; average calculation is carried out on the distance values of all two adjacent wires in the high-density integrated circuit, and the formula is adopted:obtaining an average wire spacing value sv' in the high-density integrated circuit;
the number of through holes between all metal layers in the high-density integrated circuit is summed by collecting the number of through holes between each metal layer in the high-density integrated circuit and marking the positions of the corresponding through holes according to the formula:thereby obtaining the total through hole number zts of the high-density integrated circuit, wherein ts u Denoted as the number of vias corresponding to the U-th metal layer, and U is the number of each metal layer, u=1, 2,3 … U;
based on the positions of the through holes between the metal layers in the high-density integrated circuit, the distance between two adjacent through holes is obtained, so that the hole distance value of the two adjacent through holes in the high-density integrated circuit is obtained and is recorded as hv p Where p represents the number of pitches of two adjacent through holes, and p=1, 2,3 … U-1; and (3) carrying out average calculation on pitch values of all two adjacent through holes in the high-density integrated circuit, and according to the formula:thereby obtaining an average pitch value hv' in the high-density integrated circuit;
and the high-density integrated circuit wiring resource data parameter is formed by the total wire length value, the average wire width value, the average wire spacing value, the total through hole number and the average hole pitch value.
Preferably, the analyzing the reasonable wiring state of the high-density integrated circuit specifically includes:
extracting total wire length values and average wire length values of the high-density integrated circuit from the wiring resource data parameters of the high-density integrated circuit, extracting reference values corresponding to the total wire length values and the average wire length values of the high-density integrated circuit from a database, and marking the reference values as rho 1 and rho 2 respectively;
and substituting the four items of data into a preset data model for calculation and analysis, and according to the formula:calculating a line increase and consumption coefficient lec of the high-density integrated circuit, wherein a1 and a2 are respectively expressed as set weight values, and the line increase and consumption coefficient is used for referring to a data coefficient of which the length of a wire increases data transmission delay and power consumption;
extracting average wire width value and average wire spacing value of the high-density integrated circuit from wiring resource data parameters of the high-density integrated circuit, extracting reference values corresponding to the average wire width value and the average wire spacing value of the high-density integrated circuit from a database, marking the reference values as rho 3 and rho 4 respectively, comprehensively analyzing four items of data, and according to a set data model:thereby calculating a wiring compactness factor cl of the high-density integrated circuit, wherein a3 and a4 are respectively expressed as set weight values;
extracting total through hole number and average pitch value of high-density integrated circuit from wiring resource data parameters of high-density integrated circuit, and then extracting the total through hole number and average pitch value from the total through hole numberExtracting reference values corresponding to the total through hole number and the average pitch value of the high-density integrated circuit from a database, marking the reference values as rho 5 and rho 6 respectively, comprehensively analyzing four items of data, and according to a set data model:thereby calculating a via layout coefficient phc of the high-density integrated circuit, wherein a5 and a6 are respectively expressed as set weight values;
based on the output line increase and delay coefficient, wiring compact coefficient and through hole layout coefficient phc, comprehensively analyzing the three items of data, and according to a set data model: wrs =y1×lec+y2×cl+y3× phc, thereby obtaining a wiring resource integrated coefficient wrs of the high-density integrated circuit, wherein y1, y2, y3 are respectively expressed as normalization factors;
setting a wiring resource comparison threshold value of the wiring resource comprehensive coefficient of the high-density integrated circuit, comparing and analyzing the wiring resource comprehensive coefficient of the high-density integrated circuit with a preset wiring resource comparison threshold value, marking the wiring state of the high-density integrated circuit as a reasonable wiring state if the wiring resource comprehensive coefficient is smaller than the preset wiring resource comparison threshold value, otherwise marking the wiring state of the high-density integrated circuit as an unreasonable wiring state if the wiring resource comprehensive coefficient is larger than or equal to the preset wiring resource comparison threshold value, and triggering a wiring optimization instruction.
Preferably, the wiring of the high-density integrated circuit is subjected to simulation optimization, and the specific simulation optimization process is as follows:
obtaining a wiring resource comprehensive coefficient of the high-density integrated circuit according to the output wiring optimization instruction, and performing difference calculation on the wiring resource comprehensive coefficient of the high-density integrated circuit and a corresponding reference wiring resource threshold value, thereby obtaining a wiring deviation value of the high-density integrated circuit;
comparing and matching the wiring deviation value of the density integrated circuit with a wiring optimization judging table stored in a database, thereby obtaining a wiring optimization regulating scheme of the high-density integrated circuit, wherein each wiring deviation value corresponds to one wiring optimization regulating scheme, and the content of wiring optimization regulating parameters comprises a through hole regulating rule, a line width regulating rule, a wiring hierarchy rule and a tabu region rule;
the through hole regulation rule specifies the layout rule of the through holes, the distance between the through holes and the wires and the size of the through holes, the line width regulation rule specifies the minimum line width and the line distance, the wire layering rule specifies the rule of stacking wires and the connection rule of inner layer wires and outer layer wires, and the tabu region rule specifies that the wires are prohibited to be carried out in the tabu region.
Preferably, the performance operation state of the high-density integrated circuit after the wiring optimization is subjected to simulation verification analysis, and the specific simulation verification analysis mode is as follows:
the length, bending length and branch number of a straight line segment in a wiring path of an analog signal in high-density integrated circuit wiring are obtained through an electromagnetic simulation tool, the transmission quality czl of the analog signal is calculated according to the formula: czl = c1 ++1 (|l1-l0|+1) - (c2×l2+c3×fz), where L1 represents the straight line segment length of the analog signal in the trace path, L0 represents the reference value of the straight line segment length of the analog signal in the trace path, L2 represents the curved length of the analog signal in the trace path, FZ represents the number of branches of the analog signal in the trace path, and c1, c2, c3 are respectively represented as weight values;
the propagation speed, path length and medium characteristics of the analog signal in the high-density integrated circuit wiring are obtained through an electromagnetic simulation tool, the transmission delay cy of the analog signal is calculated according to the formula: cy= (c5×pl)/(c4×pv) +c6×mc, where pv is denoted as the propagation speed of the analog signal, pl is denoted as the path length of the analog signal, mc is denoted as the medium characteristic of the analog signal, and c4, c5, c6 are respectively denoted as weight values;
the rising time, the falling time and the noise interference times of the analog signals in the high-density integrated circuit wiring are obtained through an electromagnetic simulation tool, the signal loss value sfv of the analog signals is calculated according to the formula: sfv =c7×ut+c8×dt+c9×gr, where ut denotes a rise time of the analog signal, dt denotes a fall time of the analog signal, gr denotes the number of noise disturbances of the analog signal, and c7, c8, and c9 denote weight values, respectively;
based on the transmission quality czl of the output analog signals, the transmission delay cy of the analog signals and the signal loss value sfv of the analog signals, the three data are comprehensively analyzed, and according to a set data model:obtaining an analog optimization evaluation index sov of the high-density integrated circuit, wherein λ1, λ2 and λ3 are respectively represented as weight values, and e is a constant;
setting a simulation optimization evaluation threshold of a simulation optimization evaluation index of the high-density integrated circuit, comparing and analyzing the simulation optimization evaluation index with a preset simulation optimization evaluation threshold, outputting a simulation verification passing signal if the simulation optimization evaluation index is larger than or equal to the preset simulation optimization evaluation threshold, otherwise, outputting a simulation verification failing signal.
Preferably, the physical constraint condition of the high-density integrated circuit is analyzed, and the specific analysis process is as follows:
the size of each chip in the high-density integrated circuit is obtained based on the output analog verification fail signal and marked as cc g Wherein G represents the number of each chip, g=1, 2,3 … G, and the average value of the sizes of all chips in the high-density integrated circuit is calculated according to the set formulaThereby obtaining an average size cc' of the chip of the high-density integrated circuit;
dividing the high-density integrated circuit into F regions in equal amount per unit area, and obtaining the number of devices contained in each region of the high-density integrated circuit and recording it as sl f Wherein F is expressed as the number of the divided regions, and f=1, 2,3, … F, and the number of devices contained in the F regions is subjected to average calculation according to a set formulaDevices thereby obtaining high density integrated circuitsThe arrangement density value sl';
the average size and the arrangement density value of the chips of the high-density integrated circuit form physical layout constraint condition parameters of the high-density integrated circuit;
based on physical layout constraint condition parameters of the high-density integrated circuit, comprehensive analysis is performed, and according to a set data model: pav=b1×cc '+b2×sl', thereby obtaining physical constraint impact values pav of the high-density integrated circuit, wherein b1 and b2 are respectively expressed as normalization factors;
comparing and matching the physical constraint influence value of the high-density integrated circuit with a physical constraint state judgment table stored in a database, thereby obtaining physical constraint influence levels of the high-density integrated circuit, wherein each physical constraint influence value corresponds to one physical constraint influence level, and the physical constraint influence levels comprise a primary physical constraint influence level, a secondary physical constraint influence level and a tertiary physical constraint influence level, and the physical constraint influence levels are based on the output physical constraint influence levels, so that the corresponding regulation width factors are matched with a wiring optimization regulation scheme of the high-density integrated circuit;
based on the output regulating width factor, when the executing terminal executes a wiring optimization regulating scheme on the high-density integrated circuit, the executing terminal executes corresponding width regulating operation according to the regulating width factor, so that wiring optimization analysis of the high-density integrated circuit is completed.
The invention has the beneficial effects that:
the invention can comprehensively and accurately acquire the length, width, interval and other information of the wires by analyzing the wiring resource data parameters of the high-density integrated circuit, thereby providing a sufficient data basis for subsequent analysis and optimization.
The invention analyzes the reasonable wiring state of the high-density integrated circuit, and judges the rationality of the wiring state by calculating the wire increase and delay coefficient, the wiring compact coefficient and the through hole layout coefficient and triggers the wiring optimization instruction, thereby realizing the automatic evaluation and regulation of the wiring state.
According to the wiring resource comprehensive coefficient and the reference wiring resource threshold value, the wiring deviation value is calculated, and a wiring optimization regulation scheme is formulated according to the wiring deviation value, wherein the wiring optimization regulation scheme comprises a through hole regulation rule, a line width regulation rule, a wiring hierarchy rule and a tabu region rule, so that the fine optimization of wiring is realized.
According to the invention, the performance running state of the optimized high-density integrated circuit is subjected to simulation verification analysis, the transmission quality, the transmission delay and the signal loss value of the simulation signal are calculated, and the simulation optimization evaluation index is obtained through comprehensive analysis, so that objective evaluation and verification of the wiring optimization effect are realized.
According to the invention, through analysis of physical constraint conditions, the system can acquire the chip size and the device arrangement density value of the high-density integrated circuit, so that a physical constraint influence value is obtained, and then the corresponding physical constraint influence level and the corresponding regulation width factor are matched, so that the intelligent matching and execution of the wiring optimization regulation scheme are realized.
In summary, the invention improves the analysis precision and the optimization efficiency of the wiring of the high-density integrated circuit, realizes the automatic evaluation and the regulation of the wiring state, and the simulation verification of the performance state and the intelligent optimization of the physical constraint condition, thereby being beneficial to improving the performance and the stability of the high-density integrated circuit.
Drawings
The invention is further described below with reference to the accompanying drawings.
Fig. 1 is a system block diagram of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, the present invention is a wiring analysis optimizing system based on a high-density integrated circuit, comprising: the system comprises a wiring data analysis module, a wiring reasonable state analysis module, a wiring optimization verification module, an execution terminal and a database.
The wiring data analysis module is used for analyzing wiring resource data parameters of the high-density integrated circuit, and the specific analysis process is as follows:
by collecting length information of each wire of high density integrated circuit, extracting length value of each wire from length information of each wire, and recording it as cd i Wherein i is denoted as the number of each wire, and i=1, 2,3, … n; n is a positive integer; summing the length values of all wires in the high-density integrated circuit, and calculating according to the formula:thereby obtaining a total wire length value zcd in the high-density integrated circuit; average calculation is carried out on the length values of all wires in the high-density integrated circuit, and the following formula is adopted: />Obtaining an average wire length value cd' in the high-density integrated circuit;
by collecting width information of each wire of high density integrated circuit, extracting width value of each wire from the width information of each wire, and recording it as kd i The width values of all wires in the high-density integrated circuit are calculated averagely according to the formula:thereby obtaining an average wire width value kd' in the high-density integrated circuit;
by acquiring the distance between two adjacent wires of the high-density integrated circuit, the distance value between two adjacent wires in the high-density integrated circuit is obtained and is recorded as sv j J represents the number of pitches of two adjacent wires, j=1, 2,3 … n-1; average calculation is carried out on the distance values of all two adjacent wires in the high-density integrated circuit, and the formula is adopted:obtaining an average wire spacing value sv' in the high-density integrated circuit;
the number of through holes between all metal layers in the high-density integrated circuit is summed by collecting the number of through holes between each metal layer in the high-density integrated circuit and marking the positions of the corresponding through holes according to the formula:thereby obtaining the total through hole number zts of the high-density integrated circuit, wherein ts u Denoted as the number of vias corresponding to the U-th metal layer, and U is the number of each metal layer, u=1, 2,3 … U; u is the total number of the number between each metal layer, and the value is a positive integer;
based on the positions of the through holes between the metal layers in the high-density integrated circuit, the distance between two adjacent through holes is obtained, so that the hole distance value of the two adjacent through holes in the high-density integrated circuit is obtained and is recorded as hv p Where p represents the number of pitches of two adjacent through holes, and p=1, 2,3 … U-1; and (3) carrying out average calculation on pitch values of all two adjacent through holes in the high-density integrated circuit, and according to the formula:thereby obtaining an average pitch value hv' in the high-density integrated circuit;
the high-density integrated circuit wiring resource data parameter is formed by the total wire length value, the average wire width value, the average wire spacing value, the total through hole number and the average hole pitch value;
it should be noted that the high-density integrated circuit has a multi-metal layer structure, and a plurality of through holes are disposed between the multi-metal layers, wherein the through holes are used for signal transmission and connection elements between different layers.
The wiring reasonable state analysis module is used for analyzing the wiring reasonable state of the high-density integrated circuit, and the specific analysis mode is as follows:
extracting total wire length values and average wire length values of the high-density integrated circuit from the wiring resource data parameters of the high-density integrated circuit, extracting reference values corresponding to the total wire length values and the average wire length values of the high-density integrated circuit from a database, and marking the reference values as rho 1 and rho 2 respectively;
and substituting the four items of data into a preset data model for calculation and analysis, and according to the formula:calculating a line increase and consumption coefficient lec of the high-density integrated circuit, wherein a1 and a2 are respectively expressed as set weight values, and the line increase and consumption coefficient is used for referring to a data coefficient of which the length of a wire increases data transmission delay and power consumption;
extracting average wire width value and average wire spacing value of the high-density integrated circuit from wiring resource data parameters of the high-density integrated circuit, extracting reference values corresponding to the average wire width value and the average wire spacing value of the high-density integrated circuit from a database, marking the reference values as rho 3 and rho 4 respectively, comprehensively analyzing four items of data, and according to a set data model:thereby calculating a wiring compactness factor cl of the high-density integrated circuit, wherein a3 and a4 are respectively expressed as set weight values;
extracting total through hole number and average hole pitch value of the high-density integrated circuit from wiring resource data parameters of the high-density integrated circuit, extracting reference values corresponding to the total through hole number and the average hole pitch value of the high-density integrated circuit from a database, marking the reference values as rho 5 and rho 6 respectively, comprehensively analyzing four items of data, and according to a set data model:thereby calculating a via layout coefficient phc of the high-density integrated circuit, wherein a5 and a6 are respectively expressed as set weight values;
based on the output line increase and delay coefficient, wiring compact coefficient and through hole layout coefficient phc, comprehensively analyzing the three items of data, and according to a set data model: wrs =y1×lec+y2×cl+y3× phc, thereby obtaining a wiring resource integrated coefficient wrs of the high-density integrated circuit, wherein y1, y2, y3 are respectively expressed as normalization factors;
setting a wiring resource comparison threshold value of the wiring resource comprehensive coefficient of the high-density integrated circuit, comparing and analyzing the wiring resource comprehensive coefficient of the high-density integrated circuit with a preset wiring resource comparison threshold value, marking the wiring state of the high-density integrated circuit as a reasonable wiring state if the wiring resource comprehensive coefficient is smaller than the preset wiring resource comparison threshold value, otherwise marking the wiring state of the high-density integrated circuit as an unreasonable wiring state if the wiring resource comprehensive coefficient is larger than or equal to the preset wiring resource comparison threshold value, and triggering a wiring optimization instruction.
The wiring optimization analysis module is used for performing simulation optimization on the wiring of the high-density integrated circuit based on the received wiring optimization instruction, and the specific simulation optimization process is as follows:
obtaining a wiring resource comprehensive coefficient of the high-density integrated circuit according to the output wiring optimization instruction, and performing difference calculation on the wiring resource comprehensive coefficient of the high-density integrated circuit and a corresponding reference wiring resource threshold value, thereby obtaining a wiring deviation value of the high-density integrated circuit;
comparing and matching the wiring deviation value of the density integrated circuit with a wiring optimization judging table stored in a database, thereby obtaining a wiring optimization regulating scheme of the high-density integrated circuit, wherein each wiring deviation value corresponds to one wiring optimization regulating scheme, and the content of wiring optimization regulating parameters comprises a through hole regulating rule, a line width regulating rule, a wiring hierarchy rule and a tabu region rule;
the through hole regulation rule specifies the layout rule of the through holes, the distance between the through holes and the wires and the size of the through holes, the line width regulation rule specifies the minimum line width and the line distance, the wire layering rule specifies the rule of stacking wires and the connection rule of inner layer wires and outer layer wires, and the tabu region rule specifies that the wires are prohibited to be carried out in the tabu region.
The wiring optimization verification module is based on the wiring optimization regulation scheme of the output high-density integrated circuit, and is used for carrying out simulation verification analysis on the performance running state of the high-density integrated circuit after wiring optimization, and the specific simulation verification analysis mode is as follows:
the length, bending length and branch number of a straight line segment in a wiring path of an analog signal in high-density integrated circuit wiring are obtained through an electromagnetic simulation tool, the transmission quality czl of the analog signal is calculated according to the formula: czl = c1 ++1 (|l1-l0|+1) - (c2×l2+c3×fz), where L1 represents the straight line segment length of the analog signal in the trace path, L0 represents the reference value of the straight line segment length of the analog signal in the trace path, L2 represents the curved length of the analog signal in the trace path, FZ represents the number of branches of the analog signal in the trace path, and c1, c2, c3 are respectively represented as weight values;
the propagation speed, path length and medium characteristics of the analog signal in the high-density integrated circuit wiring are obtained through an electromagnetic simulation tool, the transmission delay cy of the analog signal is calculated according to the formula: cy= (c5×pl)/(c4×pv) +c6×mc, where pv is denoted as the propagation speed of the analog signal, pl is denoted as the path length of the analog signal, mc is denoted as the medium characteristic of the analog signal, and c4, c5, c6 are respectively denoted as weight values;
the rising time, the falling time and the noise interference times of the analog signals in the high-density integrated circuit wiring are obtained through an electromagnetic simulation tool, the signal loss value sfv of the analog signals is calculated according to the formula: sfv =c7×ut+c8×dt+c9×gr, where ut denotes a rise time of the analog signal, dt denotes a fall time of the analog signal, gr denotes the number of noise disturbances of the analog signal, and c7, c8, and c9 denote weight values, respectively;
based on the transmission quality czl of the output analog signals, the transmission delay cy of the analog signals and the signal loss value sfv of the analog signals, the three data are comprehensively analyzed, and according to a set data model:obtaining an analog optimization evaluation index sov of the high-density integrated circuit, wherein λ1, λ2 and λ3 are respectively expressed as weight values, and e is a constant and is larger than 1; the specific size of the weight value is matched by the user according to the situationCustom setting of the theory;
setting a simulation optimization evaluation threshold of a simulation optimization evaluation index of the high-density integrated circuit, comparing and analyzing the simulation optimization evaluation index with a preset simulation optimization evaluation threshold, outputting a simulation verification passing signal if the simulation optimization evaluation index is larger than or equal to the preset simulation optimization evaluation threshold, otherwise, outputting a simulation verification failing signal.
The execution terminal is used for executing corresponding operation based on the wiring optimization regulation scheme of the high-density integrated circuit based on the output simulation verification passing signal, thereby completing wiring optimization analysis of the high-density integrated circuit.
The execution terminal is also used for analyzing physical constraint conditions of the high-density integrated circuit based on the simulation verification failure signal, and the specific analysis process is as follows:
the size of each chip in the high-density integrated circuit is obtained based on the output analog verification fail signal and marked as cc g Wherein G represents the number of each chip, g=1, 2,3 … G, G is the total number of the numbers of each chip, and the value is a positive integer; and average value calculation is carried out on the sizes of all chips in the high-density integrated circuit, and a set formula is used for calculating the average valueThereby obtaining an average size cc' of the chip of the high-density integrated circuit;
dividing the high-density integrated circuit into F regions in equal amount per unit area, and obtaining the number of devices contained in each region of the high-density integrated circuit and recording it as sl f Wherein F is expressed as the number of the divided regions, and f=1, 2,3, … F, and the number of devices contained in the F regions is subjected to average calculation according to a set formulaThereby obtaining an arrangement density value sl' of the device of the high-density integrated circuit;
the average size and the arrangement density value of the chips of the high-density integrated circuit form physical layout constraint condition parameters of the high-density integrated circuit;
based on physical layout constraint condition parameters of the high-density integrated circuit, comprehensive analysis is performed, and according to a set data model: pav=b1×cc '+b2×sl', thereby obtaining physical constraint impact values pav of the high-density integrated circuit, wherein b1 and b2 are respectively expressed as normalization factors; the specific size of the normalization factor is set by users according to reasonable user definition of the situation;
comparing and matching the physical constraint influence value of the high-density integrated circuit with a physical constraint state judgment table stored in a database, thereby obtaining physical constraint influence levels of the high-density integrated circuit, wherein each physical constraint influence value corresponds to one physical constraint influence level, and the physical constraint influence levels comprise a primary physical constraint influence level, a secondary physical constraint influence level and a tertiary physical constraint influence level, and the physical constraint influence levels are based on the output physical constraint influence levels, so that the corresponding regulation width factors are matched with a wiring optimization regulation scheme of the high-density integrated circuit;
based on the output regulating width factor, when the executing terminal executes a wiring optimization regulating scheme on the high-density integrated circuit, the executing terminal executes corresponding width regulating operation according to the regulating width factor, so that wiring optimization analysis of the high-density integrated circuit is completed.
The foregoing is merely illustrative of the structures of this invention and various modifications, additions and substitutions for those skilled in the art can be made to the described embodiments without departing from the scope of the invention or from the scope of the invention as defined in the accompanying claims.
Claims (6)
1. A wiring analysis optimization system based on a high density integrated circuit, comprising:
the wiring data analysis module is used for analyzing wiring resource data parameters of the high-density integrated circuit to obtain wiring resource data parameters of the high-density integrated circuit, wherein the wiring resource data parameters comprise a total wire length value, an average wire width value, an average wire spacing value, a total number of through holes and an average hole spacing value;
the wiring reasonable state analysis module is used for analyzing the wiring reasonable state of the high-density integrated circuit, outputting the wiring state of the high-density integrated circuit, and triggering a wiring optimization instruction if the wiring state of the high-density integrated circuit is marked as an unreasonable wiring state;
the wiring optimization analysis module is used for performing simulation optimization on the wiring of the high-density integrated circuit based on the received wiring optimization instruction, so as to obtain a wiring optimization regulation scheme of the high-density integrated circuit;
the wiring optimization verification module is used for carrying out simulation verification analysis on the performance running state of the high-density integrated circuit after wiring optimization based on the wiring optimization regulation scheme of the output high-density integrated circuit, so as to output a simulation verification passing signal or a simulation verification failing signal;
the execution terminal executes corresponding operation based on the output simulation verification passing signal and the wiring optimization regulation scheme based on the high-density integrated circuit; and further based on simulation verification, the signals are not passed and the physical constraint conditions of the high-density integrated circuit are analyzed, the regulating width factors corresponding to the wiring optimization regulating scheme of the high-density integrated circuit are obtained, and the wiring optimization regulating scheme is executed for the high-density integrated circuit to perform corresponding width regulating operation based on the outputted regulating width factors.
2. The wiring analysis optimizing system based on the high-density integrated circuit according to claim 1, wherein the analyzing of the wiring resource data parameters of the high-density integrated circuit is performed by the following specific analyzing process:
acquiring length information of each wire of the high-density integrated circuit, extracting length values of each wire from the length information of each wire, and summing the length values of all wires in the high-density integrated circuit to obtain a total wire length value in the high-density integrated circuit; average calculation is carried out on the length values of all the wires in the high-density integrated circuit, so that the average wire length value in the high-density integrated circuit is obtained;
acquiring width information of each wire of the high-density integrated circuit, extracting width values of each wire from the width information of each wire, and carrying out average calculation on the width values of all wires in the high-density integrated circuit, thereby obtaining average wire width values in the high-density integrated circuit;
acquiring the distance between two adjacent wires of the high-density integrated circuit, thereby obtaining the distance value between the two adjacent wires in the high-density integrated circuit; average calculation is carried out on the distance values of all adjacent two wires in the high-density integrated circuit, so that the average wire distance value in the high-density integrated circuit is obtained;
collecting the number of through holes among all metal layers in the high-density integrated circuit, marking the positions of the corresponding through holes, and summing the number of the through holes among all metal layers in the high-density integrated circuit to obtain the total number of the through holes of the high-density integrated circuit;
acquiring the distance between two adjacent through holes based on the positions of all through holes between all metal layers in the high-density integrated circuit, thereby obtaining the pitch value of the two adjacent through holes in the high-density integrated circuit; average calculation is carried out on pitch values of all two adjacent through holes in the high-density integrated circuit, so that average pitch values in the high-density integrated circuit are obtained;
and the high-density integrated circuit wiring resource data parameter is formed by the total wire length value, the average wire width value, the average wire spacing value, the total through hole number and the average hole pitch value.
3. The wiring analysis optimizing system based on the high-density integrated circuit according to claim 1, wherein the wiring reasonable state of the high-density integrated circuit is analyzed by the following specific analysis modes:
extracting the total wire length value and the average wire length value of the high-density integrated circuit from the wiring resource data parameters of the high-density integrated circuit, and extracting the reference value corresponding to the total wire length value and the average wire length value of the high-density integrated circuit from a database;
substituting the four items of data into a preset data model for calculation and analysis, so as to calculate the linear increase and delay consumption coefficient of the high-density integrated circuit;
extracting an average wire width value and an average wire spacing value of the high-density integrated circuit from the wiring resource data parameters of the high-density integrated circuit, extracting a reference value corresponding to the average wire width value and the average wire spacing value of the high-density integrated circuit from a database, and comprehensively analyzing four items of data to calculate the wiring compactness coefficient of the high-density integrated circuit;
extracting the total number of the through holes and the average pitch value of the high-density integrated circuit from the wiring resource data parameters of the high-density integrated circuit, extracting the reference value corresponding to the total number of the through holes and the average pitch value of the high-density integrated circuit from a database, and comprehensively analyzing four items of data to calculate the through hole layout coefficient of the high-density integrated circuit;
based on the output line increase and delay coefficient, wiring compact coefficient and through hole layout coefficient, comprehensively analyzing the three items of data, thereby obtaining the wiring resource comprehensive coefficient of the high-density integrated circuit;
setting a wiring resource comparison threshold value of the wiring resource comprehensive coefficient of the high-density integrated circuit, comparing and analyzing the wiring resource comprehensive coefficient of the high-density integrated circuit with a preset wiring resource comparison threshold value, marking the wiring state of the high-density integrated circuit as a reasonable wiring state if the wiring resource comprehensive coefficient is smaller than the preset wiring resource comparison threshold value, otherwise marking the wiring state of the high-density integrated circuit as an unreasonable wiring state if the wiring resource comprehensive coefficient is larger than or equal to the preset wiring resource comparison threshold value, and triggering a wiring optimization instruction.
4. The wiring analysis optimizing system based on the high-density integrated circuit according to claim 1, wherein the wiring of the high-density integrated circuit is subjected to simulation optimization, and the specific simulation optimizing process is as follows:
obtaining a wiring resource comprehensive coefficient of the high-density integrated circuit according to the output wiring optimization instruction, and performing difference calculation on the wiring resource comprehensive coefficient of the high-density integrated circuit and a corresponding reference wiring resource threshold value, thereby obtaining a wiring deviation value of the high-density integrated circuit;
comparing and matching the wiring deviation value of the density integrated circuit with a wiring optimization judging table stored in a database, thereby obtaining a wiring optimization regulating scheme of the high-density integrated circuit, wherein each wiring deviation value corresponds to one wiring optimization regulating scheme, and the content of wiring optimization regulating parameters comprises a through hole regulating rule, a line width regulating rule, a wiring hierarchy rule and a tabu region rule;
the through hole regulation rule specifies the layout rule of the through holes, the distance between the through holes and the wires and the size of the through holes, the line width regulation rule specifies the minimum line width and the line distance, the wire layering rule specifies the rule of stacking wires and the connection rule of inner layer wires and outer layer wires, and the tabu region rule specifies that the wires are prohibited to be carried out in the tabu region.
5. The wiring analysis optimizing system based on the high-density integrated circuit according to claim 1, wherein the performance operation state of the high-density integrated circuit after the wiring optimization is subjected to simulation verification analysis, and a specific simulation verification analysis mode is as follows:
the length, bending length and branch number of a straight line segment in a wiring path of an analog signal in high-density integrated circuit wiring are obtained through an electromagnetic simulation tool, the transmission quality czl of the analog signal is calculated according to the formula: czl = c1 ++1 (|l1-l0|+1) - (c2×l2+c3×fz), where L1 represents the straight line segment length of the analog signal in the trace path, L0 represents the reference value of the straight line segment length of the analog signal in the trace path, L2 represents the curved length of the analog signal in the trace path, FZ represents the number of branches of the analog signal in the trace path, and c1, c2, c3 are respectively represented as weight values;
the propagation speed, path length and medium characteristics of the analog signal in the high-density integrated circuit wiring are obtained through an electromagnetic simulation tool, the transmission delay cy of the analog signal is calculated according to the formula: cy= (c5×pl)/(c4×pv) +c6×mc, where pv is denoted as the propagation speed of the analog signal, pl is denoted as the path length of the analog signal, mc is denoted as the medium characteristic of the analog signal, and c4, c5, c6 are respectively denoted as weight values;
the rising time, the falling time and the noise interference times of the analog signals in the high-density integrated circuit wiring are obtained through an electromagnetic simulation tool, the signal loss value sfv of the analog signals is calculated according to the formula: sfv =c7×ut+c8×dt+c9×gr, where ut denotes a rise time of the analog signal, dt denotes a fall time of the analog signal, gr denotes the number of noise disturbances of the analog signal, and c7, c8, and c9 denote weight values, respectively;
based on the transmission quality czl, transmission delay cy and signal loss value sfv of the output analog signal, comprehensively analyzing the three items of data, and according to a set data model:obtaining an analog optimization evaluation index sov of the high-density integrated circuit, wherein λ1, λ2 and λ3 are respectively represented as weight values, and e is a constant;
setting a simulation optimization evaluation threshold of a simulation optimization evaluation index of the high-density integrated circuit, comparing and analyzing the simulation optimization evaluation index with a preset simulation optimization evaluation threshold, outputting a simulation verification passing signal if the simulation optimization evaluation index is larger than or equal to the preset simulation optimization evaluation threshold, otherwise, outputting a simulation verification failing signal.
6. The wiring analysis optimizing system based on the high-density integrated circuit according to claim 1, wherein the physical constraint condition of the high-density integrated circuit is analyzed, and the specific analysis process is as follows:
the size of each chip in the high-density integrated circuit is obtained based on the output analog verification fail signal and marked as cc g Wherein g represents each chipThe average size cc' of the chips of the high-density integrated circuit is obtained by carrying out average calculation on the sizes of all the chips in the high-density integrated circuit;
dividing the high-density integrated circuit into F regions in equal amount per unit area, and obtaining the number of devices contained in each region of the high-density integrated circuit and recording it as sl f Wherein F is the number of the divided areas, and the number of the devices contained in the F areas is subjected to average calculation to obtain an arrangement density value sl' of the devices of the high-density integrated circuit;
the average size and the arrangement density value of the chips of the high-density integrated circuit form physical layout constraint condition parameters of the high-density integrated circuit;
according to the set data model: pav=b1×cc '+b2×sl' to obtain a physical constraint impact value pav of the high-density integrated circuit, where b1 and b2 are respectively expressed as normalization factors;
comparing and matching the physical constraint influence value of the high-density integrated circuit with a physical constraint state judgment table stored in a database, thereby obtaining physical constraint influence levels of the high-density integrated circuit, wherein each physical constraint influence value corresponds to one physical constraint influence level, and the physical constraint influence levels comprise a primary physical constraint influence level, a secondary physical constraint influence level and a tertiary physical constraint influence level, and the physical constraint influence levels are based on the output physical constraint influence levels, so that the corresponding regulation width factors are matched with a wiring optimization regulation scheme of the high-density integrated circuit;
based on the output regulating width factor, when the executing terminal executes a wiring optimization regulating scheme on the high-density integrated circuit, the executing terminal executes corresponding width regulating operation according to the regulating width factor, so that wiring optimization analysis of the high-density integrated circuit is completed.
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