CN116341480A

CN116341480A - Global optimization method and system for digital chip layout and wiring

Info

Publication number: CN116341480A
Application number: CN202310617060.7A
Authority: CN
Inventors: 吕志鹏; 苏宙行
Original assignee: Huazhong University of Science and Technology
Current assignee: Huazhong University of Science and Technology
Priority date: 2023-05-29
Filing date: 2023-05-29
Publication date: 2023-06-27
Anticipated expiration: 2043-05-29
Also published as: CN116341480B

Abstract

The invention discloses a global optimization method and a global optimization system for digital chip layout and wiring, wherein the method comprises the following steps: abstract modeling is carried out on the three-dimensional chip layout wiring problem, and basic mathematical models of layout sub-problems and wiring sub-problems are respectively established; carrying out local search by adopting a secondary assignment algorithm, and solving the initial layout of standard elements in each unit to obtain a relaxation solution of a layout sub-problem; adjusting the initial layout through a tabu search algorithm and neighborhood actions based on unit exchange to generate a global layout, and obtaining legal solutions of layout sub-problems; performing global wiring by iteratively calling a single-network wiring algorithm to generate a Steiner forest relaxation solution, and re-wiring or adjusting and repairing a network violating constraint to obtain an initial layout wiring solution; and carrying out multi-layer joint optimization on the layout wiring problem on the basis of the initial layout wiring solution to obtain an optimal layout wiring solution. The invention realizes the joint optimization of the layout and the wiring, and can improve the accuracy of the layout and the wiring.

Description

Global optimization method and system for digital chip layout and wiring

Technical Field

The invention belongs to the technical field of digital chips, and particularly relates to a global optimization method and system for digital chip layout and wiring.

Background

With the increasing fineness of chip technology, the process is gradually developed to 3nm, the physical size almost reaches the limit, and the development of the process is being slowed down. Chip developers have difficulty relying on smaller transistors to increase the density and speed of the chip. Moore's law encounters a bottleneck in development, but the market demand for chip performance is increasing. If the wafer size is continuously increased, the number of transistors is increased, but the signal delay in the chip is increased and the yield is reduced. In recent years, with the advance of advanced processes and advanced packaging, chips are moving from two dimensions to three dimensions, i.e., the links of design, manufacture, packaging, etc. are moving toward three-dimensional structures.

While three-dimensional chips offer many benefits and opportunities, new challenges are presented to be addressed. Three-dimensional chips are not just stacks of multiple two-dimensional chips, but rather require systematic design. Three-dimensional integrated circuits provide additional degrees of freedom for circuit design, with the increase in decision complexity from two-dimensional to three-dimensional being exponential. The optimization goals of traditional power consumption, performance and area (PPA) remain applicable, but become optimization in three-dimensional space rather than two-dimensional planes, and the vertical dimension must be considered in all trade-off decisions.

The back-end design of the chip converts the gate level netlist into a physical layout usable for manufacturing in a foundry of the chip. In back-end physical design, all macro blocks, cells, gates, transistors, etc., are represented with a fixed shape and size on each fabrication level, and spatial locations (layouts) are allocated on the silicon substrate, and then appropriate connection relationships (routing) are determined. Meanwhile, once the front-end design is modified, the back-end design needs to be regenerated. Therefore, the layout and wiring links occupy important positions in the back-end physical design, and directly influence the performance, area, power consumption and other performance indexes of the chip.

In the face of the problem of layout and wiring of three-dimensional chips under advanced technology, the traditional EDA physical design methodology is difficult to adapt to the physical design requirement of the chips under advanced technology, and the main problems are as follows:

(1) The mainstream EDA tool does not consider a plurality of rules and constraints under advanced technology, has insufficient abstraction degree on the problem, and is difficult to directly use the existing EDA tool and research results of academia aiming at classical problems. The existing EDA layout wiring method is mainly oriented to two-dimensional chip design, and the considered problem is greatly different from the physical design requirement of the three-dimensional chip under the advanced process. Therefore, the modeling layer is required to directly face to the three-dimensional chip design under the advanced process for modeling, and many rules, constraints and optimization targets under the new process are considered. On the other hand, the combination optimization problem considered in the academic world does not consider various constraints and rules under the actual process conditions, and the abundant research results are difficult to be directly applied to the physical design of the three-dimensional chip.

(2) The mainstream EDA tool handles the layout and wiring links as two independent links, the feedback process is lengthy and heavily relies on manual intervention. The existing chip design is based on the EDA technology of multi-step repeated iteration to comprehensively optimize performance, area, power consumption and the like, the layout and wiring links are relatively independent, and the layout result is finally reflected to the wiring and needs to be subjected to long iteration and feedback. The process of feedback and modification of the layout is typically done manually by experienced engineers.

(3) The simplified consideration of the wiring in the layout stage results in that its optimization objective does not reflect the true goodness, and the layout links may be struggling in the wrong direction. The staged design in conventional EDA flow makes the design information redundant and isolated and eliminates the possibility of using some critical information to guide the design process. In fact, there is no obvious limit between two links of layout and wiring, the two links complement each other, and an inaccurate estimation model of the wire length in the layout stage may cause poor wiring goodness or even a problem of incapability of wiring, and a global optimization algorithm for comprehensively considering the layout and the wiring is lacking.

In the prior art, there is also few effective solutions about the comprehensive problem of the layout and wiring of the three-dimensional chip, for example, the invention patent with publication number CN113673196a discloses a global wiring optimization method based on routability prediction, which performs global wiring optimization after directly obtaining global layout results, and does not comprehensively consider the layout and wiring problems, so as to affect the final layout and wiring effect. Therefore, a comprehensive optimization method for layout and wiring of a three-dimensional chip is needed to realize a more efficient and high-quality three-dimensional chip layout generation mode.

Disclosure of Invention

In view of this, the invention provides a global optimization method and system for layout and wiring of a digital chip, which are used for solving the problem that the existing EDA technology does not comprehensively consider global optimization of layout and wiring.

The invention discloses a global optimization method for digital chip layout and wiring, which comprises the following steps:

carrying out abstract modeling on the three-dimensional chip layout wiring problem, and respectively establishing a basic mathematical model of a layout sub-problem and a basic mathematical model of a wiring sub-problem;

performing unit recursion division according to the netlist structure of the standard element, performing linear relaxation on constraint conditions of the layout sub-problem, performing local search by adopting a secondary assignment algorithm, and solving the initial layout of the standard element in each unit to obtain a relaxation solution of the layout sub-problem;

abstracting each level of layout sub-problem into a two-dimensional boxing problem, dividing the layout space of each level into areas, adjusting the initial layout through a tabu search algorithm and neighborhood actions based on unit exchange, generating a global layout, and obtaining legal solutions of the layout sub-problems;

based on global layout, relaxing constraint conditions of wiring sub-problems, carrying out global wiring by iteratively calling a single-network wiring algorithm, generating a Steiner forest relaxation solution, and carrying out rewiring or adjustment repair on a network violating the constraint to obtain an initial layout wiring solution;

And on the basis of the initial layout wiring solution, carrying out multi-layer joint optimization on the layout wiring problem, and iteratively and alternately adjusting the layout and optimizing the wiring length from the overall pattern to obtain the optimal layout wiring solution.

On the basis of the above technical solution, preferably, performing unit recursion division according to the netlist structure of the standard element, performing linear relaxation on constraint conditions of the layout sub-problem, performing local search by adopting a secondary assignment algorithm, and solving an initial layout of the standard element in each unit, where obtaining a relaxation solution of the layout sub-problem specifically includes:

constructing a standard element relation diagram according to the network where the standard element is located and the time sequence constraint relation, and recursively dividing each functional unit according to the standard element relation diagram until a set threshold is met to obtain a plurality of subsets;

and (3) carrying out linear relaxation on constraint conditions of a basic mathematical model of the layout sub-problem, carrying out local search on unit set division by adopting a heuristic secondary assignment algorithm to obtain a relaxation solution of the layout sub-problem, and evaluating the feasibility of the relaxation solution by taking the half perimeter and the density of the net as quality evaluation basis to take the feasible relaxation solution as an initial layout.

On the basis of the above technical solution, preferably, the performing region division on the layout space of each level, and adjusting the initial layout through a tabu search algorithm and domain actions based on unit exchange, the generating the global layout specifically includes:

based on the initial layout, equally dividing the layout space into a plurality of areas;

analyzing each area, and selecting potential exchange area pairs;

performing domain actions based on unit exchange on the candidate areas based on the potential exchange areas, and performing exchange effect evaluation;

judging whether the current iteration obtains an optimal neighbor solution, if not, updating selection parameters of a tabu table and a region exchange pair, reselecting a potential exchange region pair and carrying out iterative operation until obtaining the optimal neighbor solution;

and if the current iteration obtains the optimal neighbor solution and the optimal solution method is adopted, outputting the global layout.

On the basis of the above technical solution, preferably, the factors for analyzing each region and selecting potential exchange region pairs include whether the region is in a tabu table, the layout goodness of the region, the frequency of region selection and the unit distribution condition in the region;

taking the size of the unit and the fitness of the unit in the area into consideration when performing domain actions based on unit exchange, wherein the fitness is evaluated by the strength of the connection between the unit and other units in the corresponding area and the influence on area congestion;

The strength of the connection between the units is measured based on a half perimeter calculation formula of the following formula network:

wherein

Representing the units +.>

Placed in the region->

After that, the total half perimeter of all nets connected to the unit,/->

Representation unit->

The abscissa of the center of the region, +.>

Representing the units +.>

Placed in the region->

，/>

Representation and->

Maximum abscissa of the area center of all units of the net-related, +.>

Minimum value of abscissa, +.>

Maximum value of ordinate and +.>

Longitudinal sittingA target minimum value;

the impact of regional congestion is evaluated using the following formula:

wherein

Representation area->

Is a free area sub-block, +.>

Representation area->

Area of->

The parameters are normalized for values.

On the basis of the above technical solution, preferably, the step of performing global routing by iteratively invoking a single-network routing algorithm to generate a stanner forest relaxation solution, and performing rewiring or adjustment repair on a network violating constraints to obtain an initial layout routing solution specifically includes:

when global wiring is carried out by iteratively calling a single-network wiring algorithm, adopting a mode of combining the optimal two-dimensional mode wiring of a dynamic shortest-path wiring algorithm, and carrying out detour optimization on the wiring by loosening capacity constraint through a grid congestion sensing method to generate a Steiner forest loosening solution;

Relaxing grid capacity upper limit constraints and using congestion weights

Representing the extra cost of the network passing through the capacity overflow grid, and carrying out capacity overflow grid +_ on the network violating constraint by adopting a grid congestion weight self-adaptive adjustment mode>

Is applied to the conflict repair of the corresponding mesh by adopting a single mesh wiring algorithm>

Repeating the repair process until all capacity overflow grids are repaired and returning to a feasible wiring scheme;

an initial place-and-route solution is generated based on the global placement and the feasible routing scheme.

On the basis of the above technical solution, preferably, the routing optimization by relaxing capacity constraint through a grid congestion sensing method specifically includes:

translating capacity constraints in wiring problems into congestion assessment of remaining capacity of a grid, using

Representing grid->

Spill capacity of (2) and use ∈>

Metric grid +.>

Congestion level, ∈mesh>

Redefined as the following formula:

wherein ,

for wiring via a grid->

Original cost of->

To consider the wiring cost of the congestion degree, the wiring cost is +.>

The minimum is the goal for wire optimization.

On the basis of the above technical solution, preferably, the performing multi-layer joint optimization on the layout wiring problem on the basis of the initial layout wiring solution specifically includes:

Performing cell position exchange movement based on the initial layout wiring solution, and performing cell movement evaluation;

carrying out layout legalization on a new layout generated along with the exchange and movement of the cell positions;

rewiring the moved cell-related network;

global optimization is carried out on wiring problems;

and (5) carrying out iterative operation until the optimal layout wiring solution is obtained.

On the basis of the above technical solution, preferably, the performing unit movement evaluation specifically includes:

each iteration will unit

Move to layout area->

And to keep the position of the other units unchanged and to satisfy the region +.>

On the premise of capacity constraint of all grids, find the best movement action +.>

To minimize the estimated wire length;

searching for unit candidate placement areas with potential for improvement using coarse-grained evaluation of mesh-based half-perimeter

In the area->

Fine granularity evaluation based on a straight-line Steiner tree is performed internally, and an optimal target position is calculated>

；

The coarse-grained evaluation search with half-perimeter based on mesh has potential for improved placement of unit candidates

The method specifically comprises the following steps: is provided with->

Representing the connection to the unit->

Coarse-grained evaluation is aimed at +.>

Find a candidate region +. >

To minimize the aggregate->

The total half-perimeter wire length of all wire nets;

the at-region

Fine granularity evaluation based on a straight-line Steiner tree is performed in the method, and the optimal target position is found>

The method specifically comprises the following steps:

is provided with

Expressed in the current layout->

Lower net->

Is a result of the fine evaluation of the line length of (2), move +.>

The layout after doing is->

，/>

Expressed in layout->

Lower net->

Line length results of fine evaluation of (a) then for the cell

Candidate region +.>

Is +.>

Movement motion->

The profit calculation formula of (2) is as follows:

representing the units +.>

Move to position->

Decrease in posterior line length to +.>

Minimum calculating the optimal target position for the target +.>

。

In a second aspect of the present invention, a global optimization system for digital chip layout and routing is disclosed, the system comprising:

mathematical modeling module: the method comprises the steps of carrying out abstract modeling on a three-dimensional chip layout wiring problem, and respectively establishing a basic mathematical model of a layout sub-problem and a basic mathematical model of a wiring sub-problem;

an initial layout module: the method comprises the steps of performing unit recursion division according to a netlist structure of standard elements, performing linear relaxation on constraint conditions of a layout sub-problem, performing local search by adopting a secondary assignment algorithm, and solving an initial layout of the standard elements in each unit to obtain a relaxation solution of the layout sub-problem;

A global layout module: the method comprises the steps of abstracting each level of layout sub-problem into a two-dimensional boxing problem, dividing each level of layout space into areas, adjusting an initial layout through a tabu search algorithm and neighborhood actions based on unit exchange, generating a global layout, and obtaining legal solutions of the layout sub-problems;

global wiring module: the method comprises the steps of relaxing constraint conditions of wiring sub-problems based on global layout, carrying out global wiring by iteratively calling a single-network wiring algorithm, generating a Steiner forest relaxation solution, and carrying out rewiring or adjustment repair on a network violating the constraint to obtain an initial layout wiring solution;

and a joint optimization module: the method is used for carrying out multilayer joint optimization on the layout and wiring problems on the basis of the initial layout and wiring solution, and iteratively and alternately adjusting the layout and optimizing the wiring length from the overall pattern to obtain the optimal layout and wiring solution.

Compared with the prior art, the invention has the following beneficial effects:

1) The invention carries out abstract modeling on the three-dimensional chip layout wiring problem, carries out unit recursion division and local search by adopting a secondary assignment algorithm to obtain an initial layout, adjusts the initial layout by adopting a tabu search algorithm and neighborhood actions based on unit exchange to generate a global layout, carries out global wiring optimization based on the global layout, and finally carries out multilayer joint optimization on the layout wiring problem to obtain an optimal layout wiring solution, thereby realizing joint optimization of the layout problem and the wiring problem, improving the quality of the solution of the layout wiring problem and improving the accuracy of the layout wiring;

2) Aiming at the problem that mathematical modeling optimization methods such as linear programming and the like adopted by the traditional initial layout optimization method are prone to being in a local optimal solution, the invention provides a recursion segmentation initial layout generation method based on netlist structure perception, a cell relation topological structure of a netlist is established by abstracting key features such as connection relations among standard elements, time sequence logics and the like, the whole netlist is recursively divided into a plurality of internal strong correlation subsets according to the relation among nodes in the topological structure, and finally, the division result is mapped back to an original circuit netlist, so that high-quality initial layout can be generated, the quality of the initial solution is improved, and the problem of being in the local optimal solution is avoided;

3) According to the invention, an actual wiring condition in wiring optimization is considered, an approximation evaluation algorithm based on a Steiner tree is provided, and when a field action based on unit exchange is performed by combining a half perimeter optimization method in traditional layout optimization, the size of a unit and the adaptability of the unit in a region are considered, and the layout is optimized by adopting a multistage neighborhood evaluation method combining the strength of connection between the unit and other units in the region and the influence on regional congestion, so that the performance and efficiency of a heuristic algorithm in large-scale layout problem optimization are effectively balanced;

4) According to the invention, a dynamic shortest wiring method and a multi-mode wiring method are adopted to simultaneously guide three-dimensional wiring so as to realize overall pattern optimization, wiring is detour optimized by properly relaxing capacity constraint through a grid congestion sensing method, conflict repair of capacity overflow grids is carried out in a grid congestion weight self-adaptive adjustment mode, and grid capacity dynamic change caused by layout wiring is effectively treated;

5) Aiming at the difference and the connection between the layout and wiring problems in the chip design flow, the invention designs a layout and wiring alternate iteration optimization process based on the combination of two-stage interaction and feedback, and compared with the traditional method, the layout optimization process considers more practical wiring requirements, the wiring optimization rapidly feeds back the real congestion condition to the layout stage according to the practical wiring result, and the optimization design of the layout and wiring two-stage alternate iteration can avoid the excessive optimization of a single sub-problem or the excessive conservation during the optimization, thereby ensuring the feasibility of the final result and the overall optimization performance.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a flow chart of the method of the present invention;

FIG. 2 is a flow chart of an initial layout of the present invention;

FIG. 3 is a flow chart of a global layout of the present invention;

FIG. 4 is a diagram of neighborhood actions based on cell swapping;

FIG. 5 is a global routing algorithm overview framework of the present invention;

FIG. 6 is a global routing flow diagram of the present invention;

FIG. 7 is a schematic diagram of an alternate optimization mechanism for placement and routing in accordance with the present invention.

Detailed Description

The following description of the embodiments of the present invention will clearly and fully describe the technical aspects of the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, are intended to fall within the scope of the present invention.

Referring to fig. 1, the invention discloses a global optimization method for digital chip layout and wiring, which comprises the following steps:

s1, carrying out abstract modeling on the three-dimensional chip layout wiring problem, and respectively establishing a basic mathematical model of the layout sub-problem and a basic mathematical model of the wiring sub-problem.

According to the constraint and optimization targets of the physical characteristic analysis problem of the three-dimensional chip layout wiring problem, a layout wiring problem mathematical model which is highly correlated and easy to globally optimize is established.

The mathematical model of the layout wiring problem mainly considers the following elements:

(1) Known information

A unit: the number of barriers, pins and distribution layers in each cell, and the voltage domain to which the cell belongs.

Net: all nodes of each network and their corresponding cells and pins.

Space: the boundary of the chip layout wiring space, the distribution condition of voltage areas in the space, the space capacity of different layers and areas, the wiring cost and the like.

(2) Decision variables

Position of the unit: the position of each cell in space is distributed.

Road section of network: the segments that make up each net, i.e., the mesh through which each net passes.

(3) Optimization objective

Minimizing layout area: and the whole area of the chip is evaluated according to the layout result, and the minimized chip area is beneficial to reducing the production cost.

Minimizing spatial congestion: space congestion is assessed by local component density, and excessive congestion can cause routing difficulties and problems with local overheating of the chip.

Minimizing the sum of half-circumferences of the mesh: this goal may be an auxiliary goal for the layout stage to evaluate the wire length of the net.

Minimizing critical path length: each netlist has several critical paths that are too long to lengthen the clock cycles of the sequential circuits, affecting chip performance.

Minimizing bus length: the weighted wiring cost is minimized, and the target can be used as an optimization target of wiring problems alone or as a global optimization target of layout and wiring.

(4) Constraint conditions

Voltage zone constraints: each cell must be placed in a position that meets its own requirements for the voltage domain.

The components are not overlapped with each other: no overlap between each component can occur.

The wiring does not overlap and does not intersect: the wiring between different nets cannot be overlapped or intersected, otherwise short circuit occurs, and normal functions of the chip are affected.

Connectivity constraints: each net must connect all pins and the interior must be connected, and no disconnection can occur.

Intra-layer wiring direction constraint: due to the requirements of the chip manufacturing process, the direction of the wiring in all layers must be consistent with the direction constraint of the layer in which it is located, and must be horizontal or vertical.

Wiring layer restriction: each net must be routed between its specified layers.

Interlayer wiring direction constraint: when two layers of wires need to be connected, then the wires perpendicular to the two layers need to be used for connection.

Wiring length constraint: each net in the routing scheme has a maximum wire length limit, subject to voltage loss.

Heating balance constraint: components with obvious thermal effects should be distributed in a dispersed manner. In other words, the total heat generation amount of the components in the unit space must not exceed a given threshold.

The principal symbol definitions of the three-dimensional chip layout wiring mathematical model are shown in table 1.

TABLE 1 definition of mathematical model symbols for three-dimensional chip layout

The layout wiring problem mathematical model includes a basic mathematical model of a layout sub-problem and a basic mathematical model of a wiring sub-problem.

For the layout sub-problem, its basic mathematical model is as follows:

wherein equation (1) describes an optimization objective of layout problems, i.e., minimizing the sum of weighted network half-circumferences, in which the actual routing cost of each network is estimated; equation (2) states that each cell must be placed into a unique one of the grids; equations (3) - (4) are capacity constraints for layout problems, the capacity of each grid must meet the obstacles of standard cells on the grid and the capacity requirements of the network; formulas (5) - (6) indicate that standard cells where all pins on a network are located must be placed within the edge of the network. Equation (7) specifies that when the cell in which the pin of the network is located is placed on a grid, the network occupies space on the grid.

For wiring problems, the invention establishes a wiring model based on marked edges. Randomly selecting a node in a network

As root node of the network, the boolean decision variable +.>

Indicating whether the network is meshed->

Boolean decision variable->

Indicating whether the network contains a path->

，/>

Representing grid->

Depth in the network. For the wiring sub-problem, its basic mathematical model is as follows:

wherein equation (8) describes the goal of the routing problem, i.e., minimizing the network weighted line length; formulas (9) - (11) provide that the network root node ingress must be 0, the egress must be 1, and the other nodes in the network ingress must be 1, ensuring that all nodes of all networks are connected; formulas (12) - (13) ensure that the grid output of the network is greater than the grid input, and ensure the integrity of the network; equation (14) specifies that the depth of the node of the network is greater than the depth of the previous node, so as to ensure the correctness of the algorithm; equation (15) ensures that there is only one direction for one edge. All constraint formulas together ensure the integrity and connectivity of the network.

When a layout and wiring problem mathematical model is established, the invention performs unified abstraction on the layout and wiring problem, but keeps the layout and wiring model to have independent optimization targets. The two problems of layout and wiring can be solved in a split way, a high-quality initial solution is provided for the initial stage of the algorithm, and factors such as the line length of the wiring problem, the area in the layout problem, congestion and the like can be considered at the same time, so that the method and the device serve as the target of global optimization and provide good flexibility and foundation for subsequent research.

S2, performing unit recursion division according to the netlist structure of the standard element, performing linear relaxation on constraint conditions of the layout sub-problem, performing local search by adopting a secondary assignment algorithm, and solving the initial layout of the standard element in each unit to obtain a relaxation solution of the layout sub-problem.

The layout link of the chip back-end design can be regarded as a complex boxing problem with multiple constraints and multiple targets. The goal of the layout is to place standard cells into legal positions, the advantages and disadvantages of which have critical effects on the area optimization, the area congestion and the timing closure of the physical design. The invention adopts the idea of secondary assignment and the local searching and linear relaxation technology to solve the global layout problem, and the flow is shown in figure 2.

As shown in fig. 2, step S2 specifically includes the following sub-steps:

s21, unit recursion division based on netlist structure perception

And constructing a standard element relation diagram according to the relation of the network where the standard element is located, time sequence constraint and the like. The units can be divided into a plurality of subsets with stronger internal connection according to the relation diagram, if the subsets are larger and the internal relation is still too complex, the subsets are further divided, and the recursion iterates until the set threshold is met, and finally the size of the space occupied by each subset and the relative position of the space occupied by each subset are determined, so that support is provided for the follow-up global layout.

S22, initial layout generation based on linear relaxation

Based on the constraint relation of the basic mathematical model of the layout sub-problem, the linear relaxation is carried out on the basic mathematical model, and a small amount of overlapping between circuit elements is allowed to occur, so that a relaxation solution is obtained rapidly. After the specific placement position of each cell in its space is obtained, the quality of the relaxation solution is evaluated by calculating the half perimeter of the net, etc. In order to reduce constraint violation of a solution obtained by linear relaxation and enhance repairability of the solution, a heuristic secondary assignment algorithm is adopted to carry out local search on unit set division by taking half perimeter and density of a net as quality evaluation basis. Since estimating the wire length using the half perimeter may make the actual wire length and the half perimeter widely different, it is not possible to provide good guidance for the wire, and thus the routability of the layout is estimated using a fast initial wire during the search. The combination of half perimeter and quick initial wiring evaluation strategy can ensure that a high-quality initial layout which is easy to repair and capable of wiring is obtained, and finally a better repairable relaxation solution is obtained.

S3, abstracting the layout sub-problem of each level into a two-dimensional boxing problem, dividing the layout space of each level into areas, adjusting the initial layout through a tabu search algorithm and neighborhood actions based on unit exchange, generating a global layout, and obtaining legal solutions of the layout sub-problems.

In the layout and wiring problem of the three-dimensional chip, since pins and barriers in the cells are generally fixed at a specific level, when the cells are placed in a specific vertical space, it is not necessary to allocate a layer for the cells, and only whether the cells overlap with other cells at the same level needs to be considered. Therefore, when considering layout legitimization, the pins and the barriers can be distributed in units of different layers to divide, and the layout problem of each layer is abstracted into a two-dimensional boxing problem.

The layout space can be abstracted into a two-dimensional plane, and the complete layout space can be divided into uniform sub-rectangular areas according to the problem scale, wherein each area corresponds to one layout sub-problem. Specifically, in the Iter iteration, the present invention performs an evaluation of the swap actions between all units, actions

Representation area->

Units of->

Area->

Units of->

The exchange is performed. Selecting the best switching action based on the line length evaluation of the switching action and the influence on the congestion of the area +.>

And performs the exchange. If there are multiple optimal actions equivalent to the assessment of congestion, the balance is broken according to the following priorities:

(1) Corresponding region

Layout goodness of (2): the area with poor original layout priority is preferentially operated, and the overall priority can be more balanced after the operation.

(2) Historical selected frequencies: the fewer the number of times the history operation is selected, the more preferred the history operation is-the preferred access to the neighborhood actions performs less area, facilitating exploration of a larger solution space.

(3) Cell distribution conditions of different sizes: the smaller the area of the unit itself participating in the exchange, the more preferred the unit is selected-avoiding that the larger area of the operating unit causes larger damage to the better layout result.

In addition, the selected exchange pair

Should not be present in the tabu list, i.e. satisfy:

indicating the exchange count, adding the operation into a tabu table after the exchange action is executed, and avoiding the subsequent search to execute repeated search, wherein the tabu mode of the exchange action is set for the tabu:

wherein

，/>

And->

And the control superparameter for the tabu step length value enables the tabu step length to be a dynamic value within a reasonable range, so that the evacuation property of searching is improved.And then entering the next iterative search until a legal global layout solution is found.

As shown in fig. 3, the specific process of generating the global layout in step S3 includes the following sub-steps:

s31, based on the initial layout, equally dividing the layout space into a plurality of areas, and initializing a tabu table.

S32, analyzing each area, and selecting potential exchange area pairs.

The analysis is performed for each region, and factors for selecting potential pairs of swap regions include whether the region is in a tabu table, the layout goodness of the region, the frequency at which the region is selected, and the cell distribution in the region.

S33, performing domain actions based on unit exchange on the candidate areas based on the potential exchange areas, and performing exchange effect evaluation.

Fig. 4 is a schematic diagram of a neighborhood motion based on cell exchange, and when performing a domain motion based on cell exchange, the size of a cell and the fitness of the cell in a region are considered. Wherein the fitness is evaluated by the strength of the connection of the unit between the corresponding area and the other units and the impact on the area congestion.

wherein equation (18) represents the unit to be processed

Placed in the region->

Since this stage is only an assessment of the cell to region tightness, and does not need to take into account the specific location of the cell in the region, the center coordinates of the region are used instead of the placement location of the cell in calculating the half perimeter. In the formula (19), ∈>

Representation unit- >

The abscissa of the center of the region, +.>

Representing the units +.>

Placed in the region->

，/>

Representing the maximum abscissa of the center of the area where all the cells associated with the net n are located. Equations (20) - (22) define the minimum value for the abscissa, the maximum value for the ordinate, and the minimum value for the ordinate in a similar manner. The smaller the line length cost evaluation value based on the formula (18) is, the unit +.>

Placed in the region->

The better the solution quality.

The assessment of regional congestion is based primarily on the total remaining area inside the region and the number of free regional fragments. The remaining area measures the future development potential of an area, the larger the remaining area, the more cells that are potentially placeable. While the number of free area fragments is used for measuring the utilization difficulty of the residual area, the more fragments are, the more free areas with smaller area exist, the areas are generally difficult to directly utilize, and based on the two considerations, the evaluation of the area congestion by the project can be formed as the following formula:

wherein

Representing a regionrIs a free area sub-block, +.>

Representation area->

Area of->

And normalizing the parameter for the numerical value, so that the calculation of the numerical value is always kept in a reasonable range. In the above formula, the relation that the congestion degree of a single idle area is not linearly related to the residual area is described by using a calculation method with a natural logarithm as a base index, namely, as the residual linearity is reduced, the congestion degree is exponentially increased, so that the distribution of units in the process of optimizing the layout is guided to be as uniform as possible, and the distribution of units in the subsequent stage is beneficial to the distributability. The smaller the congestion degree evaluation value obtained based on the formula (23), the unit +. >

Placed in the region->

The better the solution quality.

S34, judging whether the current iteration obtains an optimal neighbor solution, if not, updating selection parameters of a tabu table and a region exchange pair, returning to the step S32 again to select a potential exchange region pair and carrying out iterative operation until the optimal neighbor solution is obtained.

And S35, if the current iteration obtains an optimal neighbor solution and the optimal solution method is adopted, outputting the global layout.

S4, relaxing constraint conditions of the wiring sub-problem based on global layout, carrying out global wiring by iteratively calling a single-network wiring algorithm, generating a Steiner forest relaxation solution, and carrying out re-wiring or adjustment repair on a network violating the constraint to obtain an initial layout wiring solution.

Fig. 5 is a global routing algorithm overall framework of the present invention, as shown in fig. 5, step S4 specifically includes:

s41, relaxing air conditioning constraint conditions of the wiring sub-problem based on global layout, and allowing certain line segments to be temporarily laid out in areas with insufficient capacity.

Specifically, the relaxation method includes ways of increasing the cell capacity, allowing network wiring to collide, and the like.

S42, global wiring is respectively carried out on each net through a single-network wiring algorithm, illegal wiring is removed, looseness is tightened, whether a feasible solution is obtained is judged, and otherwise, the steps are repeated until the feasible solution is obtained.

When global wiring is carried out by iteratively calling a single-network wiring algorithm, a mode of combining a dynamic shortest-path wiring method and a multi-mode wiring method is adopted, wiring is subjected to detour optimization by loosening capacity constraint of a grid congestion sensing method, and a Steiner forest relaxation solution is generated.

The main goal of the single wire routing algorithm is to find a routing solution that is as close to optimal as possible, meeting the problem constraints, in a short time. When solving the problem of single-mesh wiring, whether a dynamic shortest-path wiring method or a multi-mode wiring method is adopted, if all the meshes are wired by using only one algorithm, the optimal effect is difficult to reach. Therefore, when a single network is routed, the method of dynamic shortest routing and the method of multi-mode routing are adopted to simultaneously guide three-dimensional routing so as to realize overall pattern optimization, solutions with higher quality are selected as candidate solutions, for some networks with larger scale, a mode of mixing various algorithms can be adopted, multi-mode routing is adopted globally, and a routing method based on dynamic shortest routing is adopted locally.

Fig. 6 is a global routing flowchart of the present invention. The invention adopts a dynamic shortest wiring method and a multi-mode wiring method to simultaneously guide the three-dimensional wiring to realize the optimization of the whole pattern, and properly relaxes capacity constraint to optimize the wiring by a grid congestion sensing method. Passing through a grid while recording wiring

At the original cost of (a)/>

Expanding the Steiner points in the optimal two-dimensional mode wiring result into corresponding three-dimensional vertical grids, and endowing the grids on the related vertical paths with a preference attribute +.>

The preference attribute slightly smaller than 1.0 can enable the algorithm to preferentially consider grids inspired by the optimal two-dimensional mode wiring result when searching a plurality of wiring schemes with the same goodness, so that grid sharing among different wiring paths is facilitated, and the overall goodness is improved. On the other hand, considering that severely limiting the upper limit of the grid capacity tends to result in more failed wires during the search, the present invention translates the capacity constraint in the wiring problem into a congestion assessment of the remaining capacity of the grid. Use->

Representing grid->

Spill capacity of (2) and use ∈>

Measurement grid->

Is a congestion level of (a). For grid->

Redefined as the following formula:

if it is

Then represent grid +.>

There is still a residual capacityThe amount, there is also a certain wiring potential, in this case +.>

Is a relatively small value and the algorithm will be biased towards optimizing +.>

I.e. to find wiring with shorter paths. Along with->

Is increased until->

And->

Congestion index +.>

Will increase rapidly, which in order to reduce the total routing cost, the algorithm will have a greater tendency to bypass the mesh, avoiding huge congestion costs. Although the legality of the path cannot be guaranteed by the grid cost calculation based on the formula (24), a wiring result with a better overall pattern can be obtained.

S43, relaxing the grid capacity upper limit constraint and using the congestion weight

The repair process is repeated until all capacity overflow grids are repaired and a viable wiring scheme is returned.

Specifically, for each grid

Are associated with setting a dynamic congestion weight +.>

At the beginning of the algorithm, the congestion weight of all meshes is set to 0. Since all capacity overflow grids must be eliminated in the final feasible solution, the present invention only needs to randomly select one capacity overflow grid at a time as a repair target and set its weight to +.>

. Then the mesh +.>

Is routed again. It is worth noting that in the routing process, the cost calculation of the grid needs to be added with the penalty of congestion weight, namely the total cost through the grid is modified to be +.>

. If grid->

Is not repaired after re-wiring, its congestion weight is +. >

Doubling (/ ->

) To impose a greater routing penalty. As congestion weight +.>

Is added, the wiring of the net will gradually bypass the mesh +.>

To avoid a huge wiring penalty until the conflict of the grid is repaired, i.e. +.>

. The above process is repeated until all capacity overflow grids are repaired and a viable wiring scheme is returned.

S44, generating an initial layout wiring solution based on the global layout and the feasible wiring scheme.

S5, carrying out multilayer joint optimization on the layout and wiring problems on the basis of the initial layout and wiring solution, and iteratively and alternately adjusting the layout and optimizing the wiring length from the overall pattern to obtain the optimal layout and wiring solution.

Fig. 7 is a schematic diagram of an alternative optimization mechanism of the layout and routing of the present invention, and step S5 specifically includes:

s51, performing cell position exchange movement based on the initial layout wiring solution, and performing mobile cell quality assessment.

In using a layout and wiring multilayer joint optimization mechanism, the evaluation of the movement quality of a unit is important, and the selection of suitable candidate actions in each iteration is the key for ensuring the iteration quality. Each iteration will unit

Move to layout area->

And to keep the position of the other units unchanged and to satisfy the region +. >

Thus minimizing the estimated wire length.

Because of the large scale of the number of cells in the layout problem, in order to find the optimal action for each cell

The invention adopts a two-stage evaluation screening method based on coarse granularity evaluation of half perimeter of the net and fine granularity evaluation of the linear Steiner tree to achieveA trade-off between effectiveness and efficiency. First search for unit candidate placement areas with improved potential using coarse-grained evaluation based on half perimeter of the mesh +.>

. Then in this area->

And (5) performing fine granularity evaluation based on the linear Steiner tree, and finding the optimal target position.

Step S51 specifically includes the following sub-steps:

s511 coarse grain evaluation based on half perimeter of mesh

Is provided with

Representing the current layout +.>

Representing execution of a movement action +.>

Rear layout,/->

Representing the connection to the unit->

Is targeted for coarse-grained evaluation per unit +.>

Find a candidate region +.>

To get the set->

The candidate area is determined for the target of the minimum total half-cycle line length of all nets +.>

The calculation formula is as follows:

wherein ,

representation layout->

Lower net->

Is a half-circumference line length of the steel wire.

Candidate region

Is a classical problem in layout optimization, by computing the set +.>

The median of all net boundary coordinates in (a) is solved, namely:

wherein ,

are respectively the AND units->

The median of the horizontal and vertical coordinates of all nets connected. In order to avoid the algorithm falling into a locally optimal solution and to avoid the concentration of the net and the units in one area, the evaluation method also needs to have a certain evacuation property. In determining candidate region->

After that, the area is expanded to a certain extent so that the lateral width of the area satisfies +.>

Longitudinal width satisfies->

, wherein />

Is a predefined constant which can be flexibly adjusted according to the actual requirements of the scale, solving efficiency, solving quality and the like of the layout problem, and is generally described as +.>

The larger the value of (c), the higher the quality of the solution and the longer the time taken. In addition, part of illegal positions are eliminated from the candidate optimal region according to the voltage region constraint and the region capacity constraint of the unit so as to meet all design constraints in layout optimization, and then all candidate positions are subjected to the next-stage fine-grained evaluation.

S512, fine granularity evaluation based on straight-line Steiner tree

Fine grain assessment is aimed at selecting candidate regions

Is a selection unit->

Since this step will directly affect the subsequent wiring goodness, the evaluation method needs to be able to accurately measure the best target area for a unit movement and its resulting impact and benefit. The invention designs a Steiner tree evaluation algorithm (PHRE) based on a minimum spanning tree, and the process of constructing the Steiner tree is similar to that of a single-network dynamic wiring algorithm in the previous section, except that the algorithm does not consider the constraint of the actual wiring capacity of a grid, and the path search from a key pin to a pin in the wiring can be completed within the time complexity of O (1), so that the time cost of the algorithm search is greatly shortened.

Specifically, it is provided with

Expressed in the current layout->

Lower net->

Line length results of fine evaluation of (2), move action +.>

The latter layout is->

，/>

Expressed in layout->

Lower net->

Line length results of the fine evaluation of (a) then +.>

Candidate region +.>

Is +.>

Movement motion->

The profit calculation formula of (2) is as follows:

representing the units +.>

Move to position->

Reducing the length of the back line to obtainMinimum position->

The estimated wiring length is reduced to the maximum extent, so in +.>

Minimum calculating the optimal target position for the target +.>

Will->

As the best movement position.

S513, cell position exchange movement

The optimal target position calculated based on step S512

Execution unit move action->

。

Step S512 above describes how to determine individual units

Is +.>

In the process of layout iteration optimization, each iteration will compare the best movements of all cells and select one action to perform that reduces the wire length the most. However, each time all units are evaluated, unacceptable time overhead is incurred, and the present invention designs a buffer queue and local update mechanism for unit movement to reduce the time overhead. Only one evaluation of all units is required in the initial stage, all the movement actions which can improve the line length +. >

Adding candidate execution queue, maintaining the queue with binary heap data structure, and taking the head of the queue>

And executing. Since the movement movements between the units are not necessarily independent, the movements are +.>

The execution of (1) will disable the evaluation of some other units in the queue, in which case the action will be taken +.>

All units affected are reevaluated and updated to the candidate execution queue. Since in practical layout problems, movement of a single cell will typically affect the evaluation of only a small fraction of other cells, the queue updates herein have a significant acceleration effect compared to re-evaluating all cells.

S52, performing layout legalization on the new layout generated along with the cell position exchange movement.

Unit cell

Which can cause illegal routing of the net associated with the cell, requiring rewiring of the affected net.

And S53, rewiring the moved unit related network, and performing global optimization on the wiring problem.

Since the result of the cell movement is a new layout and a wiring scheme with a few illegal nets is obtained, which is essentially a new wiring problem, the best cell movement is found

And after the execution, the global wiring is carried out again through the single-mesh wiring algorithm provided in the step S4, the wiring optimization is carried out through a congestion sensing method, the conflict repair of the capacity overflow grid is carried out by adopting a grid congestion weight self-adaptive adjustment mode, the grid capacity overflow conflict which is possibly newly generated is eliminated, and a legal wiring scheme is obtained as a local optimal solution.

S54, algorithm parameters and strategies are adjusted, and the step S51 is returned.

Specifically, the unit goodness evaluation parameters are adjusted, and the selection strategy of the single-network wiring algorithm is adjusted, and the process returns to the step S51 to enter a new round of alternate iterative optimization of the layout-wiring, so that the layout is adjusted and the wiring length is optimized from the overall pattern in an iterative manner.

S55, performing iterative operation until the optimal layout wiring solution is obtained.

And evaluating the quality of a local optimal solution obtained after the overall optimization of the wiring, and taking the current solution as an optimal layout wiring solution if the quality of the solution is not obviously improved after a plurality of iterations.

Corresponding to the embodiment of the method, the invention also discloses a global optimization system for the layout and the wiring of the digital chip, which comprises the following steps:

The system embodiments and the method embodiments are in one-to-one correspondence, and the brief description of the system embodiments is just to refer to the method embodiments.

Claims

1. A global optimization method for digital chip layout and wiring, the method comprising:

2. The global optimization method of digital chip layout and wiring according to claim 1, wherein the performing unit recursion division according to the netlist structure of the standard element, performing linear relaxation on constraint conditions of the layout sub-problem, performing local search by adopting a secondary assignment algorithm, and solving an initial layout of the standard element in each unit, and obtaining a relaxation solution of the layout sub-problem specifically comprises:

3. The global optimization method of digital chip layout and wiring according to claim 1, wherein the performing region division on the layout space of each level, adjusting the initial layout through a tabu search algorithm and domain actions based on cell exchange, and generating the global layout specifically comprises:

analyzing each area, and selecting potential exchange area pairs;

4. The global optimization method of digital chip layout and wiring according to claim 3, wherein the factors for analyzing each area and selecting potential exchange area pairs include whether an area is in a tabu table, the layout goodness of an area, the frequency at which an area is selected, and the cell distribution status in an area;

the strength of the connection between the units is measured based on the following half perimeter calculation formula:

；

wherein

Representing the total half perimeter of all nets connected to the cell c after it has been placed in region r, +.>

Represents the abscissa of the center of the area where the unit c' is located, < > >

Indicating that cell c is placed in region r, +.>

Represents the maximum abscissa of the center of the area in which all the units associated with net n are located, +.>

Minimum value of abscissa, +.>

Maximum value of ordinate and +.>

Is the minimum value of the ordinate;

the impact of regional congestion is evaluated using the following formula:

；

wherein

Representing a free region sub-block in region r, is->

Representing region sub-block->

Area of->

The parameters are normalized for values.

5. The global optimization method of digital chip layout and wiring according to claim 1, wherein the step of generating a stanner forest relaxation solution by iteratively invoking a single-network wiring algorithm to perform global wiring, and performing re-wiring or adjustment repair on a network violating constraints to obtain an initial layout and wiring solution specifically comprises:

carrying out global wiring in a mode of combining a dynamic shortest wiring algorithm with the wiring in the optimal two-dimensional mode, and carrying out detour optimization on the wiring by loosening capacity constraint through a grid congestion sensing method to generate a Steiner forest loosening solution;

relaxing grid capacity upper limit constraints and using congestion weights

Representing the extra cost of the network passing through the capacity overflow grid, and carrying out capacity overflow grid +_ on the network violating constraint by adopting a grid congestion weight self-adaptive adjustment mode >

6. The global optimization method for digital chip layout and routing according to claim 5, wherein the detour optimization of the routing by relaxing capacity constraint by using a grid congestion sensing method specifically comprises:

Representing grid->

Spill capacity of (2) and use ∈>

Measurement grid->

Is ∈m for the grid ∈m>

Redefined as the following formula:

；

wherein ,

for wiring via a grid->

Is the original of (1)Cost (S)>

To consider the wiring cost of the congestion degree, the wiring is +.>

And (5) carrying out wiring optimization aiming at the minimum cost.

7. The global optimization method for digital chip layout and wiring according to claim 1, wherein the performing multi-layer joint optimization on the layout and wiring problem based on the initial layout and wiring solution specifically comprises:

rewiring the moved unit related network, and performing global optimization on wiring problems;

adjusting algorithm parameters and strategies, and carrying out unit position exchange movement again;

8. The global optimization method for digital chip layout and wiring according to claim 1, wherein said performing unit movement evaluation specifically comprises:

each iteration will unit