CN116644708A

CN116644708A - Layout and wiring optimization method, device, computer equipment and storage medium

Info

Publication number: CN116644708A
Application number: CN202310900824.3A
Authority: CN
Inventors: 李德建; 冯曦; 申福恒; 朱自然; 谭浪; 杨立新; 沈冲飞; 刘畅
Original assignee: State Grid Corp of China SGCC; State Grid Jiangsu Electric Power Co Ltd; Beijing Smartchip Microelectronics Technology Co Ltd
Current assignee: State Grid Corp of China SGCC; State Grid Jiangsu Electric Power Co Ltd; Beijing Smartchip Microelectronics Technology Co Ltd
Priority date: 2023-07-21
Filing date: 2023-07-21
Publication date: 2023-08-25
Anticipated expiration: 2043-07-21
Also published as: CN116644708B

Abstract

The embodiment of the specification provides a layout wiring optimization method, a layout wiring optimization device, computer equipment and a storage medium. The method comprises the following steps: acquiring initial wiring results of initial unit positions comprising a plurality of netlist units and initial wiring paths of a plurality of nets; determining target candidate positions of any netlist unit based on the initial unit positions and the multiple nets for any netlist unit; the target candidate position is determined according to any one of the position of the compact unit, the position of the key node and the position corresponding to the target shrinkage of the boundary frame; determining a candidate position set of any netlist unit in a peripheral area of a target candidate position; according to the candidate position set and the initial wiring paths of a plurality of nets, repositioning and pre-wiring are carried out on any netlist unit to obtain an optimized wiring result, so that the relevance between the layout and wiring optimization targets can be improved, the gap between the layout and wiring optimization targets can be reduced, and the quality of the layout and wiring can be improved.

Description

Layout and wiring optimization method, device, computer equipment and storage medium

Technical Field

The embodiment in the specification relates to the technical field of chip design, in particular to a layout and wiring optimization method, a layout and wiring optimization device, computer equipment and a storage medium.

Background

Layout and wiring are one of the cores of the physical design of a very large scale integrated circuit, are typical difficult combination optimization problems of large scale non-deterministic polynomials (Non deterministic Ploynomial, NP), and have great influence on performance indexes of the integrated circuit, such as time delay, wire network routability, power consumption, circuit reliability and the like.

At present, the problem is generally decomposed into an independent layout problem and a wiring problem, and different problems are solved for different optimization targets respectively. However, the related art simply guides the layout based on the congestion estimation of the wires, and it is difficult to make up for the optimization target gap between the layout and the wires, which easily results in the difficulty in achieving the intended target of the quality of the final layout-wire solution, and the quality of the layout wires in the related art is to be improved.

Accordingly, there is a need to provide a layout and wiring optimization method to improve the correlation of optimization targets between the layout and the wiring, thereby improving the quality of the layout and the wiring.

Disclosure of Invention

In view of this, in order to solve at least one of the technical problems in the related art described above to some extent, various embodiments of the present specification are directed to providing a layout wiring optimization method, apparatus, computer device, and storage medium.

The embodiment of the specification provides a layout wiring optimization method, which comprises the following steps: acquiring an initial wiring result; the initial wiring result comprises initial unit positions of a plurality of netlist units and initial wiring paths of a plurality of nets; determining target candidate positions of any netlist unit based on the initial unit positions and a plurality of wire nets for the any netlist unit; wherein the target candidate position is determined according to any one of the position of the compact unit, the position of the key node and the position corresponding to the target shrinkage of the boundary frame; determining a candidate position set of any netlist unit in a peripheral area of the target candidate position; wherein the set of candidate locations includes the target candidate location and candidate locations for the target candidate location; and repositioning and pre-wiring any netlist unit according to the candidate position set and the initial wiring paths of the multiple nets to obtain an optimized wiring result.

Preferably, the target candidate locations of any netlist cell are determined by: taking any one netlist unit as a target netlist unit, and determining the association degree of the target netlist unit and non-target netlist units in a plurality of netlist units through the wire nets corresponding to the target netlist units; determining compact units of the target netlist units from non-target netlist units in the netlist units according to the association degree; and taking the position of the compact unit as the target candidate position of the target netlist unit.

Further, the determining, through the net corresponding to the target netlist unit, the association degree between the target netlist unit and non-target netlist units in the netlist units includes: traversing the net connected with the target netlist unit, and determining at least one non-target netlist unit connected with the target netlist unit; determining, for any non-target netlist cell, a number of the nets between the target netlist cell and the any non-target netlist cell and a number of pin nodes of the nets; and determining the association degree between the target netlist unit and any non-target netlist unit according to the number of the nets between the target netlist unit and the any non-target netlist unit and the number of pin nodes of the nets.

Preferably, the target candidate locations of any netlist cell are determined by: taking any netlist unit as a target netlist unit, traversing nodes on initial wiring paths of a plurality of nets corresponding to the target netlist unit; taking the pin nodes and the nodes with the node degree larger than a preset value as key nodes to obtain a key node set; the node degree represents the in-out number of the network connected by the node; and determining the target candidate position of the target netlist unit according to the positions of the key nodes in the key node set.

Further, the determining the target candidate position of the target netlist unit according to the positions of the key nodes in the key node set includes: determining a first direction position set of key nodes in the key node set in a first direction and a second direction position set of key nodes in the key node set in a second direction according to the positions of the key nodes in the key node set; determining a first direction median position and a second direction median position according to the first direction position set and the second direction position set; and determining the target candidate position of the target netlist unit according to the first direction neutral position and the second direction neutral position.

Preferably, taking any one netlist unit as a target netlist unit, and determining a unit boundary frame area of the target netlist unit according to initial wiring paths of a plurality of nets corresponding to the target netlist unit; performing simulated movement on the target netlist unit in the unit boundary box area, and determining the boundary box shrinkage corresponding to any position of the target netlist unit in the unit boundary box area; and taking the target netlist unit as the target candidate position of the target netlist unit, wherein the target netlist unit reaches the position corresponding to the target shrinkage of the boundary frame in the unit boundary frame area.

Preferably, the repositioning and pre-routing the netlist unit according to the candidate position set and the initial routing paths of the multiple nets to obtain an optimized routing result includes: taking any candidate position in the candidate position set as a target position; removing said netlist cells from the initial routing paths of the connected nets; repositioning the netlist unit to the target position to obtain a pre-optimized unit position; pre-wiring the netlist unit according to a net reconnection algorithm to obtain a pre-optimized wiring path of the netlist unit aiming at the target position; if it is determined that no wire overflow occurs and the unit movement benefit reaches a unit movement benefit threshold based on the pre-optimized unit position and the pre-optimized wire route, taking the pre-optimized unit position as an optimized unit position and the pre-optimized wire route as the optimized wire route; the cell movement benefit is the reduction of the bus length of all nets connected with the cells of any netlist.

Further, if it is determined that a route overflow occurs based on the pre-optimized cell locations and the pre-optimized route paths, and/or the cell movement benefit does not reach the cell movement benefit threshold, other candidate locations in the candidate location set are used as the target locations to determine optimized cell locations and optimized route paths for the cells of the arbitrary netlist.

Preferably, the method further comprises: if the total movement income of the optimized wiring result is judged to not reach the convergence condition, the optimized wiring result is used as the initial wiring result, and the layout and wiring optimization is repeated; wherein the total movement benefit is a reduction in bus length of the net.

The embodiment of the present specification provides a layout wiring optimizing apparatus, the apparatus including: the initial wiring result acquisition module is used for acquiring an initial wiring result; the initial wiring result comprises initial unit positions of a plurality of netlist units and initial wiring paths of a plurality of nets; a target candidate position determining module, configured to determine, for any netlist unit, a target candidate position of the any netlist unit based on the initial unit position and a plurality of nets; wherein the target candidate position is determined according to any one of the position of the compact unit, the position of the key node and the position corresponding to the target shrinkage of the boundary frame; a candidate position set determining module, configured to determine a candidate position set of the any netlist unit in a surrounding area of the target candidate position; wherein the set of candidate locations includes the target candidate location and candidate locations for the target candidate location; and the layout wiring result optimizing module is used for repositioning and pre-wiring any netlist unit according to the candidate position set and the initial wiring paths of the multiple nets to obtain an optimized wiring result.

The embodiment of the present specification provides a computer device, including a memory and a processor, where the memory stores a computer program, and the processor executes the computer program to implement the method for optimizing layout and wiring according to any of the embodiments.

The present specification embodiment provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the layout wiring optimization method of any of the above embodiments.

According to the embodiments, an initial wiring result including initial unit positions of a plurality of netlist units and initial wiring paths of a plurality of nets is obtained, any one of the positions of compact units, positions of key nodes and positions corresponding to target shrinkage of a boundary frame of any one netlist unit is determined based on the initial unit positions of the netlist units and the plurality of nets, target candidate positions of the netlist units are determined according to any one of the positions of the compact units, the positions of the key nodes and the positions corresponding to target shrinkage of the boundary frame, candidate positions of the netlist units are determined in a peripheral area of the target candidate positions, so that a candidate position set of the netlist units is determined, repositioning and pre-wiring are performed on the netlist units according to the candidate position set and the initial wiring paths of the plurality of nets, and an optimized wiring result is obtained.

Drawings

Fig. 1 is a schematic diagram of a flow of a layout and wiring optimization method provided in an embodiment of the present disclosure;

FIG. 2 is a flowchart illustrating a method for determining a candidate target position according to an embodiment of the present disclosure;

FIG. 3 is a flowchart illustrating a method for determining a candidate target position according to an embodiment of the present disclosure;

FIG. 4 is a flowchart illustrating a method for determining a candidate target position according to an embodiment of the present disclosure;

FIG. 5 is a flowchart illustrating a method for determining a candidate target position according to an embodiment of the present disclosure;

FIG. 6 is a flowchart illustrating a method for determining a candidate target position according to an embodiment of the present disclosure;

FIG. 7 is a flowchart of a method for determining a candidate target position according to an embodiment of the present disclosure;

fig. 8 is a schematic diagram of a flow of a layout and routing optimization method provided in an embodiment of the present disclosure;

fig. 9 is a schematic diagram of a layout and wiring optimizing apparatus provided in the embodiment of the present specification;

fig. 10 is a schematic diagram of a computer device according to an embodiment of the present disclosure.

Detailed Description

In order to make the technical solution of the present specification better understood by those skilled in the art, the technical solution of the present specification embodiment will be clearly and completely described below with reference to the accompanying drawings in the embodiment of the present specification, and it is apparent that the described embodiment is only a part of the embodiment of the present specification, but not all the embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are intended to be within the scope of the present disclosure.

The integrated circuit design (Integrated circuit design, IC design), also referred to as very large scale integrated circuit design (VLSI design), refers to a design flow targeting integrated circuits, very large scale integrated circuits. The integrated circuit design flow may be divided into two parts, logic design and physical design.

The logic design, i.e. the front-end design, may include specification customization, detailed design, HDL (Hardware Design Language) encoding, simulation verification, logic synthesis, static timing analysis, and form verification, and a gate level netlist unit may be obtained based on the logic design.

The physical Design, i.e. the back-end Design, refers to the Design related to the process involved in the integrated circuit Design flow, which is the process of determining the geometrical arrangement of netlist cells and their connection in the integrated circuit layout, and converting the netlist cells into a physical layout, and basically may include Design for test (DFT), layout for plan (FloorPlan), clock tree synthesis (Clock Tree Synthesis, CTS), place and Route (PAR), parasitic parameter extraction, and layout physical verification. Often, the chip is built with test circuitry, and the purpose of the DFT is to take future tests into account during design. The layout, namely the global layout, can carry out complete planning and design on the internal structure of the chip, can determine the placement position of each functional circuit on the whole, and can directly influence the final area of the chip. Because of the global steering of the clock signal on the digital chip, the distribution should be symmetrically connected to each register unit so that clock delay differences are minimized when the clock signal arrives at each register from the same clock source, the CTS may determine buffering, gating and routing of the clock signal, i.e., routing of the clock, to meet specified offset and delay requirements. Placement and routing may determine the spatial locations of the netlist cells and allocate routing resources for the connections. And the parasitic parameters are extracted for analysis and verification, and the signal integrity is analyzed, so that signal voltage fluctuation, variation and distortion errors can be reduced. The layout physical verification can perform functional and time sequence verification on the physical layout of the layout and the wiring so as to perform subsequent chip manufacturing.

At present, the problem is generally decomposed into an independent layout problem and a wiring problem, and different optimization targets are adopted for different problems to solve the problem respectively. For example, the relevant placement tool and routing tool may be invoked to generate an accurate routing congestion map by integrating a global router in the placer when placing netlist cells in the placement stage, then employ efficient super-linear cell expansion techniques to relieve routing congestion during global placement, or employ dynamic cell expansion and congestion elimination models to optimize routability, then optimize placement based on the congestion map, adjust netlist cell placement locations, and route after placement meets requirements. However, the related method simply guides the layout based on the wiring congestion estimation, and it is difficult to make up for the optimization target gap between the layout and the wiring, which easily results in degradation of the quality of the final solution.

In addition, in order to optimize performance and power consumption in the advanced process node, it is necessary to consider the advanced process constraint and goal in physical design, for example, layer-based power constraint, voltage region constraint, timing constraint, etc., and as the number of transistors increases rapidly, the physical design on the nanometer scale becomes more complex, and the adverse effect of the split layout flow will be amplified.

Therefore, it is necessary to use a more uniform and efficient optimization procedure for the layout and the wiring in the physical design to cooperatively optimize the layout and the wiring, so as to improve the correlation between the layout and the wiring optimization targets and reduce the gap between the layout and the wiring optimization targets, thereby effectively reducing the performance indexes such as the bus length of the wiring scheme and improving the quality of the layout and the wiring.

Referring to fig. 1, fig. 1 is a schematic flow chart of a layout and wiring optimization method according to the present embodiment, where the method includes steps of operation of the method according to the present embodiment, but may include more or less steps based on conventional or non-creative labor. The order of steps recited in the embodiments is merely one implementation of a plurality of step execution orders and does not represent a unique execution order. In actual system or server product execution, the methods illustrated in the embodiments may be performed sequentially or in parallel (e.g., in parallel processors or in the context of multi-threaded processing). As shown in fig. 1 in particular, the layout optimization method may include the following steps.

Step S110: acquiring an initial wiring result; wherein the initial routing result includes initial cell locations of the plurality of netlist cells and initial routing paths of the plurality of nets.

In some embodiments, a plurality of gate level netlist cells of the chip, i.e., gate level netlist circuits, may be obtained through logic design, wherein the netlist cells may be descriptive of the connection relationship of circuit elements to each other. After the logic design is completed, a data importing operation may be performed to obtain a plurality of netlist units, and physical designs such as layout, placement, routing, and the like may be performed for the plurality of netlist units. Specifically, the complete planning and design can be performed through the floorplan to obtain a floorplan result, and the floorplan result generally determines the placement positions of the netlist units. Then, an existing layout tool can be called to perform layout based on the layout result and each netlist unit in and out initially to obtain an initial layout result, and the initial layout result determines the initial unit position of each netlist unit. And the existing wiring tool can be called to perform wiring based on the initial layout result to obtain an initial wiring result, and the initial wiring result determines the initial wiring path of the net connected with each netlist unit, namely, the initial layout wiring solution is obtained.

In some cases, there is a gap in optimization targets between the layout and the wiring, and the initial layout result and the initial wiring result are obtained by respectively solving based on different optimization targets, which easily causes that the initial wiring result obtained based on the initial layout result is difficult to reach the expected layout wiring solution.

In this embodiment, the initial routing result may be obtained so that the initial routing result may be subsequently optimized in a layout-wiring co-optimization by the initial cell locations of the netlist cells and the initial routing paths of the nets to which the netlist cells are connected, and a near-optimal layout-wiring solution is expected. Wherein the initial routing result may include initial cell locations of the plurality of netlist cells and initial routing paths of the net to which each of the plurality of netlist cells is connected.

Step S120: determining target candidate positions of any netlist unit based on the initial unit positions and the multiple nets for any netlist unit; wherein the target candidate position is determined according to any one of the position of the compact unit, the position of the key node, and the position corresponding to the target shrinkage of the bounding box.

In some cases, collaborative optimization for initial routing results may include adjusting initial cell locations of a plurality of netlist cells and initial routing paths of a plurality of nets in the initial routing results. Illustratively, any netlist cell in the initial wiring result and the initial wiring path of the net connected with the netlist cell can be evaluated, the netlist cell capable of performing cell movement is determined through evaluation, and the initial cell position of any netlist cell capable of performing cell movement is adjusted, so that layout optimization is realized. Illustratively, for any netlist cell whose position is adjusted, the net connected thereto can be reconnected, and the initial routing path of the net connected thereto is adjusted, thereby achieving routing optimization.

In this embodiment, for any netlist cell that can be cell shifted, a target candidate position for the netlist cell can be determined based on the initial cell position of the netlist cell and the multiple nets to which the netlist cell is connected. Specifically, for example, for any netlist cell, a target candidate location for a subsequent cell movement of the netlist cell may be determined based on an initial cell location of the netlist cell, a plurality of nets to which the netlist cell is connected, and a plurality of other netlist cells to which the netlist cell is connected through the nets.

For example, the target candidate location may be determined based on the location of the tight cell of the netlist cell, where the tight cell of the netlist cell refers to the netlist cell with the highest association with the netlist cell in the initial routing result.

The target candidate locations may also be determined, for example, based on locations of key nodes in the multiple nets to which the netlist cells are connected, where a key node refers to a node in the multiple nets to which the netlist cells are connected for which an impact weight reaches a certain impact weight threshold.

The target candidate locations may also be determined, for example, by locations corresponding to a bounding box target contraction of the netlist cell, where the bounding box target contraction is determined based on the netlist cell and a plurality of other netlist cells to which the netlist cell is connected through a plurality of nets. Illustratively, the netlist cells may have a corresponding cell bounding box region, which refers to the smallest region that can contain the netlist cells and a plurality of other netlist cells connected to the netlist cells through a plurality of nets, the extent of which may be reduced if the netlist cells are moved within the cell bounding box region, that is, the netlist cells may have a corresponding bounding box shrink when moved within the cell bounding box region, and the location corresponding to the bounding box target shrink refers to the bounding box shrink that the netlist cells achieve when moved to a location within the cell bounding box region. As an example, the bounding box target shrink may refer to the maximum amount of bounding box shrink that the netlist cell can achieve when moving within the cell bounding box region, i.e., the target candidate location may be the location corresponding to the maximum amount of bounding box shrink that the netlist cell can achieve when moving within the cell bounding box region.

Step S130: determining a candidate position set of any netlist unit in a peripheral area of a target candidate position; wherein the set of candidate locations includes the target candidate location and candidate locations for the target candidate location.

In some cases, due to routing rules constraints such as routing congestion and capacity limitations, alternative locations may be determined based on target candidate locations to attempt when cell movement is subsequently performed, but the target candidate location cannot be the final location of the cell movement.

In this embodiment, after determining the target candidate position for any netlist unit, a plurality of candidate positions of the target candidate position may be determined in a peripheral area of the target candidate position, so as to determine a candidate position set of the netlist unit, where the candidate position set of the netlist unit may include the target candidate position and the plurality of candidate positions of the target candidate position. Illustratively, the locations described in this embodiment of the present specification may refer to a mesh for placing netlist cells, and the multiple candidate locations for the target candidate location may be 8 other meshes in the perimeter 3*3 mesh of the mesh in which the target candidate location is located.

Step S140: and repositioning and pre-wiring any netlist unit according to the candidate position set and the initial wiring paths of a plurality of nets to obtain an optimized wiring result.

In this embodiment, after determining the candidate position set of any netlist unit capable of performing the unit movement in the initial routing result, the netlist unit may be sequentially tried to be moved from its initial unit position to any candidate position in the candidate position set thereof, so as to relocate the netlist unit, and pre-route the relocated netlist unit, so as to adjust initial routing paths of a plurality of nets of the netlist unit, and the optimized unit position of the netlist unit and the optimized routing paths of a plurality of nets connected to the netlist unit may be determined in at least one attempted movement of the netlist unit, and the optimized routing result may be obtained after relocating and pre-routing all netlist units capable of performing the unit movement in the initial routing result.

In the above embodiment, by acquiring the initial routing result including the initial cell positions of the plurality of netlist cells and the initial routing paths of the plurality of nets, determining any one of the positions of the compact cells, the positions of the key nodes and the positions corresponding to the target shrinkage of the boundary frame of any one netlist cell based on the initial cell positions and the plurality of nets connected thereto, and determining the candidate position set of the netlist cell according to any one of the positions of the compact cells, the positions of the key nodes and the positions corresponding to the target shrinkage of the boundary frame, and repositioning and pre-routing the netlist cell according to the candidate position set and the initial routing paths of the plurality of nets connected thereto, thereby obtaining the optimized routing result, achieving collaborative optimization of the layout and the routing for the initial routing result, improving the association between the layout and the routing optimization targets, reducing the gap between the layout and the routing optimization targets, and improving the quality of the layout and the routing.

In some embodiments, the place and route optimization method may further include the steps of: if the total movement income of the optimized wiring result is judged to not reach the convergence condition, the optimized wiring result is used as an initial wiring result, and the layout and wiring optimization is repeatedly carried out; wherein the total movement benefit is a reduction in the bus length of the net.

In some cases, collaborative optimization of place and route may be performed by iteration.

In this embodiment, whether the total movement gain of the optimized wiring result reaches the convergence condition may be determined, and if it is determined that the total movement gain of the optimized wiring result does not reach the convergence condition, the optimized wiring result may be used as the initial wiring result, and the layout and wiring optimization may be repeated.

In some embodiments, referring to fig. 2, fig. 2 is a flowchart illustrating a method for determining a target candidate position according to the present embodiment, where the target candidate position of any netlist unit can be determined by the following steps.

Step S210: and taking any netlist unit as a target netlist unit, and determining the association degree of the target netlist unit and non-target netlist units in the netlist units through a wire mesh corresponding to the target netlist unit.

In some cases, for any netlist cell that can be cell shifted, a target candidate location for the netlist cell may be determined based on a degree of association between the netlist cell and other netlist cells that have a connection relationship with the netlist cell.

In this embodiment, for any one of the netlist cells in the initial layout result, the netlist cell may be used as a target netlist cell, and other netlist cells connected to the target netlist cell through a net may be used as non-target netlist cells of the target netlist cell, and the degree of association between the target netlist cell and the non-target netlist cell may be determined based on the net connecting the target netlist cell and the non-target netlist cell.

Specifically, the target netlist unit may be connected with a plurality of non-target netlist units, a plurality of nets may be connected between the target netlist unit and any non-target netlist unit, any net connected with the target netlist unit may be connected with at least 1 non-target netlist unit, and the nets are connected with the target netlist unit or the non-target netlist unit through corresponding pin nodes.

Illustratively, referring to FIG. 3, the degree of association between a target netlist cell and any non-target netlist cell can be determined by the following steps.

Step S310: traversing the net of target netlist cell connections, determining at least one non-target netlist cell connected to the target netlist cell.

Step S320: for any non-target netlist cell, determining a number of nets between the target netlist cell and the non-target netlist cell and a number of pin nodes of any net between the target netlist cell and the non-target netlist cell.

Step S330: and determining the association degree between the target netlist unit and the non-target netlist unit according to the number of the nets between the target netlist unit and the non-target netlist unit and the number of pin nodes of any net between the target netlist unit and the non-target netlist unit.

As an example, the association of target netlist cells with non-target netlist cells may be determined according to equation 1.

Equation 1

Wherein C is ₁ Representing the target netlist unit, C ₂ Representing non-target netlist elements, affinities (C ₁ ，C ₂ ) Representing the degree of association between target netlist cell C1 and non-target netlist cell C2, N representing target netlist cell C ₁ Non-target netlist unit C ₂ A net set connected between the two nets, N representing any net in net set N, size _n Representing the number of pin nodes to which any net N in net set N is connected. Based on equation 1, when the number of nets connected to the target netlist cells and the non-target netlist cells is larger and the distance between the target netlist cells and the non-target netlist cells is longer, the line length reduction gain of the nets caused by moving the target netlist cells and the non-target netlist cells to the same position or adjacent positions is larger.

Step S220: and determining compact units of the target netlist units from non-target netlist units in the netlist units according to the association degree.

In this embodiment, after determining the degree of association between the target netlist unit and any one of the non-target netlist units, the compact unit of the target netlist unit may be determined from any one of the non-target netlist units according to the degree of association. Specifically, the tight cells of the target netlist cells may be determined according to the magnitude of the association, for example, the non-target netlist cells having the largest association may be used as the tight cells of the target netlist cells.

Step S230: the locations of the compact cells are taken as target candidate locations for the target netlist cells.

In this embodiment, after determining the compact unit of the target netlist unit, the position of the compact unit may be used as the target candidate position of the target netlist unit, and the target netlist unit and the compact unit of the target netlist unit may be bound, so that in the subsequent process of performing the unit movement, the target netlist unit may be moved to the position where the compact unit is located or to the adjacent position where the compact unit is located, so as to effectively reduce the line length of the net.

In the above embodiment, by using any one netlist unit as the target netlist unit, determining the association degree between the target netlist unit and a plurality of non-target netlist units according to the net corresponding to the target netlist unit, determining the compact unit from the plurality of non-target netlist units according to the association degree, and using the position of the compact unit as the target candidate position for the subsequent unit movement of the target netlist unit, the position prediction for the subsequent unit movement based on the unit association degree can be realized, and the subsequent collaborative optimization of the layout and the wiring for the initial wiring result is facilitated.

In some embodiments, referring to fig. 4, fig. 4 is a flowchart illustrating a method for determining a target candidate position according to the present embodiment, where the target candidate position of any netlist unit can be determined by the following steps.

Step S410: and traversing nodes on initial wiring paths of a plurality of nets corresponding to the target netlist unit by taking any netlist unit as the target netlist unit.

In some cases, for any netlist cell that can be cell shifted, a target candidate location for the netlist cell can be determined based on the node on the wire mesh to which the netlist cell is connected.

In this embodiment, for any one of the netlist cells in the initial routing result, the netlist cell may be taken as a target netlist cell, and other netlist cells connected to the target netlist cell through a net may be taken as non-target netlist cells of the target netlist cell, and nodes on the initial routing path of the net to which the target netlist cell is connected may be traversed. Specifically, the nodes on the initial routing path of the net connected to the target netlist cells may include pin nodes of the net connected to the target netlist cells, may include pin nodes of the net connected to the non-target netlist cells, and may include junction nodes of two or more nets, so that all nodes on the initial routing path of the net connected to any one target netlist cell may be determined.

Step S420: taking the pin nodes and the nodes with the node degree larger than a preset value as key nodes to obtain a key node set; the node degree represents the number of access points of the network connected by the nodes.

In some cases, after all nodes on the initial routing path of the net to which any target netlist cell is connected are determined, the nodes with larger influence weights can be used as key nodes, so that the target candidate positions of the target netlist cells can be determined according to the positions of the nodes with larger influence weights.

In this embodiment, the pin node and the node with the node degree greater than the preset value may be used as the key nodes to obtain the key node set, where the preset value is a positive integer. Specifically, the pin nodes connected with the net and the target netlist unit can be used as key nodes, the pin nodes connected with the net and the non-target netlist unit can be used as key nodes, and the node degree in the convergence node can be used as key nodes, wherein the node degree of the convergence node can represent the in-out number of the net connected with the convergence node, or the node degree of the convergence node comprises the out-out degree and the in-out degree of the convergence node. As an example, the preset value may be a value of 2.

Step S430: and determining target candidate positions of the target netlist units according to the positions of the key nodes in the key node set.

In this embodiment, after determining the set of key nodes, the position of each key node in the set of key nodes may be determined to obtain a set of key node positions, and the target candidate position of the target netlist unit may be determined according to the set of key node positions, so that when the target netlist unit performs cell movement, the target netlist unit may be moved to the target candidate position determined according to the position of the key node, so as to effectively reduce the line length of the net.

Specifically, referring to fig. 5, determining a target candidate location of a target netlist unit according to the locations of the key nodes in the set of key nodes may include the following steps.

Step S510: and determining a first direction position set of the key nodes in the key node set in the first direction and a second direction position set of the key nodes in the key node set in the second direction according to the positions of the key nodes in the key node set.

Wherein the first direction and the second direction are perpendicular.

Step S520: and determining the first direction middle position and the second direction middle position according to the first direction position set and the second direction position set respectively.

Step S530: and determining target candidate positions of the target netlist unit according to the first-direction neutral position and the second-direction neutral position.

In the above embodiment, the node on the initial wiring path of the multiple nets connected with the target netlist unit is traversed, the pin node and the node with the node degree larger than the preset value are used as the key nodes, the key node set is obtained, and the target candidate position of the target netlist unit is determined according to the position of the key node in the key node set, so that the position prediction for the subsequent unit movement based on the key node can be realized rapidly, and the subsequent collaborative optimization of the layout and the wiring for the initial wiring result is facilitated.

In some embodiments, referring to fig. 6, fig. 6 is a flowchart illustrating a method for determining a target candidate position according to the present embodiment, where the target candidate position of any netlist unit can be determined by the following steps.

Step S610: and taking any netlist unit as a target netlist unit, and determining a unit boundary box area of the target netlist unit according to initial wiring paths of a plurality of nets corresponding to the target netlist unit.

In some cases, for any netlist cell that can be cell shifted, a target candidate location for the netlist cell may be determined based on the netlist cell and cell bounding box regions corresponding to other netlist cells that have a connection relationship with the netlist cell.

In this embodiment, for any one of the netlist cells in the initial routing result, the netlist cell may be used as a target netlist cell, and a cell bounding box region of the target netlist cell may be determined from initial routing paths of a plurality of nets to which the target netlist cell is connected. Specifically, referring to fig. 7, for target netlist unit 710, initial routing paths of a plurality of nets connected to target netlist unit 710 may be traversed to determine a plurality of non-target netlist units 720 connected to target netlist unit 710, and based on the positions of target netlist unit 710 and the positions of the plurality of non-target netlist units 720, a cell bounding box region 730 corresponding to target netlist unit 710 may be determined, the cell bounding box region 730 being a minimum region capable of containing target netlist unit 710 and the plurality of non-target netlist units 720.

Step S620: and performing simulated movement on the target netlist unit in the unit boundary box area, and determining the boundary box shrinkage corresponding to any position of the target netlist unit in the unit boundary box area.

In this embodiment, after determining the cell bounding box region corresponding to the target netlist cell, the target netlist cell may be moved in a simulated manner in the cell bounding box region, and the amount of bounding box shrinkage corresponding to any position in the simulated manner in the corresponding cell bounding box region may be determined. Specifically, referring to fig. 7, the target netlist unit 710 may be moved in a simulation in a first direction and a second direction in the cell bounding box region, and the amount of bounding box shrinkage of the target netlist unit 710 in the first direction and the second direction during the simulation movement may be determined, where the first direction is perpendicular to the second direction.

Step S630: and taking the target netlist unit as a target candidate position of the target netlist unit, wherein the target netlist unit reaches a position corresponding to the target shrinkage of the bounding box in the unit bounding box area.

In this embodiment, after determining the amount of boundary frame shrinkage corresponding to any position of the target netlist unit in the cell boundary frame region, it may be determined whether or not the amount of boundary frame shrinkage corresponding to any position in the cell boundary frame region reaches the boundary frame target shrinkage amount, and if so, the position corresponding to the boundary frame target shrinkage amount of the target netlist unit in the cell boundary frame region may be set as the target candidate position of the target netlist unit. Specifically, referring to fig. 7, the first direction may be the x direction, the second direction may be the y direction, the corresponding bounding box shrinkage amounts of the target netlist unit 710 when performing the simulated movement in the cell bounding box region may be calculated in the x and y directions, respectively, and if the corresponding bounding box shrinkage amount of the target netlist unit 710 when performing the simulated movement in the x direction reaches the bounding box maximum shrinkage amount in the x direction, and the corresponding bounding box shrinkage amount of the target netlist unit 710 when performing the simulated movement in the y direction reaches the bounding box maximum shrinkage amount in the y direction, the corresponding positions in the x and y directions may be determined based on the bounding box maximum shrinkage amounts of the target netlist unit 710 in the x and y directions, respectively, so as to determine the target candidate positions of the target netlist unit 710.

In the above embodiment, by using any one netlist unit as the target netlist unit, determining the unit bounding box area of the target netlist unit according to the initial routing paths of the multiple nets corresponding to the target netlist unit, performing simulated movement on the target netlist unit in the unit bounding box area, determining the bounding box shrinkage corresponding to any position of the target netlist unit in the unit bounding box area, and using the position of the target netlist unit corresponding to the bounding box target shrinkage in the unit bounding box area as the target candidate position of the target netlist unit, the position prediction of the subsequent unit movement based on the bounding box shrinkage of the netlist unit can be realized, and the subsequent collaborative optimization of the layout and routing for the initial routing result is facilitated.

In some embodiments, referring to FIG. 8, repositioning and pre-routing any netlist cell based on a set of candidate locations and initial routing paths for a plurality of nets to obtain an optimized routing result may include the following steps.

Step S810: any candidate position in the candidate position set is taken as a target position.

In some cases, after performing position prediction for any netlist unit capable of performing unit movement, so as to determine a candidate position set of any netlist unit, for any netlist unit, an attempt can be sequentially performed based on each candidate position in the candidate position set, and repositioning and pre-wiring can be performed on the netlist unit, so as to realize collaborative optimization of layout and wiring.

In this embodiment, any candidate position in the corresponding candidate position set may be used as the target position for any netlist unit, so that when a unit movement is performed for the netlist unit, the netlist unit may be moved to the target position for relocation and pre-wiring.

Step S820: netlist cells are removed from the initial routing paths of the connected nets.

In this embodiment, netlist cells can be removed from the initial routing paths of the nets to which they are connected so that cell shifting can be performed for the netlist cells.

Step S830: repositioning the netlist cells to target locations.

In this embodiment, the netlist unit may be shifted so that the netlist unit is relocated to a target position, and by relocating the netlist unit to the target position, a pre-optimized cell position of the netlist unit may be obtained.

Step S840: and pre-wiring the netlist unit according to a net reconnection algorithm to obtain a pre-optimized wiring path of the netlist unit aiming at the target position.

In some cases, because the net connection between netlist cells is often complex, after repositioning netlist cells to a target location, the netlist cells may be pre-routed according to a net reconnection algorithm to obtain a pre-optimized routing path of the net of the netlist cells for the target location.

Step S850: and if the pre-optimized unit position and the pre-optimized wiring path are determined that no wiring overflow occurs and the unit movement benefit reaches the unit movement benefit threshold, taking the pre-optimized unit position as the optimized unit position and taking the pre-optimized wiring path as the optimized wiring path.

Wherein the movement yield is the reduction of the bus length of all nets to which the netlist cells are connected.

In some cases, for any netlist cell, the generated cell movement benefits may be different when different candidate locations in the candidate location set are the target locations, for example, when the target candidate locations and the candidate locations in the candidate location set are the target locations of the cell movement respectively, the generated cell movement benefits may be different, and in addition, when different candidate locations are the target locations of the cell movement, the generated cell movement benefits may be different, so as to obtain a larger cell movement benefit after implementing the relocation and pre-routing of the cell movement for the netlist cell, and a corresponding determination may be made, thereby determining the target location with a larger cell movement benefit.

In this embodiment, after repositioning and pre-routing the netlist cells to obtain pre-optimized cell positions and pre-optimized routing paths of the netlist cells, a determination may be made based on the pre-optimized cell positions and pre-optimized routing paths of the netlist cells, and if no routing overflow occurs and the cell movement benefit reaches the cell movement benefit threshold, the pre-optimized cell positions may be used as optimized cell positions and the pre-optimized routing paths may be used as optimized routing paths.

In some embodiments, if it is determined that a route overflow has occurred based on the pre-optimized cell locations and pre-optimized route paths, and/or the cell movement benefit does not reach the cell movement benefit threshold, other candidate locations in the set of candidate locations may be targeted to determine optimized cell locations and optimized route paths for the netlist cells.

In the above embodiment, by sequentially attempting any candidate position in the candidate position set as a target position, removing the netlist unit from the initial wiring path of the connected net, repositioning the netlist unit to the target position, and pre-wiring the netlist unit according to the net reconnection algorithm, a pre-optimized unit position and a pre-optimized wiring path of the netlist unit for the target position can be obtained, if no wiring overflow occurs and the unit movement benefit reaches the unit movement benefit threshold, the pre-optimized unit position is used as an optimized unit position, and the pre-optimized wiring path is used as an optimized wiring path, if wiring overflow occurs and/or the unit movement benefit does not reach the unit movement benefit threshold, attempting to continue to use the next candidate position in the candidate position set as the target position, and continuing repositioning and pre-wiring to determine the optimized unit position and the optimized wiring path of the netlist unit.

The present specification embodiment provides a place and route optimization method, which may include the following steps.

Step S901: calling a layout tool, and generating an initial layout result based on the imported initial netlist unit; wherein the initial placement result includes initial cell locations of the plurality of netlist cells.

Step S903: calling a wiring tool, and generating an initial wiring result based on the initial layout result; wherein the initial routing result includes initial cell locations of the plurality of netlist cells and initial routing paths of the plurality of nets of any one netlist cell.

Step S905: for the netlist unit capable of performing unit movement, evaluating initial unit positions of the netlist unit and initial wiring paths of a wire net connected with the netlist unit, and performing repositioning and pre-wiring according to an evaluation result to obtain an optimized layout result; and the optimized layout result is the optimized unit position determined by optimizing after repositioning the netlists.

Specifically, the netlist cells capable of cell movement can be evaluated by the following three different cell position prediction methods, and different prediction methods can be selected according to different situations to determine target candidate positions so as to optimize the line length of the net.

Method (1): position prediction based on unit association.

The association degree between any two netlist units can be calculated, the compact unit of each unit is determined according to the association degree value, the compact units are bound, and in the process of moving the subsequent units, the line length of a line net can be effectively reduced by moving each unit into the grid where the compact unit is located. Specifically, the degree of association between any two netlist elements can be calculated by equation 1.

Equation 1

Wherein C is ₁ And C ₂ Representing any two netlist cells, N being netlist cell C ₁ And netlist unit C ₂ A set of nets connected therebetween, N representing any net in set N, size _n Is the number of pin nodes to which net n is connected. As can be seen from equation 1, when two netlist cells are connected more net and two netlist cells are far away, the cell movement benefit or the line length decrease benefit caused by moving the two netlist cells into the same grid is relatively large, so that for one netlist cell, another netlist cell with the highest association degree can be used as a compact cell, and the grid where the compact cell is located can be used as a candidate position. However, due to complicated routing rule constraints such as routing congestion and grid capacity limitation, in actual candidate position selection, instead of using the position of the compact unit as a candidate position, 8 other grids in the 3*3 grid surrounding the position of the compact unit may be selected as candidate positions to obtain a candidate position set, and in the process of moving the subsequent units, the unit movement may be attempted sequentially according to the corresponding ranking criteria.

Method (2): position prediction based on key nodes.

For any netlist unit, all nodes on an initial wiring path of a connected net can be traversed, during the traversing process, pin nodes on the initial wiring path and nodes with the node degree not smaller than 2 can be marked as key nodes, the key nodes are stored, and then the median positions of all key nodes in all nets connected by the netlist unit in the x direction and the y direction are calculated to determine the final candidate positions of the netlist unit.

IllustrativelyNetlist unit C can be calculated using the following steps SS1-SS5 ₁ Is used to determine the final candidate position of the object.

SS1: traversing netlist unit C ₁ The initial wiring path of any wire net n, and the position coordinates of all key nodes on the initial wiring path are stored in the wire net array pos corresponding to the wire net n _n In (a) and (b); wherein net n is net list unit C ₁ Any one of a plurality of nets connected.

SS2: net array pos corresponding to net n _n Merging to netlist unit C ₁ Is a cell array pos.

SS3: jump to SS1 until netlist cell C ₁ All nets connected end the traversal.

SS4: all positions in the cell array pos are ordered in the x-direction and the y-direction, respectively.

SS5: taking the intermediate position (x) _mid ，y _mid ) As candidate locations for netlist cell C1; wherein x is _mid Represents the median position in the x-direction, y _mid Indicating the neutral position in the y-direction.

Illustratively, the location (x _mid ，y _mid ) Another 8 grids of the perimeter 3*3 grids are also used as candidate positions, resulting in a candidate position set.

The method (3) predicts the position based on the amount of shrinkage of the bounding box.

For any netlist cell, the line length reduction amount caused by cell movement of the netlist cell can be estimated based on the boundary frame shrinkage amount, and the position capable of shrinking the cell boundary frame area to the greatest extent in the current cell boundary frame area of the netlist cell is selected as the candidate position for cell movement of the netlist cell.

The candidate position calculation method can calculate in the x direction and the y direction respectively. Illustratively, taking the x-direction as an example, all nets connected by netlist cells may be traversed sequentially to obtain the range [ x ] of all nets in the x-direction _min ,x _max ]Then traversing all nets again, calculating the range to which the netlist cells move [x _min ,x _max ]Any position in the list unit brings the bounding box shrinkage to the current unit bounding box area of the netlist unit, the position corresponding to the largest bounding box shrinkage is determined, the position determination method in the y direction is similar to the position determination method in the x direction, and the candidate position can be determined through the position corresponding to the largest bounding box shrinkage in the x direction and the position corresponding to the largest bounding box shrinkage in the y direction. Likewise, a candidate location set may be obtained from another 8 grids of the candidate location perimeter 3*3 grids that also serve as candidate locations.

Specifically, after determining a set of candidate locations for any netlist cell, repositioning may be performed for the netlist cell, and illustratively, an attempt may be made to sequentially move each candidate location in the set of candidate locations, first removing the netlist cell from the initial routing paths of all nets to which it is connected, and placing it in any candidate location that is a target location, i.e., repositioning the netlist cell, i.e., determining a pre-optimized cell location for the netlist cell.

Specifically, because of the complex wire network connection relationship between the netlist units, after repositioning one netlist unit, the connected wire network needs to be re-routed, otherwise, accurate candidate positions cannot be obtained when the subsequent unit position prediction is performed, and in order to avoid the expense caused by frequently calling a routing tool, after repositioning any netlist unit, the netlist unit can be pre-routed, so that more accurate information is provided for the subsequent unit position prediction and evaluation. For example, different net reconnection algorithms may be employed to generate a new complete routing path for the netlist cell, i.e., to determine a pre-optimized routing path for the netlist cell, depending on the different net demolition conditions. As an example, if the remainder includes two or more communicating portions after the associated pin nodes of the netlist cells are removed from the nets to which they are connected, a multi-source multi-sink maze routing method may be used to reconnect the sub-tree to the pin nodes of the target site. As an example, after the relevant pin nodes of the netlist unit are removed from the net to which they are connected, if the remaining connection portions are connected, then the connection of the sub-tree to the target location may be performed again, i.e. the connection problem of multiple sources and single targets may be simplified, for example, the net reconnection may be performed using an a-algorithm.

Specifically, when all the associated net pre-routes of the netlist cells are finished, if no overflow occurs and the bus length reduction is greater than or equal to the set cell movement profit threshold, this candidate location of the netlist cells may be determined, the pre-optimized cell location of the netlist cells may be determined as the optimized cell location of the netlist cells, and the pre-optimized route path of the netlist cells may be determined as the optimized route path of the netlist cells. If overflow occurs or the decrease in bus length of the net of netlist cells is less than the set cell movement profit threshold, the position of the netlist cells can be restored to the initial cell position, the initial routing path of the netlist cells is restored, and the next candidate position is continuously tried.

When all netlist cell relocations are completed, an optimized layout result can be obtained, which includes optimized cell locations for a plurality of netlist cells.

Step S907: and (3) taking the optimized layout result as an initial layout result, and repeatedly executing the steps S903-S905 until the bus lengths of the nets of all the netlist units are converged.

The embodiment of the specification provides a layout and wiring optimizing device. Referring to fig. 9, the layout optimization device may include an initial routing result acquisition module 910, a target candidate location determination module 920, a candidate location set determination module 930, and a layout result optimization module 940.

An initial wiring result obtaining module 910, configured to obtain an initial wiring result; the initial routing result includes initial cell locations of the plurality of netlist cells and initial routing paths of the plurality of nets;

a target candidate position determining module 920, configured to determine, for any netlist unit, a target candidate position of the any netlist unit based on the initial unit position and the plurality of nets; the target candidate position is determined according to any one of the position of the compact unit, the position of the key node and the position corresponding to the target shrinkage of the boundary frame;

a candidate position set determining module 930, configured to determine a candidate position set of any netlist unit in a surrounding area of the target candidate position; wherein the candidate location set comprises a target candidate location and a candidate location for the target candidate location;

and the layout and wiring result optimizing module 940 is used for repositioning and pre-wiring any netlist unit according to the candidate position set and the initial wiring paths of the multiple nets to obtain an optimized wiring result.

The specific functions and effects achieved by the layout and wiring optimization device may be explained with reference to other embodiments of the present specification, and will not be described herein. The various modules in the floorplan optimization means may be implemented in whole or in part by software, hardware, and combinations thereof. The modules can be embedded in hardware or independent of a processor in the computer device, or can be stored in a memory in the computer device in a software mode, so that the processor can call and execute the operations corresponding to the modules.

In some implementations, the target candidate location determination module 920 may include a target candidate location first determination module, a target candidate location second determination module, and a target candidate location third determination module. The target candidate position first determining module is used for taking any netlist unit as a target netlist unit and determining the association degree of the target netlist unit and non-target netlist units in the multiple netlist units through a wire net corresponding to the target netlist unit; a target candidate position second determining module, configured to determine, according to the association degree, a compact unit of the target netlist unit from non-target netlist units in the multiple netlist units; and the third determining module of the target candidate position is used for taking the position of the compact unit as the target candidate position of the target netlist unit.

In some implementations, the target candidate location determination module 920 may include a target candidate location fourth determination module, a target candidate location fifth determination module, and a target candidate location sixth determination module. The fourth determining module of the target candidate position is used for taking any netlist unit as a target netlist unit and traversing nodes on initial wiring paths of a plurality of nets corresponding to the target netlist unit; a fifth determining module of the target candidate position is used for taking the pin node and the node with the node degree larger than the preset value as key nodes to obtain a key node set; the node degree represents the in-out number of the network connected by the node; and the sixth determination module is used for determining the target candidate position of the target netlist unit according to the positions of the key nodes in the key node set.

In some implementations, the target candidate location determination module 920 may include a target candidate location seventh determination module, a target candidate location eighth determination module, and a target candidate location ninth determination module. The seventh determining module is configured to determine a unit boundary frame area of the target netlist unit according to initial routing paths of a plurality of nets corresponding to the target netlist unit by using any netlist unit as the target netlist unit; the eighth determination module of the target candidate position is used for performing simulated movement on the target netlist unit in the unit boundary frame area and determining the boundary frame shrinkage corresponding to any position of the target netlist unit in the unit boundary frame area; and a ninth determination module for determining a target candidate position of the target netlist unit, wherein the target netlist unit reaches a position corresponding to the target shrinkage of the bounding box in the cell bounding box area, and the target candidate position is used as the target candidate position of the target netlist unit.

Referring to fig. 10, in some embodiments, a computer apparatus may be provided, including a memory and a processor, where the memory stores a computer program, and the processor implements the method for optimizing layout and wiring in the above embodiments when executing the computer program.

The present specification embodiment also provides a computer-readable storage medium having stored thereon a computer program which, when executed by a computer, causes the computer to perform the layout wiring optimization method in any of the above embodiments.

The present description also provides a computer program product containing instructions which, when executed by a computer, cause the computer to perform the method of optimizing layout wiring in any of the above embodiments.

In one embodiment, a computer device is provided, which may be a terminal, and an internal structure diagram thereof may be as shown in fig. 10. The computer device includes a processor, a memory, and a communication interface connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The communication interface of the computer device is used for carrying out wired or wireless communication with an external terminal, and the wireless mode can be realized through WIFI, an operator network, NFC (near field communication) or other technologies. The computer program, when executed by a processor, implements a method of layout optimization.

It will be appreciated that the specific examples herein are intended only to assist those skilled in the art in better understanding the embodiments of the present disclosure and are not intended to limit the scope of the present invention.

It should be understood that, in various embodiments of the present disclosure, the sequence number of each process does not mean that the execution sequence of each process should be determined by the function and the internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure.

It will be appreciated that the various embodiments described in this specification may be implemented either alone or in combination, and are not limited in this regard.

Unless defined otherwise, all technical and scientific terms used in the embodiments of this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this specification belongs. The terminology used in the description is for the purpose of describing particular embodiments only and is not intended to limit the scope of the description. The term "and/or" as used in this specification includes any and all combinations of one or more of the associated listed items. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It will be appreciated that the processor of the embodiments of the present description may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method embodiments may be implemented by integrated logic circuits of hardware in a processor or instructions in software form. The processor may be a general purpose processor, a Digital signal processor (Digital SignalProcessor, DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), an off-the-shelf programmable gate array (Field Programmable Gate Array, FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components. The methods, steps and logic blocks disclosed in the embodiments of the present specification may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method disclosed in connection with the embodiments of the present specification may be embodied directly in hardware, in a decoded processor, or in a combination of hardware and software modules in a decoded processor. The software modules may be located in a random access memory, flash memory, read only memory, programmable read only memory, or electrically erasable programmable memory, registers, etc. as well known in the art. The storage medium is located in a memory, and the processor reads the information in the memory and, in combination with its hardware, performs the steps of the above method.

It will be appreciated that the memory in the embodiments of this specification may be either volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The nonvolatile memory may be a read-only memory (ROM), a Programmable ROM (PROM), an Erasable Programmable ROM (EPROM), an Electrically Erasable Programmable ROM (EEPROM), or a flash memory, among others. The volatile memory may be Random Access Memory (RAM). It should be noted that the memory of the systems and methods described herein is intended to comprise, without being limited to, these and any other suitable types of memory.

Those of ordinary skill in the art will appreciate that the elements and algorithm steps described in connection with the embodiments disclosed herein can be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present specification.

It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described system, apparatus and unit may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.

In the several embodiments provided in this specification, it should be understood that the disclosed systems, apparatuses, and methods may be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiment.

In addition, each functional unit in each embodiment of the present specification may be integrated into one processing unit, each unit may exist alone physically, or two or more units may be integrated into one unit.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the present specification may be essentially or portions contributing to the prior art or portions of the technical solutions may be embodied in the form of a software product stored in a storage medium, including several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the embodiments of the present specification. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a read-only memory (ROM), a random-access memory (RAM), a magnetic disk, or an optical disk, etc.

The foregoing is merely specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope disclosed in the present disclosure, and should be covered by the scope of the present disclosure. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A method of optimizing a layout wiring, the method comprising:

acquiring an initial wiring result; the initial wiring result comprises initial unit positions of a plurality of netlist units and initial wiring paths of a plurality of nets;

determining target candidate positions of any netlist unit based on the initial unit positions and a plurality of wire nets for the any netlist unit; wherein the target candidate position is determined according to any one of the position of the compact unit, the position of the key node and the position corresponding to the target shrinkage of the boundary frame;

determining a candidate position set of any netlist unit in a peripheral area of the target candidate position; wherein the set of candidate locations includes the target candidate location and candidate locations for the target candidate location;

and repositioning and pre-wiring any netlist unit according to the candidate position set and the initial wiring paths of the multiple nets to obtain an optimized wiring result.

2. The method of layout and routing optimization of claim 1 wherein the target candidate locations for any netlist cell are determined by:

taking any one netlist unit as a target netlist unit, and determining the association degree of the target netlist unit and non-target netlist units in a plurality of netlist units through the wire nets corresponding to the target netlist units;

Determining compact units of the target netlist units from non-target netlist units in the netlist units according to the association degree;

and taking the position of the compact unit as the target candidate position of the target netlist unit.

3. The method of optimizing layout and routing according to claim 2, wherein said determining, through said net corresponding to said target netlist cell, a degree of association of said target netlist cell with a non-target netlist cell of a plurality of said netlist cells comprises:

traversing the net connected with the target netlist unit, and determining at least one non-target netlist unit connected with the target netlist unit;

determining, for any non-target netlist cell, a number of the nets between the target netlist cell and the any non-target netlist cell and a number of pin nodes of the nets;

and determining the association degree between the target netlist unit and any non-target netlist unit according to the number of the nets between the target netlist unit and the any non-target netlist unit and the number of pin nodes of the nets.

4. The method of layout and routing optimization of claim 1 wherein the target candidate locations for any netlist cell are determined by:

Taking any netlist unit as a target netlist unit, traversing nodes on initial wiring paths of a plurality of nets corresponding to the target netlist unit;

taking the pin nodes and the nodes with the node degree larger than a preset value as key nodes to obtain a key node set; the node degree represents the in-out number of the network connected by the node;

and determining the target candidate position of the target netlist unit according to the positions of the key nodes in the key node set.

5. The method of claim 4, wherein the determining the target candidate locations of the target netlist cells based on locations of key nodes in a set of key nodes comprises:

determining a first direction position set of key nodes in the key node set in a first direction and a second direction position set of key nodes in the key node set in a second direction according to the positions of the key nodes in the key node set;

determining a first direction median position and a second direction median position according to the first direction position set and the second direction position set;

and determining the target candidate position of the target netlist unit according to the first direction neutral position and the second direction neutral position.

6. The method of layout and routing optimization of claim 1 wherein the target candidate locations for any netlist cell are determined by:

taking any one netlist unit as a target netlist unit, and determining a unit boundary frame area of the target netlist unit according to initial wiring paths of a plurality of nets corresponding to the target netlist unit;

performing simulated movement on the target netlist unit in the unit boundary box area, and determining the boundary box shrinkage corresponding to any position of the target netlist unit in the unit boundary box area;

and taking the target netlist unit as the target candidate position of the target netlist unit, wherein the target netlist unit reaches the position corresponding to the target shrinkage of the boundary frame in the unit boundary frame area.

7. The method of optimizing place and route according to claim 1, wherein repositioning and pre-routing the cells of any netlist according to the candidate position set and the initial routing paths of the plurality of nets to obtain an optimized routing result comprises:

taking any candidate position in the candidate position set as a target position;

removing said netlist cells from the initial routing paths of the connected nets;

Repositioning the netlist unit to the target position to obtain a pre-optimized unit position;

pre-wiring the netlist unit according to a net reconnection algorithm to obtain a pre-optimized wiring path of the netlist unit aiming at the target position;

if it is determined that no wire overflow occurs and the unit movement benefit reaches a unit movement benefit threshold based on the pre-optimized unit position and the pre-optimized wire route, taking the pre-optimized unit position as an optimized unit position and the pre-optimized wire route as the optimized wire route; the cell movement benefit is the reduction of the bus length of all nets connected with the cells of any netlist.

8. The method according to claim 7, wherein if it is determined that a route overflow occurs based on the pre-optimized cell locations and the pre-optimized route paths and/or the cell movement benefit does not reach the cell movement benefit threshold, other candidate locations in the candidate location set are taken as the target locations to determine optimized cell locations and optimized route paths for the cells of the arbitrary netlist.

9. The method of optimizing layout wiring according to claim 1, characterized in that the method further comprises:

If the total movement income of the optimized wiring result is judged to not reach the convergence condition, the optimized wiring result is used as the initial wiring result, and the layout and wiring optimization is repeated; wherein the total movement benefit is a reduction in bus length of the net.

10. A layout wiring optimizing apparatus, characterized by comprising:

the initial wiring result acquisition module is used for acquiring an initial wiring result; the initial wiring result comprises initial unit positions of a plurality of netlist units and initial wiring paths of a plurality of nets;

a target candidate position determining module, configured to determine, for any netlist unit, a target candidate position of the any netlist unit based on the initial unit position and a plurality of nets; wherein the target candidate position is determined according to any one of the position of the compact unit, the position of the key node and the position corresponding to the target shrinkage of the boundary frame;

a candidate position set determining module, configured to determine a candidate position set of the any netlist unit in a surrounding area of the target candidate position; wherein the set of candidate locations includes the target candidate location and candidate locations for the target candidate location;

And the layout wiring result optimizing module is used for repositioning and pre-wiring any netlist unit according to the candidate position set and the initial wiring paths of the multiple nets to obtain an optimized wiring result.

11. The place and route optimization device of claim 10, wherein the target candidate location determination module comprises:

a target candidate position first determining module, configured to determine, by using the arbitrary netlist unit as a target netlist unit and through the net corresponding to the target netlist unit, a degree of association between the target netlist unit and non-target netlist units in the netlist units;

a target candidate position second determining module, configured to determine, according to the association degree, a compact unit of the target netlist unit from non-target netlist units in the netlist units;

and a third determining module of target candidate positions, configured to take the position of the compact unit as the target candidate position of the target netlist unit.

12. The place and route optimization device of claim 10, wherein the target candidate location determination module comprises:

a fourth determining module of a target candidate position, configured to traverse nodes on initial routing paths of a plurality of nets corresponding to the target netlist unit with the arbitrary netlist unit as the target netlist unit;

A fifth determining module of the target candidate position is used for taking the pin node and the node with the node degree larger than the preset value as key nodes to obtain a key node set; the node degree represents the in-out number of the network connected by the node;

and a sixth determining module of target candidate positions, configured to determine the target candidate positions of the target netlist unit according to positions of key nodes in the key node set.

13. The place and route optimization device of claim 10, wherein the target candidate location determination module comprises:

a seventh determining module of a target candidate position, configured to determine a cell bounding box area of the target netlist unit according to initial routing paths of a plurality of nets corresponding to the target netlist unit by using the arbitrary netlist unit as the target netlist unit;

a target candidate position eighth determining module, configured to perform simulated movement on the target netlist unit in the unit bounding box area, and determine a bounding box shrinkage amount corresponding to any position of the target netlist unit in the unit bounding box area;

and a ninth determination module of target candidate positions, configured to use, as the target candidate positions of the target netlist units, a position where the target netlist units reach a target shrinkage of a bounding box in the cell bounding box area.

14. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor implements the method of optimizing layout wiring of any of claims 1 to 9 when executing the computer program.

15. A computer-readable storage medium, on which a computer program is stored, characterized in that the computer program, when executed by a processor, implements the method of optimizing layout wiring as claimed in any one of claims 1 to 9.