CN105576042A - Manufacturing process of silica glass passivated bi-directional trigger tube chip - Google Patents
Manufacturing process of silica glass passivated bi-directional trigger tube chip Download PDFInfo
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- CN105576042A CN105576042A CN201610099262.7A CN201610099262A CN105576042A CN 105576042 A CN105576042 A CN 105576042A CN 201610099262 A CN201610099262 A CN 201610099262A CN 105576042 A CN105576042 A CN 105576042A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 32
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 title abstract description 7
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 41
- 239000010703 silicon Substances 0.000 claims abstract description 41
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 38
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 27
- 230000003647 oxidation Effects 0.000 claims abstract description 26
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 24
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 24
- 239000011574 phosphorus Substances 0.000 claims abstract description 24
- 238000009792 diffusion process Methods 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims description 52
- 239000011521 glass Substances 0.000 claims description 36
- 238000002161 passivation Methods 0.000 claims description 20
- 239000007788 liquid Substances 0.000 claims description 14
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 12
- 238000005260 corrosion Methods 0.000 claims description 12
- 230000007797 corrosion Effects 0.000 claims description 12
- 239000000126 substance Substances 0.000 claims description 12
- 239000001301 oxygen Substances 0.000 claims description 9
- 229910052760 oxygen Inorganic materials 0.000 claims description 9
- 239000011241 protective layer Substances 0.000 claims description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 239000000956 alloy Substances 0.000 claims description 6
- 229910045601 alloy Inorganic materials 0.000 claims description 6
- 238000000576 coating method Methods 0.000 claims description 6
- 239000003292 glue Substances 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 238000007747 plating Methods 0.000 claims description 6
- 239000010410 layer Substances 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 3
- 239000000428 dust Substances 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims description 3
- 239000001257 hydrogen Substances 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 238000000926 separation method Methods 0.000 claims description 3
- 238000010301 surface-oxidation reaction Methods 0.000 claims description 3
- 238000009713 electroplating Methods 0.000 abstract 1
- 238000005530 etching Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 150000003376 silicon Chemical class 0.000 description 3
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 229960000583 acetic acid Drugs 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 238000007596 consolidation process Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000003912 environmental pollution Methods 0.000 description 1
- 239000012362 glacial acetic acid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 238000004062 sedimentation Methods 0.000 description 1
- 239000000741 silica gel Substances 0.000 description 1
- 229910002027 silica gel Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8611—Planar PN junction diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3178—Coating or filling in grooves made in the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66121—Multilayer diodes, e.g. PNPN diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66128—Planar diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66136—PN junction diodes
Abstract
The invention discloses a manufacturing process of a silica glass passivated bi-directional trigger tube chip. The manufacturing process comprises the following steps: (S101) selecting the type of a silicon wafer; (S201) carrying out phosphorus diffusion on the selected silicon wafer, so as to form an N<+> region; (S301) carrying out oxidation treatment on the element after the phosphorus diffusion; (S401) selectively etching the element after the oxidation treatment; (S501) slotting the selectively etched element; (S601) forming a protecting layer in a slot of the slotted element; and (S701) carrying out electroplating on the element with the protecting layer, so as to form an electrode. According to the manufacturing process, the production process can be simplified, the electric leakage is reduced, and the thermal stability and the volt-ampere characteristics of devices are improved.
Description
Technical field
The invention belongs to chip manufacturing field, particularly a kind of silicon-based glass passivation two-way trigger tube chip manufacturing process.
Background technology
At present, bidirectional trigger diode experienced by roughly two processes in the evolution of decades:
One, use the planar technique of silicon device to make this device, there is following drawback:
1: complex process.2: electric leakage is large, the thermally-stabilised difference of device.3: voltage-current characteristic is bad.
Two, the mesa technique utilizing white glue to protect makes this device, there is following drawback:
1: electric leakage is large, the thermally-stabilised difference of device.2: production process environmental pollution is serious.
Many drawbacks that above two kinds of techniques exist.Particularly element leakage is large, and thermo qualitative difference is above two technique institute general character.Also be self defective workmanship impossible gone beyond.
Therefore, need now a kind of silicon-based glass passivation two-way trigger tube chip manufacturing process badly, can simplify production technology, reduction is leaked electricity and is improved thermal stability and the voltage-current characteristic of device.
Summary of the invention
The present invention proposes a kind of silicon-based glass passivation two-way trigger tube chip manufacturing process, solves that complex process in prior art, electric leakage are serious, the problem of device thermal stability and voltage-current characteristic difference.
Technical scheme of the present invention is achieved in that the two-way flip chip manufacturing process of silicon-based glass passivation, comprises the steps,
S101: select silicon chip type;
S201: phosphorus diffusion process is carried out to the silicon chip after selecting, forms N
+district;
S301: oxidation processes is carried out to the element after phosphorus diffusion process;
S401: selective etch is carried out to the element after oxidation processes;
S501: slot treatment is carried out to the element after selective etch;
S601: form protective layer in the member slot after slot treatment;
S701: plating forms electrode on the element forming protective layer.
As one preferred embodiment, be also provided with step S801 after described step S701: carry out scribing separation to forming the element of electrode after plating, in scribing processes, feed velocity controlled in 5-6mm/ second.
As one preferred embodiment, described step S101 silicon chip type is P-type silicon sheet, its electricalresistivityρ=0.10-0.14 Ω/CM, thickness 165 ± 5 microns.
As one preferred embodiment, the phosphorus diffusion process in described step S201 comprises carries out phosphorus diffusion process to two surfaces of silicon chip simultaneously, forms N
+district, the temperature of phosphorus diffusion process controls more than 1250 DEG C, and the phosphorus diffusion process time is 20-23 hour.In
As one preferred embodiment, in described step S301, oxidation processes specifically comprises: the element surface growth thickness after phosphorus diffusion process is the oxide layer of 0.8 micron to 1.2 microns, during oxidation, temperature controls more than 1180 DEG C, time 4-6 hour, first dry-oxygen oxidation is carried out in oxidizing process, carry out wet-oxygen oxidation again, finally carry out dry-oxygen oxidation.
As one preferred embodiment, in described step S401, selective etch comprises and carries out even glue and exposure to the two-sided of element after oxidation processes, forms selective etch region.
As one preferred embodiment, described slot treatment utilizes chemical corrosion liquid to slot, and forms mesa structure, leaves standstill more than 48 hours, and utilize the temperature of Dynamic controlling chemical corrosion liquid before chemical corrosion liquid uses.
As one preferred embodiment, described step S601 is included in coating glass dust in groove and sinters, and forms protective layer.
As one preferred embodiment, form electrode in described step S701 specifically to comprise and once form secondary after nickel electrode, alloy treatment and form nickel electrode.
As one preferred embodiment, make large nitrogen do protection gas in described alloy treatment process, flow control is 15 liters/min, passes into the hydrogen of 150 ml/min simultaneously, prevents surface oxidation.
After have employed technique scheme, the invention has the beneficial effects as follows: this silicon-based glass passivation two-way trigger tube chip manufacturing process adopts glassivation mode to protect table top, make use of the good heat resistance of glass and good insulating properties simultaneously, the glass coating method staticly settled and the method adopting vacuum condition to carry out sintered glass ensure that the glassy layer that the compactness of glassivation is obviously better than commonsense method and is formed, thus reduce electric leakage, the thermal endurance of device and reliability are significantly improved, manufacturing process is simple, avoid the pollution to environment in manufacture process, the method of chemical corrosion liquid slot treatment is utilized to ensure that the effect of the rotten sheet of ultrathin in addition.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is process flow diagram of the present invention;
Fig. 2 is the schematic diagram of the process of two-sided expansion phosphorus and selective etch in Fig. 1;
Fig. 3 is the schematic diagram that slot treatment in Fig. 1, glassivation and silicon chip are separated;
Fig. 4 is the situation table of comparisons of present invention process and common process.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
As shown in Figure 1-Figure 3, the two-way flip chip manufacturing process of this silicon-based glass passivation comprises the steps:
S101: select silicon chip type;
S201: phosphorus diffusion process is carried out to the silicon chip after selecting, forms N
+district;
S301: oxidation processes is carried out to the element after phosphorus diffusion process;
S401: selective etch is carried out to the element after oxidation processes;
S501: slot treatment is carried out to the element after selective etch;
S601: form protective layer in the member slot after slot treatment;
S701: plating forms electrode on the element forming protective layer.
Concrete, be also provided with step S801 after step S701: carry out scribing separation to the element forming electrode after plating, in scribing processes, feed velocity controlled in 5-6mm/ second.
Step S101 silicon chip type is P-type silicon sheet, its electricalresistivityρ=0.10-0.14 Ω/CM, thickness 165 ± 5 microns.
Phosphorus diffusion process in step S201 comprises carries out phosphorus diffusion process to two surfaces of silicon chip simultaneously, forms N
+district, the temperature of phosphorus diffusion process controls more than 1250 DEG C, and the phosphorus diffusion process time is 20-23 hour.
In step S301, oxidation processes specifically comprises: the element surface growth thickness after phosphorus diffusion process is the oxide layer of 0.8 micron to 1.2 microns, during oxidation, temperature controls more than 1180 DEG C, time 4-6 hour, first dry-oxygen oxidation is carried out in oxidizing process, carry out wet-oxygen oxidation again, finally carry out dry-oxygen oxidation.
In step S401, selective etch adopts photoengraving, comprises and carries out even glue and exposure to the two-sided of element after oxidation processes, forms selective etch region.
Slot treatment utilizes chemical corrosion liquid to slot (abbreviationization corruption fluting), and form mesa structure, should leave standstill more than 48 hours, and utilize the temperature of Dynamic controlling chemical corrosion liquid at chemical corrosion liquid, chemical corrosion liquid uses nitric acid; Hydrofluoric acid: glacial acetic acid: the mixed liquor of phosphoric acid, leave standstill and can use for more than 48 hours, in use procedure, the temperature of liquid is Dynamic controlling, and generally, liquid rises to 15 DEG C by-10 DEG C and lasts ten minutes.
Step S601 is included in coating glass dust in groove and sinters, and forms protective layer, and for ensureing the densification of glass, this technique have employed glass and staticly settles method, makes glass natural sedimentation at silicon chip surface, then wipes unnecessary powder with silica gel block.The sintering process of glass employs vacuum condition, and in conjunction with the consolidation process of glass, control negative pressure height to reach the requirement of glass compactness, process is called for short glassivation.
Form electrode in step S701 specifically to comprise and once form secondary after nickel electrode, alloy treatment and form nickel electrode.
Make large nitrogen do protection gas in alloy treatment process, flow control is 15 liters/min, passes into the hydrogen of 150 ml/min simultaneously, prevents surface oxidation.
It is to be noted as ensureing that device parameters △ V is greater than 8V.The thickness of the p type island region in the middle of this device must control at 35-40 μm, and the pn of both sides knot must be disconnected when changing rotten fluting, and namely real residual silicon wafer thickness is necessarily less than the thickness of p type island region, generally at 30-35 μm.By whole φ 76mm silicon chip, corrode into the thin slice of a common blank sheet of paper half thickness.There is suitable difficulty.Glass passivation process is own extensive use in semicon industry domestic at present, but this technique is used on the broad silicon chip of blank sheet of paper one half thickness, traditional process cannot meet at all, this programme provides a set of operational version being different from conventional method, glass passivation process is transplanted on the type product, improves sintering condition simultaneously, make glass fine and close, electric leakage significantly reduces, thus this device can be made to have good reliability.
Please refer to Fig. 4, after adopting this manufacturing process, all many-sides are with fork-like farm tool used in ancient China improvement, and especially normal temperature electric leakage and high temperature electric leakage, bring the raising of matter.The main distinction of above three kinds of technology modes protects exposed pn knot by diverse ways and different materials.The first planar technique mode is by high-temperature oxydation growth silicon dioxide film, pn knot is protected and expands, due to silicon dioxide film self character, determine the drawback that its electric leakage is larger, and production process is quite high to the requirement of environment, very easily cause product rejection because environment degree of purity makes not the coating mass that grows not good enough.The second white glue technique is when when this product is by international vendors corner on the market, the one of compatriots' invention for treating scheme, respite this product market supply at home, but the characteristic of white glue determines the quality of this product.It is a kind of makeshift.The situation that domestic market is monopolized just thoroughly has been reversed in the appearance of the third glassivation.Through effort in recent years, this product at home market account for absolute predominance, and turns to international market to supply.
This silicon-based glass passivation two-way trigger tube chip manufacturing process: adopt glassivation mode to protect table top, make use of good heat resistance and the insulating properties of glass simultaneously, the glass coating method staticly settled and the method adopting vacuum condition to carry out sintered glass ensure that the compactness of glassivation is obviously better than the glassy layer of commonsense method institute shape war, thus reduce electric leakage, the thermal endurance of device and reliability are significantly improved, manufacturing process is simple, avoid the pollution to environment in manufacture process, the method of chemical corrosion liquid slot treatment is utilized to ensure that the effect of the rotten sheet of ultrathin in addition.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. the two-way flip chip manufacturing process of silicon-based glass passivation, is characterized in that, comprise the steps,
S101: select silicon chip type;
S201: phosphorus diffusion process is carried out to the silicon chip after selecting, forms N
+district;
S301: oxidation processes is carried out to the element after phosphorus diffusion process;
S401: selective etch is carried out to the element after oxidation processes;
S501: slot treatment is carried out to the element after selective etch;
S601: form protective layer in the member slot after slot treatment;
S701: plating forms electrode on the element forming protective layer.
2. the two-way flip chip manufacturing process of silicon-based glass passivation according to claim 1, it is characterized in that, also be provided with step S801 after described step S701: carry out scribing separation to forming the element of electrode after plating, in scribing processes, feed velocity controlled in 5-6mm/ second.
3. the two-way flip chip manufacturing process of silicon-based glass passivation according to claim 1, is characterized in that, described step S101 silicon chip type is P-type silicon sheet, its electricalresistivityρ=0.10-0.14 Ω/CM
2, thickness 165 ± 5 microns.
4. the two-way flip chip manufacturing process of silicon-based glass passivation according to claim 1, is characterized in that, the phosphorus diffusion process in described step S201 comprises carries out phosphorus diffusion process to two surfaces of silicon chip simultaneously, forms N
+district, the temperature of phosphorus diffusion process controls more than 1250 DEG C, and the phosphorus diffusion process time is 20-23 hour.
5. the two-way flip chip manufacturing process of silicon-based glass passivation according to claim 1, it is characterized in that, in described step S301, oxidation processes specifically comprises: the element surface growth thickness after phosphorus diffusion process is the oxide layer of 0.8 micron to 1.2 microns, during oxidation, temperature controls more than 1180 DEG C, time 4-6 hour, in oxidizing process, first carry out dry-oxygen oxidation, then carry out wet-oxygen oxidation, finally carry out dry-oxygen oxidation.
6. the two-way flip chip manufacturing process of silicon-based glass passivation according to claim 1, is characterized in that, in described step S401, selective etch comprises and carries out even glue and exposure to the two-sided of element after oxidation processes, forms selective etch region.
7. the two-way flip chip manufacturing process of silicon-based glass passivation according to claim 1, it is characterized in that, described slot treatment utilizes chemical corrosion liquid to slot, and forms mesa structure, chemical corrosion liquid leaves standstill more than 48 hours, and utilizes the temperature of Dynamic controlling chemical corrosion liquid.
8. the two-way flip chip manufacturing process of silicon-based glass passivation according to claim 1, is characterized in that, described step S601 is included in coating glass dust in groove and sinters, and forms protective layer.
9. the two-way flip chip manufacturing process of silicon-based glass passivation according to claim 1, is characterized in that, forms electrode and specifically comprise and once form secondary after nickel electrode, alloy treatment and form nickel electrode in described step S701.
10. the two-way flip chip manufacturing process of silicon-based glass passivation according to claim 9; it is characterized in that, make large nitrogen do protection gas in described alloy treatment process, flow control is 15 liters/min; pass into the hydrogen of 150 ml/min simultaneously, prevent surface oxidation.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109461767A (en) * | 2018-10-25 | 2019-03-12 | 深圳市金鑫城纸品有限公司 | A kind of super-junction structure and preparation method thereof |
| CN114843180A (en) * | 2022-05-03 | 2022-08-02 | 江苏晟驰微电子有限公司 | Chemical corrosion junction removing equipment and process for manufacturing rectifier tube |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3907615A (en) * | 1968-06-28 | 1975-09-23 | Philips Corp | Production of a three-layer diac with five-layer edge regions having middle region thinner at center than edge |
| CN101651102A (en) * | 2009-08-25 | 2010-02-17 | 南通明芯微电子有限公司 | Bidirectional trigger diode chip production method |
| CN102244104A (en) * | 2011-07-07 | 2011-11-16 | 重庆平伟实业股份有限公司 | Flat and lug combined bidirectional diode chip and manufacturing process thereof |
| CN103956324A (en) * | 2014-04-30 | 2014-07-30 | 天津中环半导体股份有限公司 | Production technology for transient voltage suppressor chip with channeling effect |
-
2016
- 2016-02-23 CN CN201610099262.7A patent/CN105576042B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3907615A (en) * | 1968-06-28 | 1975-09-23 | Philips Corp | Production of a three-layer diac with five-layer edge regions having middle region thinner at center than edge |
| CN101651102A (en) * | 2009-08-25 | 2010-02-17 | 南通明芯微电子有限公司 | Bidirectional trigger diode chip production method |
| CN102244104A (en) * | 2011-07-07 | 2011-11-16 | 重庆平伟实业股份有限公司 | Flat and lug combined bidirectional diode chip and manufacturing process thereof |
| CN103956324A (en) * | 2014-04-30 | 2014-07-30 | 天津中环半导体股份有限公司 | Production technology for transient voltage suppressor chip with channeling effect |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109461767A (en) * | 2018-10-25 | 2019-03-12 | 深圳市金鑫城纸品有限公司 | A kind of super-junction structure and preparation method thereof |
| CN109461767B (en) * | 2018-10-25 | 2022-03-29 | 深圳市金鑫城纸品有限公司 | Manufacturing method of super junction structure |
| CN114843180A (en) * | 2022-05-03 | 2022-08-02 | 江苏晟驰微电子有限公司 | Chemical corrosion junction removing equipment and process for manufacturing rectifier tube |
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