CN103151332A - ONO (SiO2-Si3N4-SiO2) antifuse unit structure and preparation method thereof - Google Patents
ONO (SiO2-Si3N4-SiO2) antifuse unit structure and preparation method thereof Download PDFInfo
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Abstract
The invention relates to an ONO (SiO2-Si3N4-SiO2) antifuse unit structure and a preparation method thereof, which belong to the technical field of micro-electronics. According to the technical scheme provided by the invention, the ONO antifuse unit structure comprises a lower electrode plate, wherein the lower electrode plate comprises a substrate, and field oxide and a N+ diffusion zone are formed on the upper part of the substrate; an antifuse hole which penetrates through an injection masking layer and a corrosion masking layer is formed just above the N+ diffusion zone, the injection masking layer covers the N+ diffusion zone and the field oxide on the upper part of the substrate, and the corrosion masking layer covers the injection masking layer; an ONO dielectric layer is formed on the corrosion masking layer, the ONO dielectric layer covers the corrosion masking layer and is filled in the antifuse hole, and the ONO dielectric layer comes into contact with the N+ diffusion zone at the bottom of the antifuse hole; and an upper electrode plate covers the ONO dielectric layer. The ONO antifuse unit structure and the preparation method have the advantages of simple processing step, good process compatibility, safety and reliability, the uniformity of fuse unit breakdown voltage can be improved, and the programming time and the fuse on-resistance after programming are reduced.
Description
Technical field
The present invention relates to a kind of antifuse unit structure and preparation method, especially a kind of ONO antifuse unit structure and preparation method thereof belongs to microelectronic technical field.
Background technology
Anti-fuse storage unit is natural radioresistance assembly, have non-volatile, high reliability, volume is little, speed is fast, the advantage such as low in energy consumption, at present, anti-fuse technique has had application extremely widely in fields such as computer, communication, automobile, satellite and Aero-Space.Antifuse unit structure is sandwich structure, mainly is made of upper/lower electrode and the anti-fuse dielectric layer that is between upper/lower electrode, and its dielectric layer kind is various: SiO
2(as patent US.pat.NO.4543594), Si
3N
4(as patent US.pat.NO.3423646), amorphous silicon (as patent US.pat.NO.4499557), SiO
2/ Si
3N
4/ SiO
2-ONO composite films (as patent US.pat.NO.4943538) etc. are selected corresponding dielectric layer according to different demands.When not programming, anti-fuse cell performance high-impedance state can be up to 10
10Ohm, after adding the suitable voltage programming between upper/lower electrode, anti-fuse shows good Ohmic resistance characteristic.
Affect the anti-fuse storage unit reliability of structure of ONO factor a lot, as bottom oxide layer (tunnel oxidation layer), Si
3N
4, the coating growth technique such as top layer oxide layer, the techniques such as anti-fuse pitting corrosion.Patent US.pat.NO.6307248 adopts plain layer polysilicon film as the masking layer of anti-fuse hole window, than traditional Si
3N
4More easily control the sidewall pattern in anti-fuse hole with photoresist, reduced the impact of pitting corrosion technique on anti-fuse storage unit reliability.
Summary of the invention
The objective of the invention is to overcome the deficiencies in the prior art, a kind of ONO antifuse unit structure and preparation method thereof is provided, its processing step is simple, can improve the uniformity of fuse cell puncture voltage, reduce the rear fuse conducting resistance of programming time and programming, processing compatibility is good, and is safe and reliable.
According to technical scheme provided by the invention, described ONO antifuse unit structure comprises lower electrode plate, and described lower electrode plate comprises substrate, and the top of described substrate is provided with an oxygen and N+ diffusion region; Arrange directly over described N+ diffusion region and connect the anti-fuse hole of injecting masking layer and corrosion masking layer, described injection masking layer covers on the N+ diffusion region and an oxygen on substrate top, and the corrosion masking layer is covered in and injects on masking layer; On described corrosion masking layer, the ono dielectric layer is set, described ono dielectric layer covers on the corrosion masking layer, and is filled in anti-fuse hole, and the N+ diffusion region of ono dielectric layer bottom anti-fuse hole contacts, and is coated with electric pole plate on the ono dielectric layer.
Described corrosion masking layer is amorphous silicon layer, and the injection masking layer is silicon dioxide layer.
A kind of preparation method of ONO antifuse unit structure, the preparation method of described antifuse unit structure comprises the steps:
A, provide substrate, and make required field oxygen and active area on described substrate;
B, thermal oxide growth injects masking layer on above-mentioned substrate;
C, utilization are injected masking layer and inject the N-type ion on substrates, to obtain the N+ diffusion region on substrate;
D, injecting deposit corrosion masking layer on masking layer, and etching corrosion masking layer and inject masking layer and obtain anti-fuse hole, described anti-fuse hole connects the corrosion masking layer and injects masking layer, contacts with the N+ diffusion region at the bottom of the hole in anti-fuse hole;
E, above-mentioned substrate is carried out tunnel oxidation clean;
F, utilize low-pressure oxidized technique growth tunnel oxidation layer, described tunnel oxidation layer covers on the corrosion masking layer, and covers sidewall and the diapire in anti-fuse hole;
G, adopt the silicon nitride film of LPCVD deposit richness-N on above-mentioned tunnel oxidation layer;
H, above-mentioned silicon nitride film layer is carried out high-temperature oxydation, obtain the top layer oxide layer;
I, on the top layer oxide layer deposit top electrode.
Described step a comprises the steps:
A1, at Grown
The first silicon dioxide layer;
A2, on above-mentioned the first silicon dioxide layer the deposit silicon nitride layer, the thickness of described silicon nitride layer is
The first silicon dioxide layer and silicon nitride layer on a3, the above-mentioned substrate of photoetching are to make required active area;
A4, utilize above-mentioned silicon nitride layer to be masking layer, thermal oxidation production
The second silicon dioxide layer, with obtain being positioned on substrate the field oxygen;
The first silicon dioxide layer and the silicon nitride layer of a5, oxygen inboard, the above-mentioned field of removal.
In described step c, during described injection N-type ion, first inject the P ion, the As ion that reinjects, wherein, the P/As implantation dosage is: 1.0E15～7.0E15/cm
2, the P/As Implantation Energy is: 50～80kev, the annealing process temperature is 900～1050 ℃, degeneration atmosphere N
2
In described steps d, the corrosion masking layer is amorphous silicon layer, and the thickness of corrosion masking layer is
The temperature of deposit corrosion masking layer is 490～580 ℃, and pressure is 250～450mtorr.
In described step f, the pressure 50～100torr of described growth tunnel oxidation layer (16), O
2Flow control is at 8～15SLM, and temperature is 680～820 ℃, and directly over N+ diffusion region (13), the thickness of tunnel oxidation layer (16) is
In described step g, the pressure of LPCVD deposition silicon nitride film is 250～450mtorr, DCS:NH
3=1:5～1:10, technological temperature are 680～780 ℃, Si
3N
4Thicknesses of layers is
In described step h, adopt the wet-oxygen oxidation growth to obtain
The top layer oxide layer, temperature is 900～1050 ℃; And employing N
2O annealing, N
2O annealing process pressure 50～100torr, 800～900 ℃ of technological temperatures.
The thickness of described electric pole plate is 3000～5000A polysilicon layer, and passes through POCL
3Doping, the sheet resistance that makes electric pole plate is 20～27 Ω/.
Advantage of the present invention: adopt thickness stability and the interior uniformity of disk of low-pressure oxidized technology controlling and process tunnel oxidation layer, adopt the fixedly injection sequencing of P/As ion, be controlled at the technology stability of the tunnel oxidation layer of bottom crown N+ diffusion region growth.Adopt and regulate DCS and NH
3Ratio, make the silicon nitride film in ONO have richness-N, reduce programming time, improve the uniformity of fuse cell puncture voltage in silica-based disk.Amorphous silicon layer is as the corrosion masking layer in anti-fuse hole, in order to control better the sidewall pattern in anti-fuse hole.Adopt low pressure N
2O annealing reduces the defective that produces because of dangling bonds in the top layer oxide layer, improves fuse cell puncture voltage uniformity.
The present invention utilizes N under hot conditions
2The oxygen atom that O decomposes can shift out the N with dangling bonds the top oxide layer, helps like this to strengthen the compactness of top layer oxide layer.Adopt industry device making technics flow process commonly used, compatible with the MOS technological process, technique is simple, controlled.With the ONO anti-fuse structures of routine relatively, have advantages of fuse cell puncture voltage good uniformity, programming time and programming after the fuse conducting resistance low.
Description of drawings
Fig. 1～Fig. 3 is the concrete implementing process step of the present invention cutaway view, wherein
Fig. 1 is the cutaway view after the present invention obtains anti-fuse hole.
Fig. 2 is the cutaway view after the present invention obtains the top layer oxide layer.
Fig. 3 is the cutaway view after the present invention obtains electric pole plate.
Description of reference numerals: 11-substrate, 12-field oxygen, 13-N+ diffusion region, 14-inject masking layer, 15-corrosion masking layer, 16-tunnel oxidation layer, 17-silicon nitride film, 18-top layer oxide layer, 19-electric pole plate and the anti-fuse of 20-hole.
Embodiment
The invention will be further described below in conjunction with concrete drawings and Examples.
As shown in Figure 3: for fuse conducting resistance after puncture voltage uniformity, reduction programming time and the programming that can optimize anti-fuse cell, the present invention includes lower electrode plate, described lower electrode plate comprises substrate 11, and the top of described substrate 11 is provided with an oxygen 12 and N+ diffusion region 13; Anti-fuse hole 20 that connect to inject masking layer 14 and corrosion masking layer 15 is set directly over described N+ diffusion region 13, and described injection masking layer 14 covers on the N+ diffusion region 13 and an oxygen 12 on substrate 11 tops, and corrosion masking layer 15 is covered in and injects on masking layer 14; On described corrosion masking layer 15, the ono dielectric layer is set, described ono dielectric layer covers on corrosion masking layer 15, and is filled in anti-fuse hole 20, and the N+ diffusion region 13 of ono dielectric layer and 20 bottoms, anti-fuse hole contacts, and is coated with electric pole plate 19 on the ono dielectric layer.
Particularly, described ono dielectric layer comprises the tunnel oxidation layer 16 of bottom, be covered in the silicon nitride film 17 on described tunnel oxidation layer 16 and be covered in top layer oxide layer 18 on described silicon nitride film 17, injecting masking layer 14 be silicon dioxide layer, and corroding masking layer 15 is amorphous silicon layer.
As Fig. 1～shown in Figure 3: the ONO antifuse unit structure of said structure, can prepare by following processing step, described preparation technology comprises following concrete steps:
A, provide substrate 11, and make required field oxygen 12 and active area on described substrate 11;
Wherein, described step a comprises the steps:
A1, growth on substrate 11
The first silicon dioxide layer; Described substrate 11 is silicon substrate, and the crystalline phase of substrate 11 is＜100 〉;
A2, on above-mentioned the first silicon dioxide layer the deposit silicon nitride layer, the thickness of described silicon nitride layer is
In the embodiment of the present invention, the first silicon dioxide layer and the silicon nitride layer all technique by routine are prepared and obtain.
The first silicon dioxide layer and silicon nitride layer on a3, the above-mentioned substrate 11 of photoetching are to make required active area;
A4, utilize above-mentioned silicon nitride layer to be masking layer, thermal oxidation production
The second silicon dioxide layer, with obtain being positioned on substrate 11 the field oxygen 12; Isolate by the active area on 12 pairs of substrates 11 of field oxygen, be the routine techniques means of the art.
The first silicon dioxide layer and the silicon nitride layer of a5, oxygen 12 inboards, the above-mentioned field of removal.Namely remove the first silicon dioxide layer and silicon nitride layer on active area, in order to active area is carried out follow-up operation.
B, thermal oxide growth injects masking layer 14 on above-mentioned substrate 11;
In the embodiment of the present invention, described injection masking layer 14 is silicon dioxide layer, and the thickness that injects masking layer 14 is
Injecting masking layer 14 covers on oxygen 12 on the scene and active area;
C, utilize to inject masking layer 14 inject the N-type ion on substrate 11, to obtain N+ diffusion region 13 on substrate 11;
In the embodiment of the present invention, when injecting the N-type ion, need to apply photoresist injecting on masking layer 14, then corresponding region on the photoetching active area, to carry out required Implantation, inject masking layer 14 and photoresist sheltering as Implantation; During described injection N-type ion, first inject the P ion, the As ion that reinjects, wherein, the P/As implantation dosage is: 1.0E15～7.0E15/cm
2, the P/As Implantation Energy is: 50～80kev, the annealing process temperature is 900～1050 ℃, degeneration atmosphere N
2, annealing time is 30～60 minutes, activates implanted dopant, forms N+ diffusion region 13.In the embodiment of the present invention, 13 impedances that can reduce lower electrode plate in the interior formation of substrate 11 N+ diffusion region.
D, injecting deposit corrosion masking layer 15 on masking layer 14, and etching corrosion masking layer 15 and inject masking layer 14 and obtain anti-fuse hole 20, described anti-fuse hole 20 connects corrosion masking layers 15 and injects masking layer 14, contacts with N+ diffusion region 13 at the bottom of the hole in anti-fuse hole 20;
In the embodiment of the present invention, corrosion masking layer 15 is amorphous silicon layer, and the thickness of corrosion masking layer 15 is
The temperature of deposit corrosion masking layer 15 is 490～580 ℃, and pressure is 250～450mtorr(millitorr).When the anti-fuse of etching hole 20, need to apply photoresist on corrosion masking layer 15, then photoetching photoresist, the position that forms anti-fuse hole 20 at needs obtains etching window, utilize etching window and to inject masking layer 14 and to carry out etching corrosion masking layer 15, obtain anti-fuse hole 20, obtaining the anti-fuse hole 20 above-mentioned photoresists of rear removal.In the embodiment of the present invention, with the masking layer technique of amorphous silicon layer as 20 corrosion of anti-fuse hole, more help the sidewall pattern in anti-fuse hole 20 to control than conventional lithography glue.Obtain behind anti-fuse hole 20 structure as shown in Figure 1.
E, above-mentioned substrate 11 is carried out tunnel oxidation clean;
In the embodiment of the present invention, needed to clean, wherein before preparation ono dielectric layer, at first will carry out SPM and APM cleans, then adopting concentration is natural oxidizing layer at the bottom of 0.5%～2% HF solution floats 20 holes, anti-fuse hole, and therefore, described step e comprises the steps:
E1, utilizing the SPM(Surfuric/Peroxide Mix of 90～140 ℃) solution cleaned 3～10 minutes, and wherein, SPM solution is H
2SO
4With H
2O
2Mixed liquor, H
2SO4 and H
2The O2 volume ratio is 3:1～4:1, H
2SO4 concentration is 96%～98%, H
2O
2Concentration is 30%～32%;
E2,40～80 ℃ of APM(Ammonia/Peroxide Mix of recycling) cleaned 5～15 minutes in cleaning fluid, wherein, APM solution is NH
4OH, H
2O
2And H
2The O mixed liquor, NH
4OH, H
2O
2And H
2The volume ratio of O is NH
4OH:H
2O
2: H
2O=1:20:70～1:2:7, H
2SO4 concentration is 96%～98%, H
2O2 concentration is 30%～32%, NH
4OH concentration is 30%～33%;
E3, to utilize concentration be natural oxidizing layer at the bottom of 0.5%～2%HF solution floats 20 holes, anti-fuse hole.
F, utilize low-pressure oxidized technique growth tunnel oxidation layer 16, described tunnel oxidation layer 16 covers on corrosion masking layer 15, and covers sidewall and the diapire in anti-fuse hole 20;
Complete after above-mentioned tunnel oxidation cleans, need do immediately tunnel oxidation technique, fast because of process rate if when adopting tunnel oxidation layer 16 at the bottom of normal pressure technique growth hole, easily cause technology controlling and process unstable; Therefore, in the embodiment of the present invention, adopt low-pressure oxidized technique to make tunnel oxidation layer 16, can help to reduce oxidation rate, and oxide layer is finer and close, simultaneously, in more easy to control, the uniformity between sheet, between stove.In the embodiment of the present invention, the pressure 50～100torr of described growth tunnel oxidation layer 16, O
2Flow control is at 8～15SLM(Standard Liters per Minute), temperature is 680～820 ℃, directly over N+ diffusion region 13, the thickness of tunnel oxidation layer 16 is
G, adopt the silicon nitride film 17 of LPCVD deposit richness-N on above-mentioned tunnel oxidation layer 16;
After completing the technique of tunnel oxidation layer 16, need to adopt immediately the LPCVD(low-pressure chemical vapor deposition on tunnel oxidation layer 16) silicon nitride film 17 of deposit one deck richness-N, the pressure of technique is 250～450mtorr, DCS:NH
3=1:5～1:10, technological temperature are 680～780 ℃, Si
3N
4Thicknesses of layers is
H, above-mentioned silicon nitride film layer 17 is carried out high-temperature oxydation, obtain top layer oxide layer 18;
Adopt the high temperature thermal oxidation metallization processes to carry out thermal oxidation to above-mentioned silicon nitride film 17, form top oxide layer 18, the mode of oxidation adopts wet-oxygen oxidation (H
2/ O
2), form
Top layer thermal oxide layer 18, technological temperature is 900～1050 ℃; Because the top oxidation is take silicon nitride film 17 as base heat growth top layer oxide layer 18, so top layer oxide layer 18 easy defective that produces in oxidizing process, therefore, the present invention has adopted low pressure N
2The O annealing way is repaired or is reduced defective in the oxide layer of top, its N
2O annealing process pressure 50～100torr, 800～900 ℃ of technological temperatures, as shown in Figure 2.
I, on top layer oxide layer 18 deposit electric pole plate 19.
The thickness of described electric pole plate 19 is
Polysilicon layer, and pass through POCL
3Doping, the sheet resistance that makes electric pole plate 19 is 20～27 Ω/ (square resistance), as shown in Figure 3.
The present invention adopts thickness stability and the interior uniformity of disk of low-pressure oxidized technology controlling and process tunnel oxidation layer 16, adopts the fixedly injection sequencing of P/As ion, is controlled at the technology stability of the tunnel oxidation layer 16 of bottom crown N+ diffusion region 13 growths.Adopt and regulate DCS and NH
3Ratio, make the silicon nitride film 17 in ONO have richness-N, reduce programming time, improve the uniformity of fuse cell puncture voltage in silica-based disk.Amorphous silicon layer is as the corrosion masking layer 15 in anti-fuse hole 20, in order to control better the sidewall pattern in anti-fuse hole.Adopt low pressure N
2O annealing reduces the defective that produces because of dangling bonds in top layer oxide layer 18, improves fuse cell puncture voltage uniformity.
The present invention utilizes N under hot conditions
2The oxygen atom that O decomposes can shift out the N with dangling bonds the top oxide layer, helps like this to strengthen the compactness of top layer oxide layer 18.Adopt industry device making technics flow process commonly used, compatible with the MOS technological process, technique is simple, controlled.With the ONO anti-fuse structures of routine relatively, have advantages of fuse cell puncture voltage good uniformity, programming time and programming after the fuse conducting resistance low.
Claims (10)
1. an ONO antifuse unit structure, comprise lower electrode plate, and described lower electrode plate comprises substrate (11), and the top of described substrate (11) is provided with an oxygen (12) and N+ diffusion region (13); It is characterized in that: arrange directly over described N+ diffusion region (13) and connect the anti-fuse hole (20) of injecting masking layer (14) and corrosion masking layer (15), described injection masking layer (14) covers on the N+ diffusion region (13) and an oxygen (12) on substrate (11) top, and corrosion masking layer (15) is covered in and injects on masking layer (14); On described corrosion masking layer (15), the ono dielectric layer is set, described ono dielectric layer covers on corrosion masking layer (15), and be filled in anti-fuse hole (20), the ono dielectric layer contacts with the N+ diffusion region (13) of bottom, anti-fuse hole (20), is coated with electric pole plate (19) on the ono dielectric layer.
2. ONO antifuse unit structure according to claim 1, it is characterized in that: described corrosion masking layer (15) is amorphous silicon layer, injecting masking layer (14) is silicon dioxide layer.
3. the preparation method of an ONO antifuse unit structure, is characterized in that, the preparation method of described antifuse unit structure comprises the steps:
(a), substrate (11) is provided, and make required field oxygen (12) and active area described substrate (11) is upper;
(b), inject masking layer (14) at the upper thermal oxide growth of above-mentioned substrate (11);
(c), utilize injection masking layer (14) at the upper N-type ion that injects of substrate (11), to obtain N+ diffusion region (13) on substrate (11);
(d), injecting the upper deposit corrosion of masking layer (14) masking layer (15), and etching is corroded masking layer (15) and injection masking layer (14) obtains anti-fuse hole (20), described anti-fuse hole (20) connects corrosion masking layer (15) and injects masking layer (14), contacts with N+ diffusion region (13) at the bottom of the hole in anti-fuse hole (20);
(e), above-mentioned substrate (11) being carried out tunnel oxidation cleans;
(f), utilize low-pressure oxidized technique growth tunnel oxidation layer (16), described tunnel oxidation layer (16) covers on corrosion masking layer (15), and covers sidewall and the diapire in anti-fuse hole (20);
(g), at the upper silicon nitride film (17) that adopts LPCVD deposit richness-N of above-mentioned tunnel oxidation layer (16);
(h), above-mentioned silicon nitride film layer (17) is carried out high-temperature oxydation, obtain top layer oxide layer (18);
(i), at the upper deposit electric pole plate (19) of top layer oxide layer (18).
4. the preparation method of ONO antifuse unit structure according to claim 3, is characterized in that, described step (a) comprises the steps:
(a1), in the upper growth of substrate (11)
The first silicon dioxide layer;
(a2), on above-mentioned the first silicon dioxide layer the deposit silicon nitride layer, the thickness of described silicon nitride layer is
(a3), the first silicon dioxide layer and silicon nitride layer on the above-mentioned substrate of photoetching (11), to make required active area;
(a4), utilize above-mentioned silicon nitride layer to be masking layer, thermal oxidation production
The second silicon dioxide layer, with obtain being positioned on substrate (11) the field oxygen (12);
(a5), remove above-mentioned oxygen (12) inboard the first silicon dioxide layer and silicon nitride layer.
5. the preparation method of ONO antifuse unit structure according to claim 3, is characterized in that, in described step (c), during described injection N-type ion, first injects the P ion, the As ion that reinjects, and wherein, the P/As implantation dosage is: 1.0E15～7.0E15/cm
2, the P/As Implantation Energy is: 50～80kev, the annealing process temperature is 900～1050 ℃, degeneration atmosphere N
2
6. the preparation method of ONO antifuse unit structure according to claim 3, is characterized in that, in described step (d), corrosion masking layer (15) be amorphous silicon layer, and the thickness that corrodes masking layer (15) is
The temperature of deposit corrosion masking layer (15) is 490～580 ℃, and pressure is 250～450mtorr.
7. the preparation method of ONO antifuse unit structure according to claim 3, is characterized in that, in described step (f), and the pressure 50～100torr of described growth tunnel oxidation layer (16), O
2Flow control is at 8～15SLM, and temperature is 680～820 ℃, and directly over N+ diffusion region (13), the thickness of tunnel oxidation layer (16) is
8. the preparation method of ONO antifuse unit structure according to claim 3, is characterized in that, in described step (g), the pressure of LPCVD deposition silicon nitride film (17) is 250～450mtorr, DCS:NH
3=1:5～1:10, technological temperature are 680～780 ℃, Si
3N
4Thicknesses of layers is
9. the preparation method of ONO antifuse unit structure according to claim 3, is characterized in that, in described step (h), adopts the wet-oxygen oxidation growth to obtain
Top layer oxide layer (18), temperature is 900～1050 ℃; And employing N
2O annealing, N
2O annealing process pressure 50～100torr, 800～900 ℃ of technological temperatures.
10. the preparation method of ONO antifuse unit structure according to claim 3, is characterized in that, the thickness of described electric pole plate (19) is
Polysilicon layer, and pass through POCL
3Doping, the sheet resistance that makes electric pole plate (19) is 20～27 Ω/.
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Cited By (2)
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| CN106169461A (en) * | 2016-09-22 | 2016-11-30 | 中国电子科技集团公司第五十八研究所 | Radioprotective PIP type ONO anti-fuse structures and CMOS technology Integration Method |
| CN107301877A (en) * | 2016-04-14 | 2017-10-27 | 意法半导体有限公司 | Configurable rom |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9735103B1 (en) | 2016-07-20 | 2017-08-15 | International Business Machines Corporation | Electrical antifuse having airgap or solid core |
| US9793207B1 (en) | 2016-07-20 | 2017-10-17 | International Business Machines Corporation | Electrical antifuse including phase change material |
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