CN105576031A - 一种以GaN为界面层的GaAs沟道MOS界面结构 - Google Patents
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- 229910001218 Gallium arsenide Inorganic materials 0.000 title claims abstract description 44
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 8
- 230000012010 growth Effects 0.000 claims description 11
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- 229910052733 gallium Inorganic materials 0.000 claims description 7
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 7
- 229910052721 tungsten Inorganic materials 0.000 claims description 7
- 239000010937 tungsten Substances 0.000 claims description 7
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 6
- 229910052593 corundum Inorganic materials 0.000 claims description 6
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- 238000004544 sputter deposition Methods 0.000 claims description 6
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 6
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- 239000000463 material Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 235000011114 ammonium hydroxide Nutrition 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
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Abstract
本发明公开了一种以GaN为界面层的GaAs沟道MOS界面结构，该结构自上而下依次是：一半绝缘单晶砷化镓衬底(101)；一在该砷化镓单晶衬底层(101)上形成的砷化镓沟道层(102)；一在该N型掺杂的砷化镓沟道层(102)上形成的界面控制层GaN(103)；一在该界面控制层GaN(103)上形成的界面过渡层AlN(104)；一在该界面过渡层AlN(104)上形成的高K介质层(105)；以及一在该高K栅介质(105)上形成的金属栅结构(106)。
Description
技术领域
本发明涉及半导体集成电路制造技术领域，具体涉及一种以GaN为界面层的GaAs沟道MOS界面结构，应用于高性能III-V族半导体CMOS技术。
背景技术
Ⅲ-Ⅴ化合物半导体材料相对硅材料而言，具有高载流子迁移率、大的禁带宽度等优点，而且在热学、光学和电磁学等方面都有很好的特性。在过去四十年中，高质量热稳定栅介质材料一直是III-V族半导体在大规模CMOS集成电路中的应用的主要障碍。最新研究报道表明：在III-V族半导体表面，直接采用原子层沉积(ALD)以及分子束外延(MBE)技术沉积高k栅介质材料已经实现了器件质量的的MOS界面。然而，该界面的性质仍无法与SiO2/Si相比拟，直接在高迁移率沟道表面直接生长高k栅介质材料界面态密度高会导致沟道载流子迁移率的下降。因此，需要一种新的途径在III-V族半导体材料上同时实现高载流子迁移率与低界面态密度，以满足高性能III-V族半导体CMOS技术的要求。
发明内容
(一)要解决的技术问题
本发明的主要目的是提供一种以GaN为界面层的GaAs沟道MOS界面结构，以同时实现高载流子迁移率与低界面态密度，满足高性能III-V族半导体CMOS技术的要求。
(二)技术方案
为达到上述目的，本发明提供了一种以GaN为界面层的GaAs沟道MOS界面结构，其特征在于，该结构自下而上依次包括：
一半绝缘单晶砷化镓衬底(101)；
一在该砷化镓单晶衬底层(101)上形成的砷化镓沟道层(102)；
一在该砷化镓沟道层(102)上形成的GaN界面控制层(103)；
一在该GaN界面控制层(103)上形成的AlN界面过渡层(104)；
一在该AlN界面过渡层(104)上形成的Al2O3高K介质层(105)；
以及一在该Al2O3高K栅介质(105)上形成的钨金属栅层(106)。
上述方案中，所述单晶衬底101是砷化镓(GaAs)衬底，其衬底晶向为(100)、(110)或者(111)。
上述方案中，所述砷化镓沟道层(102)是采用MBE或者MOCVD的生长方式在砷化镓单晶衬底上生长的，厚度在20纳米到200纳米。
上述方案中，所述GaN界面控制层(103)是采用MBE或者MOCVD的生长方式在砷化镓沟道层上生长的，其生长方式为在生长完砷化镓的镓原子后，采用含N气体进行吹扫，在砷化镓沟道层上形成厚度为2-4个原子层的GaN界面控制层。
上述方案中，所述AlN界面过渡层(104)是采用MBE或者MOCVD的生长方式在GaN界面控制层(103)上生长的，其生长方式为在生长完GaN的N原子后，采用含Al元素的生长气体进行吹扫，在GaN界面控制层(103)上形成厚度为2-4个原子层的AlN界面控制层。
上述方案中，所述Al2O3高K栅介质(105)的生长方式为原子层沉积，是在生长完AlN后，立即放入原子层沉积系统生长的，厚度为3-5纳米。
上述方案中，所述钨金属栅层(106)其沉积方式为溅射，是在Al2O3介质生长后，立即放入溅射系统进行的，钨金属层的厚度为50-200纳米。
(三)有益效果
从上述技术方案可以看出，本发明具有以下有益效果：
本发明提供的一种以GaN为界面层的GaAs沟道MOS界面结构，利用GaN界面控制层技术钝化界面处的悬挂键，实现低界面态密度，并降低沟道中载流子的散射，同时GaP界面层又是势垒层，提高了沟道层中的二维电子气浓度，实现高迁移率和高电子浓度双重作用；由于砷化镓材料的电子迁移率和空穴迁移率相对比较均衡，所以发明这种GaAs沟道MOS结构，以满足高性能III-V族半导体CMOS技术的要求。
附图说明
图1是本发明提供的GaAs沟道MOS界面结构的示意图；
图2是本发明提高的GaAs沟道MOS界面结构实施例图
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本发明进一步详细说明。
如图2所示，图2是本发明提供一种以GaN为界面层的GaAs沟道MOS界面结构，其特征在于，该结构自下而上依次包括：
一半绝缘单晶砷化镓衬底(201)；
一在该砷化镓单晶衬底层(201)上形成的50纳米厚的砷化镓沟道层(202)；
一在该砷化镓沟道层(202)上采用MBE方式生长的4个原子层厚的GaN界面控制层(203)；
一在该GaN界面控制层(203)上采用MBE方式生长的4个原子层厚的AlN界面过渡层(204)；
一在该AlN界面过渡层(204)上采用原子层沉积系统生长的3纳米厚度的Al2O3高K介质层(205)；
以及一在该Al2O3高K栅介质(205)上采用磁控溅射系统直接溅射的100纳米厚度的钨金属栅层(206)。
上述实施例中，所述单晶衬底201是砷化镓(GaAs)衬底，其衬底晶向为(100)，在生长沟道层之前，进行常规的有机清洗，再采用稀释盐酸清洗，再用稀释的氨水进行清洗。
上述实施例中，所述砷化镓沟道层(202)是采用MBE的生长方式在砷化镓单晶衬底上生长的，厚度在50纳米。
上述实施例中，所述GaN界面控制层(203)是采用MBE或者MOCVD的生长方式在砷化镓沟道层上生长的，其生长方式为在生长完砷化镓的镓原子后，采用含N气体进行吹扫，在砷化镓沟道层上形成厚度为4个原子层的GaN界面控制层。
上述实施例中，所述AlN界面过渡层(204)是采用MBE或者MOCVD的生长方式在GaN界面控制层(203)上生长的，其生长方式为在生长完GaN的N原子后，采用含Al元素的生长气体进行吹扫，在GaN界面控制层(203)上形成厚度为4个原子层的AlN界面控制层。
上述实施例中，所述Al2O3高K栅介质(205)的生长方式为原子层沉积，是在生长完AlN后，立即放入原子层沉积系统生长的，其厚度为3纳米。
上述实施例中，所述钨金属栅层(206)其沉积方式为溅射，是在Al2O3介质生长后，立即放入溅射系统进行的，钨金属层的厚度为200纳米。
以上所述的具体实施例，对本发明的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施例而已，并不用于限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。
Claims (5)
1.一种以GaN为界面层的GaAs沟道MOS界面结构，其特征在于，该结构自下而上依次包括：
一半绝缘单晶砷化镓衬底(101)；
一在该砷化镓单晶衬底层(101)上形成的砷化镓沟道层(102)；
一在该砷化镓沟道层(102)上形成的GaN界面控制层(103)；
一在该GaN界面控制层(103)上形成的AlN界面过渡层(104)；
一在该AlN界面过渡层(104)上形成的Al2O3高K介质层(105)；
以及一在该Al2O3高K栅介质(105)上形成的钨金属栅层(106)。
2.根据权利要求1所述的以GaN为界面层的GaAs沟道MOS界面结构，其特征在于，所述GaN界面控制层(103)是在生长N型砷化镓沟道层(102)后，采用含N的气体源进行表面吹扫后形成的，其厚度为2-4个原子层。
3.根据权利要求1所述的以GaN为界面层的GaAs沟道MOS界面结构，其特征在于，所述AlN界面过渡层(104)是在生长GaN为界面控制层(103)后，采用含Al的气体源进行表面吹扫后形成的，其厚度为2-4个原子层。
4.根据权利要求1所述的以GaN为界面层的GaAs沟道MOS界面结构，其特征在于，所述Al2O3高K介质层(105)是在生长AlN界面过渡层(104)后，立即转移到原子层沉积系统中生长的，其厚度为2-3纳米。
5.根据权利要求1所述的以GaN为界面层的GaAs沟道MOS界面结构，其特征在于，所述W金属栅层(106)是在生长Al2O3高K介质层(105)后，立即转移到磁控溅射台上直接溅射形成的，其厚度为50-200纳米。
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| CN110797398A (zh) * | 2019-11-07 | 2020-02-14 | 中合博芯(重庆)半导体有限公司 | 一种高k氧化物栅绝缘层mos-hemt器件及其制备方法 |
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| US20100270591A1 (en) * | 2009-04-27 | 2010-10-28 | University Of Seoul Industry Cooperation Foundation | High-electron mobility transistor |
| CN102194859A (zh) * | 2010-03-05 | 2011-09-21 | 中国科学院微电子研究所 | 高迁移率ⅲ-ⅴ族半导体mos界面结构 |
| CN102842595A (zh) * | 2011-06-20 | 2012-12-26 | 中国科学院微电子研究所 | 半导体器件及其制造方法 |
| CN103828030A (zh) * | 2012-08-10 | 2014-05-28 | 日本碍子株式会社 | 半导体元件、hemt元件、以及半导体元件的制造方法 |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106024712A (zh) * | 2016-07-29 | 2016-10-12 | 东莞华南设计创新院 | 一种自对准砷化镓pmos器件的制作方法 |
| CN110797398A (zh) * | 2019-11-07 | 2020-02-14 | 中合博芯(重庆)半导体有限公司 | 一种高k氧化物栅绝缘层mos-hemt器件及其制备方法 |
| CN110797398B (zh) * | 2019-11-07 | 2024-03-26 | 中合博芯(重庆)半导体有限公司 | 一种高k氧化物栅绝缘层mos-hemt器件及其制备方法 |
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