CN105575813A - High-voltage VDMOS device and making method thereof - Google Patents
High-voltage VDMOS device and making method thereof Download PDFInfo
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- CN105575813A CN105575813A CN201410549457.8A CN201410549457A CN105575813A CN 105575813 A CN105575813 A CN 105575813A CN 201410549457 A CN201410549457 A CN 201410549457A CN 105575813 A CN105575813 A CN 105575813A
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Abstract
The invention discloses a high-voltage VDMOS device and a making method thereof. A grid making method of the high-voltage VDMOS device comprises the following steps of making a groove on a front side of a wafer of the high-voltage VDMOS device; making a grid oxide layer on a front side of the wafer where the groove is formed; and making a grid on a front side of the wafer where the grid oxide layer is formed, wherein a mask layer window used for making the grid aligns the groove, and a width of the mask layer window used for making the grid is greater than an opening width of the groove. Through the above technology process, the grid is filled into the groove. Under the condition that an effective length of the grid is not changed, a transverse width of the grid is reduced so that a cellular integration degree is increased under the condition of a same chip area or a chip area is reduced under the condition of a same current processing capability. Besides, because the effective length of the grid is not reduced, a large influence on performance of other electrical parameters is not generated.
Description
Technical field
The present invention relates to semiconductor device manufacture technology field, particularly relate to a kind of high pressure VDMOS (vertical DMOS) device and preparation method thereof.
Background technology
High pressure VDMOS generally adopts the structure cell of plane to obtain high puncture voltage, as shown in Figure 1.Along with the competition of VDMOS produce market is more and more fierce, many manufacturers release corresponding contracting version product one after another.The reduction of product size realizes mainly through the approach reducing cellular size.An important parameter of high pressure VDMOS is conducting resistance (RDSON), and the important component part of conducting resistance is the surface charge accumulation layer resistance formed on layer immediately below grid.Grid length reduces, and the conducting resistance of high pressure VDMOS will be larger.For avoiding conducting resistance (RDSON) excessive, cellular size is difficult to continue to reduce.
Summary of the invention
The object of this invention is to provide a kind of high pressure VDMOS device and preparation method thereof, to solve the problem that existing high pressure VDMOS manufacture craft cannot reduce DMOS cellular size further.
The object of the invention is to be achieved through the following technical solutions:
A manufacture method for high pressure VDMOS device, its fabrication comprises the following steps:
Groove is made in the wafer front of described high pressure VDMOS device;
Grid oxic horizon is made in the described wafer front forming groove;
Make grid in the described wafer front forming grid oxic horizon, wherein, make the mask window of grid and described trough aligned, and the width of the mask window of described making grid is greater than the A/F of described groove.
Preferably, described groove is up big and down small bowl structure.
Based on above-mentioned any means embodiment, preferably, make groove in the wafer front of described high pressure VDMOS device, comprising:
Adopt photoetching, etching technics, form groove in the wafer front of described high pressure VDMOS device;
At described flute surfaces growth sacrificial oxide layer, to be adjusted described groove shape by described sacrificial oxide layer;
Remove described sacrificial oxide layer.
Preferably, the thickness of described sacrificial oxide layer is greater than 1000 dusts.
Based on the inventive concept same with method, the embodiment of the present invention also provides a kind of high pressure VDMOS device, comprising:
Be produced on the groove in the wafer front of described high pressure VDMOS device;
Be produced on the grid oxic horizon in the described wafer front forming groove;
Be produced on the grid in the described wafer front forming grid oxic horizon, wherein, make the mask window of grid and described trough aligned, and the width of the mask window of described making grid be greater than the A/F of described groove.
Preferably, described groove is up big and down small bowl structure.
The high pressure VDMOS device formed by above-mentioned technical process, makes grid insert in groove.When grid effective length is constant, reduce the transverse width of grid, thus realize improving cellular integrated level under identical chip area condition, or reduce chip area under identical current handling capability condition.In addition, because the effective length of grid is not reduced, can not have much impact to the performance of other electrical quantitys.
Accompanying drawing explanation
Fig. 1 is existing high pressure VDMOS device structure cell schematic diagram;
The method flow diagram that Fig. 2 provides for the embodiment of the present invention;
Device architecture schematic diagram after the formation epitaxial loayer that Fig. 3 provides for the embodiment of the present invention;
Device architecture figure after the formation initial oxide layer that Fig. 4 provides for the embodiment of the present invention;
Device architecture schematic diagram after the formation cushion oxide layer that Fig. 5 provides for the embodiment of the present invention;
Fig. 6 for groove that the embodiment of the present invention provides formed after device architecture schematic diagram;
Device architecture schematic diagram after the formation sacrificial oxide layer that Fig. 7 provides for the embodiment of the present invention;
Device architecture schematic diagram after the removal sacrificial oxide layer that Fig. 8 provides for the embodiment of the present invention;
Device architecture schematic diagram after the formation gate oxide that Fig. 9 provides for the embodiment of the present invention and polysilicon;
Device architecture schematic diagram after the formation grid that Figure 10 provides for the embodiment of the present invention;
Device architecture schematic diagram after the formation P type tagma that Figure 11 provides for the embodiment of the present invention;
Figure 12 for the invention process provide complete annealing process after device architecture schematic diagram;
Device architecture schematic diagram after the formation N-type source region that Figure 13 provides for the embodiment of the present invention;
The formation P+ tagma that Figure 14 provides for the embodiment of the present invention device architecture schematic diagram after completing annealing process;
Device architecture schematic diagram after the formation dielectric layer that Figure 15 provides for the embodiment of the present invention;
Device architecture schematic diagram after the formation front metal that Figure 16 provides for the embodiment of the present invention;
Device architecture schematic diagram after the formation back metal that Figure 17 provides for the embodiment of the present invention.
Embodiment
The main thought of the embodiment of the present invention is, enters in groove, exchange the shortening of lateral dimension with the increase of longitudinal size for by the main part " filling " of the grid material of high pressure VDMOS.Realize the integrated level that improve cellular under identical chip area condition, or under identical current handling capability condition, reduce the area of chip.
Below in conjunction with accompanying drawing, high pressure VDMOS device that the embodiment of the present invention provides and preparation method thereof is described in detail.
The manufacture method of a kind of high pressure VDMOS device that the embodiment of the present invention provides, its fabrication process as shown in Figure 2, specifically comprises the following steps:
Step 200, the wafer front of above-mentioned high pressure VDMOS device make groove.
In the embodiment of the present invention, the gash depth make step 200 and the concrete value of openings of sizes are not construed as limiting.In actual production process, determine according to actual requirement.Such as, the gash depth that the effective length determining step 200 needed for grid makes and openings of sizes.
Step 210, make grid oxic horizon in the above-mentioned wafer front forming groove.
Step 220, make grid in the above-mentioned wafer front forming grid oxic horizon, wherein, make the mask window of grid and above-mentioned trough aligned, and the width of the mask window of making grid is greater than the A/F of groove.
In the embodiment of the present invention, grid material can but be not limited only to polysilicon.
By above-mentioned technical process, grid is inserted in groove.When grid effective length is constant, reduce the transverse width of grid, thus realize improving cellular integrated level under identical chip area condition, or reduce chip area under identical current handling capability condition.In addition, because the effective length of grid is not reduced, can not have much impact to the performance of other electrical quantitys.
In the embodiment of the present invention, the groove shape that step 200 is formed is not construed as limiting.In order to improve puncture voltage, the radius of curvature of channel bottom fillet can be increased, thus reduce the electric field strength at channel bottom place, improve puncture voltage.
In order to be beneficial to filling and the covering of grid material, preferably, above-mentioned groove is up big and down small bowl structure.
Based on above-mentioned any means embodiment, the implementation of above-mentioned steps 200 has multiple.Exemplify a preferred implementation below: adopt photoetching, etching technics, form groove in the wafer front of above-mentioned high pressure VDMOS device; At this flute surfaces growth sacrificial oxide layer, to be adjusted this groove shape by sacrificial oxide layer; Remove this sacrificial oxide layer.
By generating sacrificial oxide layer in flute surfaces, groove shape being adjusted, the radius of curvature of channel bottom fillet can be increased.
Wherein, the thickness of sacrificial oxide layer is greater than 1000 dusts.Preferably, the thickness of sacrificial oxide layer is between 1000 dust to 10000 dusts.Wherein, 1 dust equals 10
-10rice.
Preferably, the first groove opening diameter formed is at 1.6um ~ 2.0um.Gash depth is at 1.0um ~ 1.2um.Groove opening diameter after adjustment is at 3.0um ~ 3.5um, and channel bottom after adjustment is comparatively mild, is less than 60 °.
Preferably, make the mask window diameter of grid at 4um ~ 5um, making the grid effective length obtained can reach 6um ~ 10um.
Below by for the complete manufacturing process of a high pressure VDMOS device, the technical scheme that the embodiment of the present invention provides is described.
Step 1, make epitaxial loayer on one of wafer surface, as shown in Figure 3.
Wherein, wafer and the substrate shown in Fig. 3 301, form one side and the wafer front of epitaxial loayer 302.
Step 2, generation initial oxide layer, as shown in Figure 4; Then open active area, peel initial oxide layer 303 off.
It should be pointed out that terminal structure position needs to retain initial oxide layer, cell region needs to peel initial oxide layer off.
Step 3, grow liners oxide layer (Pad-OX), as shown in Figure 5.
In Fig. 5, cushion oxide layer 304 is grown on epi-layer surface.
Step 4, employing photoetching, etching technics make groove.As shown in Figure 6.
Concrete, at cushion oxide layer 304 surface-coated photoresist, adopt photoetching process, utilize mask plate to carry out photoetching to photoresist, form the photoetching agent pattern 305 making groove.Adopt etching technics, utilize photoetching agent pattern 305 pairs of cushion oxide layer 304 and epitaxial loayer 302 to etch, form groove 306, then remove photoresist and cushion oxide layer 304.
Step 5, growth sacrificial oxide layer, as shown in Figure 7.
By growth sacrificial oxide layer 307, the shape of groove 306 is adjusted, big up and small down bowl-shape of the groove 306 after adjustment.
Step 6, removal sacrificial oxide layer, as shown in Figure 8.
Now, the opening of groove broadens, and the radius of curvature of bottom roundings increases, and is beneficial to filling and the covering of grid material.
Step 7, growth gate oxide and polysilicon.As shown in Figure 9, gate oxide 308 and polysilicon layer 309 " inserting " groove 306.
Step 8, photoetching, etching are carried out to polysilicon layer, form grid.As shown in Figure 10, the mask window making grid 310 is aimed at groove 306, and the width making the mask window of grid 310 is greater than the A/F of groove 306.
Step 9, utilize gate window, the autoregistration carrying out P type tagma is injected, as shown in figure 11.P type tagma 311 is formed in epitaxial loayer 302.
Step 10, carry out annealing process, as shown in figure 12, P type tagma 311 is pushed into desired depth.
Step 11, employing photoetching, injection technology, form N-type source region, and carry out preannealing, as shown in figure 13.Wherein, N-type tagma 312 is formed in epitaxial loayer 302.
Step 12, deposit side wall, carry out P+ injection, and anneal, as shown in figure 14.The injection in P+ tagma 314 is carried out by side wall 313.
Step 13, dielectric layer deposited (ILD), as shown in figure 15, dielectric layer 315 is for doing electrical isolation.
Step 14, open fairlead, deposit front metal, as shown in figure 16.Row metal of going forward side by side is carved for 316 times.
Step 15, thinning back side, and carry out back metal deposit, as shown in figure 17.Back metal 317 is deposited on the wafer back side.
Through the high pressure VDMOS device that above-mentioned technical process is formed, than the existing high pressure VDMOS device shown in Fig. 1, the main part " filling " of the grid material of high pressure VDMOS is entered in groove, exchanges the shortening of lateral dimension with the increase of longitudinal size for.Realize the integrated level that improve cellular under identical chip area condition, or under identical current handling capability condition, reduce the area of chip.
Based on the inventive concept same with method, the embodiment of the present invention also provides a kind of high pressure VDMOS device, comprising:
Be produced on the groove in the wafer front of described high pressure VDMOS device;
Be produced on the grid oxic horizon in the described wafer front forming groove;
Be produced on the grid in the described wafer front forming grid oxic horizon, wherein, make the mask window of grid and described trough aligned, and the width of the mask window of described making grid be greater than the A/F of described groove.
Its complete structure can with reference to Figure 17, and the present invention repeats no more.
Preferably, described groove is up big and down small bowl structure.
Preferably, described groove opening diameter range is 3.0um ~ 3.5um, and channel bottom angle is less than 60 °.
Preferably, the mask window diameter range making grid is 4um ~ 5um.
The high pressure VDMOS device that the embodiment of the present invention provides, grid is inserted in groove.When grid effective length is constant, reduce the transverse width of grid, thus realize improving cellular integrated level under identical chip area condition, or reduce chip area under identical current handling capability condition.In addition, because the effective length of grid is not reduced, can not have much impact to the performance of other electrical quantitys.
Although describe the preferred embodiments of the present invention, those skilled in the art once obtain the basic creative concept of cicada, then can make other change and amendment to these embodiments.So claims are intended to be interpreted as comprising preferred embodiment and falling into all changes and the amendment of the scope of the invention.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (10)
1. a manufacture method for high pressure VDMOS device, is characterized in that, the fabrication of described high pressure VDMOS device comprises the following steps:
Groove is made in the wafer front of described high pressure VDMOS device;
Grid oxic horizon is made in the described wafer front forming groove;
Make grid in the described wafer front forming grid oxic horizon, wherein, make the mask window of grid and described trough aligned, and the width of the mask window of described making grid is greater than the A/F of described groove.
2. method according to claim 1, is characterized in that, described groove is up big and down small bowl structure.
3. method according to claim 1, is characterized in that, makes groove, comprising in the wafer front of described high pressure VDMOS device:
Adopt photoetching, etching technics, form groove in the wafer front of described high pressure VDMOS device;
At described flute surfaces growth sacrificial oxide layer, to be adjusted described groove shape by described sacrificial oxide layer;
Remove described sacrificial oxide layer.
4. method according to claim 3, is characterized in that, the groove opening diameter range before adjustment is 1.6um ~ 2.0um, and gash depth scope is 1.0um ~ 1.2um.
5. method according to claim 3, is characterized in that, the groove opening diameter after adjustment is at 3.0um ~ 3.5um, and channel bottom angle is less than 60 °.
6. the method according to claim 4 or 5, is characterized in that, the mask window diameter range making grid is 4um ~ 5um.
7. a high pressure VDMOS device, is characterized in that, comprising:
Be produced on the groove in the wafer front of described high pressure VDMOS device;
Be produced on the grid oxic horizon in the described wafer front forming groove;
Be produced on the grid in the described wafer front forming grid oxic horizon, wherein, make the mask window of grid and described trough aligned, and the width of the mask window of described making grid be greater than the A/F of described groove.
8. high pressure VDMOS device according to claim 7, is characterized in that, described groove is up big and down small bowl structure.
9. high pressure VDMOS device according to claim 7, is characterized in that, described groove opening diameter range is 3.0um ~ 3.5um, and channel bottom angle is less than 60 °.
10. high pressure VDMOS device according to claim 9, is characterized in that, the mask window diameter range making grid is 4um ~ 5um.
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| CN201410549457.8A CN105575813A (en) | 2014-10-16 | 2014-10-16 | High-voltage VDMOS device and making method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117650158A (en) * | 2024-01-26 | 2024-03-05 | 湖北九峰山实验室 | Wide bandgap semiconductor trench MOSFET device and manufacturing method thereof |
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| US20040166637A1 (en) * | 2000-05-30 | 2004-08-26 | Hiroyasu Ito | Manufacturing method of semiconductor device |
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| US20050009255A1 (en) * | 2003-07-10 | 2005-01-13 | International Rectifier Corp. | Process for forming thick oxides on Si or SiC for semiconductor devices |
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|---|---|---|---|---|
| US20040166637A1 (en) * | 2000-05-30 | 2004-08-26 | Hiroyasu Ito | Manufacturing method of semiconductor device |
| JP2002016080A (en) * | 2000-06-28 | 2002-01-18 | Toshiba Corp | Manufacturing method of trench-gate type mosfet |
| CN1527369A (en) * | 2003-03-03 | 2004-09-08 | ��ʽ�����װ | Semiconductor device with slot structure and producing method thereof |
| US20050009255A1 (en) * | 2003-07-10 | 2005-01-13 | International Rectifier Corp. | Process for forming thick oxides on Si or SiC for semiconductor devices |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117650158A (en) * | 2024-01-26 | 2024-03-05 | 湖北九峰山实验室 | Wide bandgap semiconductor trench MOSFET device and manufacturing method thereof |
| CN117650158B (en) * | 2024-01-26 | 2024-05-10 | 湖北九峰山实验室 | Wide bandgap semiconductor trench MOSFET device and manufacturing method thereof |
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Application publication date: 20160511 |
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