CN105575306A - Display panel and bidirectional shift register circuit - Google Patents

Abstract

A display panel and a bidirectional shift register circuit are provided. The display panel includes a gate driving circuit. The grid driving circuit comprises a plurality of shift registers connected in series. At least one shift register comprises an input circuit, an output circuit and a control circuit. The input circuit is coupled to the first input terminal and the second input terminal for receiving a first input signal and a second input signal respectively. The output circuit is coupled to the first clock input terminal, and is used for receiving the first clock signal and outputting the pulse signal at the output terminal according to the first clock signal. The control circuit is coupled to the output circuit through the first control node, the second control node and the third control node, and controls a voltage of the first control node, the second control node and the third control node according to the first input signal or the second input signal, so as to control the operation of the output circuit.

Description

Display panel and bidirectional shift register circuit

technical field

The invention relates to a bidirectional shift register, in particular to a bidirectional shift register which can effectively shorten the falling time of output pulses and reduce power consumption.

Background technique

Shift registers are widely used in data driving circuits and gate driving circuits to respectively control the timing of sampling data signals for each data line and the timing of generating scanning signals for each gate line. In the data driving circuit, the shift register is used to output a selection signal to each data line, so that image data can be sequentially written into each data line. On the other hand, in the gate driving circuit, the shift register is used to generate a scanning signal to each gate line for sequentially writing image signals supplied to each data line into pixels of a pixel matrix.

Conventional shift registers can only generate sampled or scanned signals in a single scan sequence. However, a single scanning sequence can no longer meet the demands of current image display system products. For example, the display screens of some digital cameras can be rotated according to the angle at which the camera is placed. Additionally, some image display systems may include the ability to rotate the screen. Therefore, a new bidirectional shift register architecture is needed, which can generate output signals in different scan orders. And can effectively shorten the output pulse fall time and reduce power consumption.

Contents of the invention

The invention discloses a display panel, which includes a grid driving circuit. The gate driving circuit includes a plurality of serially connected shift registers. At least one shift register includes an input circuit, an output circuit and a control circuit. The input circuit is coupled to the first input end and the second input end for receiving the first input signal and the second input signal respectively. The output circuit is coupled to the first clock input end for receiving the first clock signal, and outputs a pulse signal at the output end according to the first clock signal. The control circuit is coupled to the output circuit through the first control node, the second control node and the third control node, and controls the first control node, the second control node and the third control node according to the first input signal or the second input signal A voltage, and then control the operation of the output circuit.

The invention also proposes a bidirectional shift register circuit for generating multiple gate driving signals. The bidirectional shift register circuit includes a plurality of shift registers, and at least one shift register includes an input circuit, an output circuit, a control circuit, a second clock input terminal and a third clock input terminal. The input circuit is coupled to a first input terminal and a second input terminal for receiving a first input signal and a second input signal respectively. The output circuit is coupled to a first clock input end for receiving a first clock signal, and outputs a pulse signal at an output end according to the first clock signal. The control circuit is coupled to the output circuit through a first control node, a second control node and a third control node, and controls the first control node, the second control node and the third control node according to the first input signal or the second input signal A voltage of the control node is used to control the operation of the output circuit. The second clock input terminal is used for receiving a second clock signal. The third clock input terminal is used for receiving a third clock signal. When the shift register is operating in the forward scan, a falling edge of the first clock signal is adjacent to a rising edge of the second clock signal, and when the shift register is operating in the reverse scan, a falling edge of the first clock signal is adjacent A rising edge of the third clock signal.

Description of drawings

FIG. 1 is a block diagram showing a display device according to an embodiment of the invention.

Figure 2 is a diagram showing an example of a clock signal waveform.

FIG. 3 is a block diagram showing a circuit of a bidirectional shift register according to an embodiment of the present invention.

FIG. 4 is a circuit diagram showing a shift register according to a first embodiment of the present invention.

FIG. 5 is a waveform diagram showing related signals and node voltages during forward scanning of the shift register according to the first embodiment of the present invention.

FIG. 6 is a waveform diagram showing related signals and node voltages during reverse scanning of the shift register according to the first embodiment of the present invention.

FIG. 7 is a circuit diagram showing a shift register according to a second embodiment of the present invention.

FIG. 8 is a waveform diagram showing related signals and node voltages during forward scanning of the shift register according to the second embodiment of the present invention.

FIG. 9 is a waveform diagram showing related signals and node voltages during reverse scanning of the shift register according to the second embodiment of the present invention.

【Symbol Description】

100～display device;

101～display panel;

102～input unit;

110～gate drive circuit;

120～data drive circuit;

130～pixel matrix;

140～control chip;

201, 202～waveform;

300～two-way shift register circuit;

400, 700, SR(1), SR(2), SR(3), SR(4), SR(M)～shift register;

410, 710～input circuit;

420, 720～control circuit;

430, 730～ output circuit;

440～switching circuit;

BCSV, CSV ~ control signal;

C～capacitance;

C1 ~ the first clock input terminal;

C2 ~ the second clock input terminal;

C3 ~ the third clock input terminal;

C4 ~ the fourth clock input terminal;

CKV1, CKV2, CKV3, CKV4 ~ clock signal;

G(1), G(2), G(M-1), G(M)～gate drive signal;

IN1 ~ the first input terminal;

IN2 ~ the second input terminal;

M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M23, M24, M25, M26, M27, M28, M29, M30 ~ transistors;

N1～the first control node;

N2～second control node;

N3～the third control node;

N4～the fourth control node;

N5～fifth control node;

OUT ~ output terminal;

STV ~ start pulse;

T _f1 , T _f2 ~ falling time;

VL～low operating voltage;

VH～high operating voltage;

VH1, VH1’, VH2, VH2’, VH3, VH3’, VH4, VH4’～high voltage.

detailed description

In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments are specifically cited below and described in detail with accompanying drawings.

FIG. 1 is a block diagram showing a display device according to an embodiment of the invention. As shown in the figure, the display device 100 may include a display panel 101 , a data driving circuit 120 and a control chip 140 , wherein the display panel 101 includes a gate driving circuit 110 and a pixel matrix 130 . The gate driving circuit 110 is used for generating a plurality of gate driving signals to drive a plurality of pixels of the pixel matrix 130 . The data driving circuit 120 is used for generating a plurality of data driving signals to provide image data to a plurality of pixels of the pixel matrix 130 . The control chip 140 is used to generate a plurality of timing signals, including a clock signal, a reset signal, a start pulse, and the like.

In addition, the display device 100 may further include an input unit 102 . The input unit 102 is used for receiving image signals to control the display panel 101 to display images. According to the embodiment of the present invention, the display device 100 can be applied in an electronic device, wherein the electronic device has various implementations, including: a mobile phone, a digital camera, a personal digital assistant, a mobile computer, a desktop A computer, a television, a monitor for a car, a portable disc player, or any device including an image display function.

According to an embodiment of the present invention, the gate driving circuit 110 may be designed as a gate driving circuit for unilateral driving and arranged on one side of the pixel matrix 130, or may be designed as a gate driving circuit for bilateral driving, and are arranged on both sides of the pixel matrix 130 , but the present invention is not limited to any one implementation.

In addition, according to an embodiment of the present invention, according to the design of single-side driving or double-side driving, the gate driving circuit 110 may include one or more shift register circuits, and the shift register circuits are bidirectional shift register circuits, It is used to support the operation of two different scanning directions (forward scanning and reverse scanning). In an embodiment of the present invention, the bidirectional shift register circuit may include a plurality of serially connected shift registers (ShiftRegister, abbreviated as SR), and the shift registers of each stage may sequentially generate a gate drive signal to each gate lines for driving pixels on each gate line. For example, when the bidirectional shift register circuit operates in forward scanning, the shift registers of each stage are in a first order (for example, SR(1)-SR(M), where M represents the number of shift registers, and M is a positive integer) to sequentially output corresponding gate drive signals, and when the bidirectional shift register circuit is operating in reverse scanning, the shift registers of each stage are in a second order (for example, SR(M)～SR( 1)) Sequentially output the corresponding gate drive signals.

Generally speaking, when the resolution of the display panel increases, the number of required shift registers must also increase accordingly. However, once the number of shift registers increases, the load on the clock signal supplied to the shift register circuit will also increase accordingly, resulting in the waveform distortion of the clock signal received by the remote shift register. .

Figure 2 is a diagram showing an example of a clock signal waveform. Waveform 201 represents the clock signal waveform received by the near-end shift register, and waveform 202 represents the clock signal waveform received by the far-end shift register. Here, the near-end and far-end represent the shift register and the clock provided The relative distance of the control chip of the signal. It can be seen from the figure that the falling time (falling time) T _f2 of the pulse of the clock signal received by the remote shift register is much longer than the falling time T _f1 of the pulse of the clock signal received by the near-end shift register . However, in a design where the pulse width of the clock signal has multiple horizontal times, the falling edge of the clock signal is an important time point for reading image data. Therefore, the falling time of the pulse of the clock signal must be as short as possible. .

In this way, the size of the transistor (for example, corresponding to the transistor M1 shown in the embodiments of FIGS. 4 and 7 of the present invention) used to output one of the pulses of the clock signal as the gate pulse in the conventional technology cannot be reduced, to avoid prolonging the fall time of the gate pulse. However, the large size of the transistor M1 results in an ineffective reduction of the circuit area and high power consumption. In view of this, the present invention proposes a bidirectional shift register that can effectively shorten the gate pulse fall time and reduce power consumption. The following paragraphs go into more detail.

FIG. 3 is a block diagram showing a circuit of a bidirectional shift register according to an embodiment of the present invention. As shown in the figure, the bidirectional shift register circuit 300 may include a plurality of serially connected shift registers SR( 1 )˜SR(M). Each shift register may at least include a first input terminal IN1, a second input terminal IN2, an output terminal OUT, a first clock input terminal C1, a second clock input terminal C2, a third clock input terminal C3 and a fourth clock input terminal C4 . The first stage shift register SR(1) receives the start pulse STV at the first input terminal IN1 as the first input signal, and the other stage shift registers SR(2)~SR(M) respectively receive the start pulse STV at the first input terminal IN1 The gate pulses output by the first-stage shift registers SR(1)˜SR(M-1) are used as the first input signal. The last stage shift register SR(M) receives the start pulse STV at the second input terminal IN2 as the second input signal, and the other stages of shift registers SR(M-1)~SR(1) respectively receive the start pulse STV at the second input terminal IN2 Receive gate pulses output by the shift registers SR(M)˜SR(2) at the next stage as the second input signal.

In addition, according to an embodiment of the present invention, each shift register can receive at least four clock signals, for example, the clock signals CKV1 , CKV2 , CKV3 and CKV4 shown in the figure. As shown in FIG. 3 , each shift register receives a clock signal at each clock input terminal according to a predetermined rule. In an embodiment of the present invention, a rising edge of a clock signal is preferably adjacent to a falling edge of a next clock signal. In addition, during the forward scanning, the pulses of the clock signals CKV1 - CKV4 are sequentially and cyclically generated, and during the reverse scanning, the pulses of the clock signals CKV4 - CKV1 are instead sequentially and cyclically generated. As shown in FIG. 5 and FIG. 8, during forward scanning, a rising edge of the clock signal CKV1 is adjacent to a falling edge of the clock signal CKV4, a rising edge of the clock signal CKV2 is adjacent to a falling edge of the clock signal CKV1, and thus By analogy, the pulses of the clock signals CKV1 - CKV4 are sequentially and cyclically generated. also. As shown in FIG. 6 and FIG. 9, during reverse scanning, a rising edge of the clock signal CKV4 is adjacent to a falling edge of the clock signal CKV1, a rising edge of the clock signal CKV3 is adjacent to the clock signal CKV4, and the clock signals CKV4~CKV1 Pulses are generated sequentially and cyclically.

In addition, according to an embodiment of the present invention, during forward scanning, the operations of the shift registers of each stage are activated in response to the first input signal received from the first input terminal IN1, and in response to the input signal received from the fourth clock input terminal C4. The received clock signal is turned off. During the reverse scan, the operations of the shift registers of each stage are activated in response to the second input signal received from the second input terminal IN2, and are deactivated in response to the clock signal received from the fourth clock input terminal C4. The following paragraphs will introduce the multiple shift register circuits proposed by the present invention in more detail.

FIG. 4 is a circuit diagram showing a shift register according to a first embodiment of the present invention. The shift register 400 may be any one of the shift registers SR( 1 )˜SR(M) shown in FIG. 3 , and may include an input circuit 410 , a control circuit 420 , an output circuit 430 and a switching circuit 440 . For convenience, the shift register 400 is regarded as the first-stage shift register SR(1) for illustration below.

The input circuit 410 is coupled to the first input terminal IN1 and the second input terminal IN2 to receive the input signal STV and G(2) respectively (that is, the gate drive signal output by the next-stage shift register SR(2) ). The output circuit 430 is coupled to the first clock input terminal C1 for receiving the clock signal CKV1 , and outputs a pulse signal (ie, the gate pulse of the gate driving signal G( 1 )) at the output terminal OUT according to the clock signal CKV1 . The control circuit 420 is coupled to the output circuit 430 through the first control node N1, the second control node N2 and the third control node N3, and controls the first control node N1, the second control node N2 according to the input signal STV or G(2) and a voltage of the third control node N3 to further control the operation of the output circuit 430 . The switching circuit 440 is coupled to the second clock input terminal C2 and the third clock input terminal C3 for receiving the clock signal CKV2 and the clock signal CKV4 .

In this embodiment, the input circuit 410 and the switching circuit 440 further receive two control signals CSV and BCSV. The control signals CSV and BCSV are used to define the scan direction. For example, when operating in forward scan, the control signal CSV has a first voltage level and the control signal BCSV has a second voltage level. At this time, the input circuit 410 only transmits the input signal STV to the control circuit 420 , and the switch circuit 440 only transmits the clock signal CKV2 to the control circuit 420 . When operating in reverse scan, the control signal CSV has the second voltage level and the control signal BCSV has the first voltage level. At this time, the input circuit 410 only transmits the input signal G( 2 ) to the control circuit 420 , and the switching circuit 440 only transmits the clock signal CKV4 to the control circuit 420 .

According to an embodiment of the present invention, the output circuit 430 may include transistors M1 , M2 and a capacitor C. As shown in FIG. The transistor M1 is coupled between the first clock input terminal C1 and the output terminal OUT, and has a control electrode coupled to the first control node N1. The transistor M2 is coupled between the output terminal OUT and the low operating voltage VL, and has a control electrode coupled to the second control node N2. The transistor M1 is turned on or off according to the voltage of the first control node N1, and the transistor M2 is turned on or off according to the voltage of the second control node N2.

The control circuit 420 may include transistors M3 - M8 . The transistor M3 is coupled between the high operating voltage VH and the first control node N1, and has a control electrode coupled to the fourth control node N4. The transistor M3 is turned on or off according to a voltage of the fourth control node N4 to control the voltage of the first control node N1. The transistor M4 is coupled between the high operating voltage VH and the second control node N2, and has a control electrode coupled to the fifth control node N5. The transistor M4 is turned on or off according to a voltage of the fifth control node N5 to control the voltage of the second control node N2. The transistor M5 is coupled between the high operating voltage VH and the third control node N3, and has a control electrode coupled to the fourth clock input terminal C4. The transistor M5 is turned on or off according to a voltage of the clock signal CKV3 to control the voltage of the third control node N3.

The transistor M6 is coupled between the first control node N1 and the low operating voltage VL, and has a control electrode coupled to the third control node N3. The transistor M6 is turned on or off according to a voltage of the third control node N3 to control the voltage of the first control node N1. The transistor M7 is coupled between the second control node N2 and the low operating voltage VL, and has a control electrode coupled to the fourth control node N4. The transistor M7 is turned on or off according to a voltage of the fourth control node N4 to control the voltage of the second control node N2. The transistor M8 is coupled between the third control node N3 and the low operating voltage VL, and has a control electrode coupled to the fourth control node N4. The transistor M8 is turned on or off according to a voltage of the fourth control node N4 to control the voltage of the third control node N3.

The input circuit 410 may include transistors M9 and M10. The transistor M9 is coupled between the first input terminal IN1 and the fourth control node N4, and has a gate receiving the control signal CSV. The transistor M10 is coupled between the second input terminal IN2 and the fourth control node N4, and has a gate receiving the control signal BCSV. The transistors M9 and M10 are respectively turned on or off according to the voltage levels of the control signals CSV and BCSV to selectively transmit the input signal STV or G( 2 ) to the control circuit 420 .

The switching circuit 440 may include transistors M11 and M12. The transistor M11 is coupled between the second clock input terminal C2 and the fifth control node N5, and has a gate receiving the control signal CSV. The transistor M12 is coupled between the third clock input terminal C3 and the fifth control node N5, and has a gate receiving the control signal BCSV. The transistors M11 and M12 are respectively turned on or off according to the voltage levels of the control signals CSV and BCSV to selectively transmit the clock signal CKV2 or CKV4 to the control circuit 420 .

FIG. 5 is a waveform diagram showing related signals and node voltages during forward scanning of the shift register according to the first embodiment of the present invention. Likewise, for the convenience of description, the waveform shown in FIG. 5 is the waveform corresponding to the first-stage shift register SR(1). With reference to the waveforms shown in FIG. 5 , the following paragraphs will introduce in more detail the operation of the shift register in the forward scanning according to the first embodiment of the present invention.

During forward scanning, the transistors M9 and M11 are turned on according to the voltage level of the control signal CSV. When the start pulse STV arrives, the fourth control node N4 is charged to a high voltage close to the high operating voltage VH, thereby turning on the transistors M3 , M7 and M8 . When the transistor M3 is turned on, the first control node N1 is charged to a high voltage VH1 close to the high operating voltage VH, thereby turning on the transistor M1. When the transistors M7 and M8 are turned on, the second control node N2 and the third control node N3 are discharged to a voltage level having the low operating voltage VL.

When the pulse of the clock signal CKV1 arrives, the first control node N1 is further charged to another high voltage VH2 higher than the voltage VH1. At this time, the output terminal OUT also outputs a pulse signal (ie, the gate pulse of the gate driving signal G( 1 )) in response to the pulse of the clock signal CKV1 . In addition, since the pulse of the start pulse STV has ended at this time, the fourth control node N4 is discharged to the low operating voltage VL, thereby turning off the transistors M3 , M7 and M8 .

When the pulse of the clock signal CKV2 arrives, the fifth control node N5 is charged to a high voltage close to the high operating voltage VH, thereby turning on the transistor M4. When the transistor M4 is turned on, the second control node N2 is charged to a high voltage VH3 close to the high operating voltage VH, thereby turning on the transistor M2. At this time, since the transistors M1 and M2 are both turned on, the voltage of the output terminal OUT can be discharged through the transistors M1 and M2 at the same time. Therefore, the falling time T _f of the gate pulse of the gate driving signal G( 1 ) can be effectively shortened.

When the pulse of the clock signal CKV3 arrives, the transistor M5 is turned on, the third control node N3 is charged to a high voltage VH4 close to the high operating voltage VH, and the transistor M6 is turned on. When the transistor M6 is turned on, the first control node N1 is discharged to the low operating voltage VL, thereby turning off the transistor M1.

It should be noted that, in an embodiment of the present invention, the voltage levels of the high voltages VH1, VH3, VH4, etc. close to the high operating voltage VH may be equal to or slightly lower than the voltage level of the high voltage VH, while the other high voltage The voltage level of VH2 is higher than the voltage level of the high voltage VH, so that the voltage level of the gate pulse output by the shift register will not suffer from threshold loss due to the threshold voltage of the transistor M1.

Since the shift register 400 only generates pulse signals according to the waveform of the received clock signal when the transistor M1 is turned on, the period in which the first control node N1 has a high voltage level that can turn on the transistor M1 can be regarded as a shift The range in which register 400 is enabled. In other words, during forward scanning, the operations of the shift registers of each stage are activated in response to the first input signal received from the first input terminal IN1, and are deactivated in response to the clock signal received from the fourth clock input terminal C4 . In addition, when the pulse of the clock signal CKV4 received from the third clock input terminal C3 arrives, since the transistors M10 and M12 will not be turned on at this time, in this embodiment, the shift register will not respond .

FIG. 6 is a waveform diagram showing related signals and node voltages during reverse scanning of the shift register according to the first embodiment of the present invention. The waveform shown in FIG. 6 is the waveform corresponding to the shift register SR(M) of the last stage. The operation of the shift register in the reverse scan is similar to that in the forward scan, the only difference is that the pulses of the clock signals CKV4 - CKV1 are sequentially and cyclically generated in the reverse scan. Those skilled in the art can deduce the operation of the shift register during the reverse scan based on the above introduction for the forward scan, so the relevant description will not be repeated here.

FIG. 7 is a circuit diagram showing a shift register according to a second embodiment of the present invention. The shift register 700 may be any one of the shift registers SR( 1 )˜SR(M) shown in FIG. 3 , and may include an input circuit 710 , a control circuit 720 and an output circuit 730 . For convenience, the shift register 700 is regarded as the first-stage shift register SR(1) for illustration below.

The input circuit 710 is coupled to the first input terminal IN1 and the second input terminal IN2 to receive the input signal STV and G(2) respectively (ie, the gate drive signal output by the next stage shift register SR(2) ). The output circuit 730 is coupled to the first clock input terminal C1 for receiving the clock signal CKV1 , and outputs a pulse signal (ie, the gate pulse of the gate driving signal G( 1 )) at the output terminal OUT according to the clock signal CKV1 . The control circuit 720 is coupled to the output circuit 730 through the first control node N1, the second control node N2 and the third control node N3, and controls the first control node N1, the second control node N2 according to the input signal STV or G(2) and a voltage of the third control node N3 to further control the operation of the output circuit 730 .

According to an embodiment of the present invention, the output circuit 730 may include transistors M1 , M2 and a capacitor C. As shown in FIG. The transistor M1 is coupled between the first clock input terminal C1 and the output terminal OUT, and has a control electrode coupled to the first control node N1. The transistor M2 is coupled between the output terminal OUT and the low operating voltage VL, and has a control electrode coupled to the second control node N2. The transistor M1 is turned on or off according to the voltage of the first control node N1, and the transistor M2 is turned on or off according to the voltage of the second control node N2.

The input circuit 710 may include transistors M23 and M29. The transistor M23 is coupled between the high operating voltage VH and the first control node N1, and has a control electrode coupled to the first input terminal IN1. The transistor M23 is turned on or off according to the voltage of the input signal received from the first input terminal IN1 to control the voltage of the first control node N1 during forward scanning. The transistor M29 is coupled between the high operating voltage VH and the first control node N1, and has a control electrode coupled to the second input terminal IN2. The transistor M29 is turned on or off according to the voltage of the input signal received from the second input terminal IN2 to control the voltage of the first control node N1 during reverse scanning.

The control circuit 720 may include transistors M24, M25, M26, M27, M28 and M30. The transistor M24 is coupled between the high operating voltage VH and the second control node N2, and has a control electrode coupled to the second clock input terminal C2. The transistor M24 is turned on or off according to the voltage of the clock signal received from the second clock input terminal C2 to control the voltage of the second control node N2 during forward scanning. The transistor M30 is coupled between the high operating voltage VH and the second control node N2, and has a control electrode coupled to the third clock input terminal C3. The transistor M30 is turned on or off according to the voltage of the clock signal received from the third clock input terminal C3 to control the voltage of the second control node N2 during reverse scanning.

The transistor M25 is coupled between the high operating voltage VH and the third control node N3, and has a control electrode coupled to the fourth clock input terminal C4. The transistor M25 is turned on or off according to the voltage of the clock signal received from the fourth clock input terminal C4 to control the voltage of the third control node N3. The transistor M26 is coupled between the second control node N2 and the third control node N3, and has a control electrode coupled to the first clock input terminal C1. The transistor M26 is turned on or off according to the voltage of the clock signal received from the first clock input terminal C1 to control the voltage of the second control node N2.

The transistor M27 is coupled between the first control node N1 and the low operating voltage VL, and has a gate coupled to the third control node N3. The transistor M27 is turned on or off according to the voltage of the third control node N3 to control the voltage of the first control node N1. The transistor M28 is coupled between the third control node N3 and the low operating voltage VL, and has a control electrode coupled to the first control node N1. The transistor M28 is turned on or off according to the voltage of the first control node N1 to control the voltage of the third control node N3.

FIG. 8 is a waveform diagram showing related signals and node voltages during forward scanning of the shift register according to the second embodiment of the present invention. Likewise, for the convenience of description, the waveform shown in FIG. 8 is the waveform corresponding to the first-stage shift register SR(1). With reference to the waveform shown in FIG. 8 , the following paragraphs will introduce in more detail the operation of the shift register in the forward scanning according to the second embodiment of the present invention.

When the start pulse STV arrives, the transistor M23 is turned on, and the first control node N1 is charged to a high voltage VH1' close to the high operating voltage VH, thereby turning on the transistors M1 and M28. When the transistor M28 is turned on, the third control node N3 is discharged to the low operating voltage VL.

When the pulse of the clock signal CKV1 arrives, the first control node N1 is further charged to another high voltage VH2' higher than the voltage VH1'. At this time, the output terminal OUT also outputs a pulse signal (ie, the gate pulse of the gate driving signal G( 1 )) in response to the pulse of the clock signal CKV1 . In addition, the transistor M26 is also turned on in response to the pulse of the clock signal CKV1 to discharge the second control node N2 to the low operating voltage VL according to the voltage of the third control node N3. In addition, since the pulse of the start pulse STV has ended at this time, the transistor M23 is turned off.

When the pulse of the clock signal CKV2 arrives, the transistor M24 is turned on, the second control node N2 is charged to a high voltage VH3 ′ close to the high operating voltage VH, and the transistor M2 is turned on. At this time, since the transistors M1 and M2 are both turned on, the voltage of the output terminal OUT can be discharged through the transistors M1 and M2 at the same time. Therefore, the falling time T _f of the gate pulse of the gate driving signal G( 1 ) can be effectively shortened.

When the pulse of the clock signal CKV3 arrives, the transistor M25 is turned on, the third control node N3 is charged to a high voltage VH4' close to the high operating voltage VH, and the transistor M27 is turned on. When the transistor M27 is turned on, the first control node N1 is discharged to the low operating voltage VL, thereby turning off the transistor M1.

It should be noted that, in an embodiment of the present invention, the voltage levels of the high voltages VH1', VH3', VH4', etc. close to the high operating voltage VH may be equal to or slightly lower than the voltage level of the high voltage VH, while the other The voltage level of a high voltage VH2' is higher than the voltage level of the high voltage VH, so that the voltage level of the gate pulse output by the shift register will not be lost due to the threshold voltage of the transistor M1.

In addition, when the gate pulse of the gate driving signal G(2) output by the next-stage shift register SR(2) arrives, the transistor M29 is turned on. However, since the first control node N1 still has a high voltage level at this time, the gate pulse of the gate driving signal G( 2 ) will not affect the shift register.

Since the shift register 700 only generates pulse signals according to the waveform of the received clock signal when the transistor M1 is turned on, the period in which the first control node N1 has a high voltage level that can turn on the transistor M1 can be regarded as a shift The range in which register 700 is enabled. In other words, during forward scanning, the operations of the shift registers of each stage are activated in response to the first input signal received from the first input terminal IN1, and are deactivated in response to the clock signal received from the fourth clock input terminal C4 . In addition, when the pulse of the clock signal CKV4 received from the third clock input terminal C3 arrives, since the shift register has been turned off at this time, the shift register will not react. In this way, compared with the structure of the first embodiment, in the second embodiment, there is no need to use the control signals CSV and BCSV to define the scanning direction, and only need to change the pulse generation sequence of the clock signals CKV1-CKV4 to control and Define the scan direction.

FIG. 9 is a waveform diagram showing related signals and node voltages during reverse scanning of the shift register according to the second embodiment of the present invention. The waveform shown in FIG. 9 is the waveform corresponding to the shift register SR(M) of the last stage. The operation of the shift register in the reverse scan is similar to that in the forward scan, the only difference is that the pulses of the clock signals CKV4 - CKV1 are sequentially and cyclically generated in the reverse scan. Those skilled in the art can deduce the operation of the shift register during the reverse scan based on the above introduction for the forward scan, so the relevant description will not be repeated here.

As mentioned above, in the embodiment of the present invention, since the voltage of the output terminal OUT can be discharged through the transistors M1 and M2 at the same time, the falling time T _f of the gate pulse of the gate driving signal can be effectively shortened. In addition, compared to the traditional design where the voltage at the output terminal can only be discharged by the transistor M1 and thus the size of the transistor M1 cannot be reduced, in the embodiment of the present invention, since the voltage at the output terminal OUT can pass through the transistors M1 and M2 at the same time Discharged, transistor M1 can be effectively scaled down.

Even, unlike conventional designs where the size of transistor M1 (i.e., the width-to-length ratio (W/L), or when the transistor length is fixed, can refer to the width of the transistor) must be larger than the size limit of transistor M2, in the present invention In an embodiment, the size (ie, W/L or width) of transistor M1 may be smaller than that of transistor M2, and in embodiments of the present invention, both transistors M1 and M2 may be smaller than transistors M1 and M2 in conventional designs. size. In this way, the circuit area of the shift register can be effectively reduced, and the power consumption of the shift register can also be effectively reduced.

The use of ordinal numerals such as "first" and "second" used to modify elements in the claims does not imply any priority, order of precedence, order of precedence among elements, or order of steps performed by the method, Rather, it is used only as an identification to distinguish between different elements having the same name (with different ordinal numbers).

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be subject to the scope defined by the appended claims.

Claims (20)

1. a display pannel, comprising:

Gate driver circuit, comprises the shift register of multiple serial connection, and wherein at least one shift register comprises:

Input circuit, is coupled to first input end and the second input end, in order to receive the first input signal and the second input signal respectively;

Output circuit, is coupled to the first input end of clock, in order to receive the first clock signal, and according to this first clock signal in output terminal output pulse signal; And

Control circuit, this output circuit is coupled to by the first Controlling vertex, the second Controlling vertex and the 3rd Controlling vertex, and control the voltage of this first Controlling vertex, this second Controlling vertex and the 3rd Controlling vertex according to this first input signal or this second input signal, and then control the running of this output circuit.

2. display pannel as claimed in claim 1, wherein this shift register also comprises:

Commutation circuit, be coupled to second clock input end and the 3rd input end of clock, in order to receive second clock signal and the 3rd clock signal, wherein when this shift register operations is in forward scan, this second clock signal is sent to this control circuit by this commutation circuit, and when this shift register operations is in reverse scan, the 3rd clock signal is sent to this control circuit by this commutation circuit.

3. display pannel as claimed in claim 1, wherein this control circuit is more coupled to second clock input end and the 3rd input end of clock, in order to receive second clock signal and the 3rd clock signal.

4. display pannel as claimed in claim 1, wherein this output circuit comprises:

The first transistor, is coupled to this first input end of clock, this first Controlling vertex and this output terminal; And

Transistor seconds, is coupled to this output terminal, this second Controlling vertex and low operating voltage,

Wherein this first transistor switched on or closedown according to this voltage of this first Controlling vertex, and the switched on or closedown according to this voltage of this second Controlling vertex of this transistor seconds, and

Wherein after this pulse signal of output, the voltage of this output terminal is discharged by this first transistor and this transistor seconds.

5. display pannel as claimed in claim 1, wherein this control circuit comprises:

Third transistor, is coupled to high operation voltage, the 4th Controlling vertex and this first Controlling vertex;

4th transistor, is coupled to this high operation voltage, the 5th Controlling vertex and this second Controlling vertex; And

5th transistor, is coupled to this high operation voltage, the 4th input end of clock and the 3rd Controlling vertex,

Wherein this third transistor switched on or closedown according to a voltage of the 4th Controlling vertex, in order to control this voltage of this first Controlling vertex, 4th transistor is switched on or closedown according to a voltage of the 5th Controlling vertex, in order to control this voltage of this second Controlling vertex, and the 5th transistor is switched on or closedown according to a voltage of the 4th clock signal, in order to control this voltage of the 3rd Controlling vertex.

6. display pannel as claimed in claim 5, wherein this control circuit also comprises:

6th transistor, is coupled to this first Controlling vertex, the 3rd Controlling vertex and low operating voltage;

7th transistor, is coupled to this second Controlling vertex, the 4th Controlling vertex and this low operating voltage; And

8th transistor, is coupled to the 3rd Controlling vertex, the 4th Controlling vertex and this low operating voltage,

Wherein the 6th transistor switched on or closedown according to this voltage of the 3rd Controlling vertex, in order to control this voltage of this first Controlling vertex, 7th transistor is switched on or closedown according to a voltage of the 4th Controlling vertex, in order to control this voltage of this second Controlling vertex, and the 8th transistor is switched on or closedown according to this voltage of the 4th Controlling vertex, in order to control this voltage of the 3rd Controlling vertex.

7. display pannel as claimed in claim 3, wherein this input circuit comprises:

Third transistor, is coupled to high operation voltage, this first input end and this first Controlling vertex,

And this control circuit comprises:

4th transistor, is coupled to this high operation voltage, this second clock input end and this second Controlling vertex; And

5th transistor, is coupled to this high operation voltage, the 4th input end of clock and the 3rd Controlling vertex,

Wherein this third transistor switched on or closedown according to a voltage of this first input signal, in order to control this voltage of this first Controlling vertex, 4th transistor is switched on or closedown according to the voltage of this second clock signal, in order to control this voltage of this second Controlling vertex, and the 5th transistor is switched on or closedown according to a voltage of the 4th clock signal, in order to control this voltage of the 3rd Controlling vertex.

8. display pannel as claimed in claim 7, wherein this control circuit also comprises:

6th transistor, is coupled to this second Controlling vertex, this first input end of clock and the 3rd Controlling vertex;

7th transistor, is coupled to this first Controlling vertex, the 3rd Controlling vertex and low operating voltage; And

8th transistor, is coupled to the 3rd Controlling vertex, this first Controlling vertex and this low operating voltage,

Wherein the 6th transistor switched on or closedown according to a voltage of this first clock signal, in order to control this voltage of this second Controlling vertex, 7th transistor is switched on or closedown according to this voltage of the 3rd Controlling vertex, in order to control this voltage of this first Controlling vertex, and the 8th transistor is switched on or closedown according to this voltage of this first Controlling vertex, in order to control this voltage of the 3rd Controlling vertex.

9. display pannel as claimed in claim 8, wherein this input circuit also comprises:

9th transistor, is coupled to this high operation voltage, this second input end and this first Controlling vertex,

And this control circuit also comprises:

Tenth transistor, is coupled to this high operation voltage, the 3rd input end of clock and this second Controlling vertex.

10. display pannel as claimed in claim 1, wherein each shift register receives at least four clock signals, and the negative edge of rising edge another clock signal contiguous of wherein clock signal in described clock signal.

11. display pannels as claimed in claim 4, wherein the width of this transistor seconds is greater than the width of this first transistor.

12. 1 kinds of bidirectional shift register circuit, in order to produce multiple gate drive signal, this bidirectional shift register circuit comprises multiple shift register, and wherein at least one shift register comprises:

Input circuit, is coupled to first input end and the second input end, in order to receive the first input signal and the second input signal respectively;

Output circuit, is coupled to the first input end of clock, in order to receive the first clock signal, and according to this first clock signal at output terminal output pulse signal;

Control circuit, this output circuit is coupled to by the first Controlling vertex, the second Controlling vertex and the 3rd Controlling vertex, and control the voltage of this first Controlling vertex, this second Controlling vertex and the 3rd Controlling vertex according to this first input signal or this second input signal, and then control the running of this output circuit;

Second clock input end, in order to receive second clock signal; And

3rd input end of clock, in order to receive the 3rd clock signal,

Wherein when this shift register operations is in forward scan, the rising edge of negative edge this second clock signal contiguous of this first clock signal, and when this shift register operations is in reverse scan, the rising edge of contiguous 3rd clock signal of negative edge of this first clock signal.

13. bidirectional shift register circuit as claimed in claim 12, wherein this shift register also comprises:

Commutation circuit, be coupled to this second clock input end and the 3rd input end of clock, in order to receive this second clock signal and the 3rd clock signal, wherein when this shift register operations is in forward scan, this second clock signal is sent to this control circuit by this commutation circuit, and when this shift register operations is in reverse scan, the 3rd clock signal is sent to this control circuit by this commutation circuit.

14. bidirectional shift register circuit as claimed in claim 12, wherein this output circuit comprises:

The first transistor, is coupled to this first input end of clock, this first Controlling vertex and this output terminal; And

Transistor seconds, is coupled to this output terminal, this second Controlling vertex and low operating voltage,

Wherein this first transistor switched on or closedown according to this voltage of this first Controlling vertex, and the switched on or closedown according to this voltage of this second Controlling vertex of this transistor seconds, and

Wherein after this pulse signal of output, the voltage of this output terminal is discharged by this first transistor and this transistor seconds.

15. bidirectional shift register circuit as claimed in claim 12, wherein this control circuit comprises:

Third transistor, is coupled to high operation voltage, the 4th Controlling vertex and this first Controlling vertex;

4th transistor, is coupled to this high operation voltage, the 5th Controlling vertex and this second Controlling vertex; And

5th transistor, is coupled to this high operation voltage, the 4th input end of clock and the 3rd Controlling vertex,

Wherein this third transistor switched on or closedown according to the voltage of the 4th Controlling vertex, in order to control this voltage of this first Controlling vertex, 4th transistor is switched on or closedown according to the voltage of the 5th Controlling vertex, in order to control this voltage of this second Controlling vertex, and the 5th transistor is switched on or closedown according to the voltage of the 4th clock signal, in order to control this voltage of the 3rd Controlling vertex.

16. bidirectional shift register circuit as claimed in claim 15, wherein this control circuit also comprises:

6th transistor, is coupled to this first Controlling vertex, the 3rd Controlling vertex and low operating voltage;

7th transistor, is coupled to this second Controlling vertex, the 4th Controlling vertex and this low operating voltage; And

8th transistor, is coupled to the 3rd Controlling vertex, the 4th Controlling vertex and this low operating voltage,

Wherein the 6th transistor switched on or closedown according to this voltage of the 3rd Controlling vertex, in order to control this voltage of this first Controlling vertex, 7th transistor is switched on or closedown according to the voltage of the 4th Controlling vertex, in order to control this voltage of this second Controlling vertex, and the 8th transistor is switched on or closedown according to this voltage of the 4th Controlling vertex, in order to control this voltage of the 3rd Controlling vertex.

17. bidirectional shift register circuit as claimed in claim 13, wherein this input circuit comprises:

Third transistor, is coupled to high operation voltage, this first input end and this first Controlling vertex,

And this control circuit comprises:

4th transistor, is coupled to this high operation voltage, this second clock input end and this second Controlling vertex; And

5th transistor, is coupled to this high operation voltage, the 4th input end of clock and the 3rd Controlling vertex,

Wherein this third transistor switched on or closedown according to a voltage of this first input signal, in order to control this voltage of this first Controlling vertex, 4th transistor is switched on or closedown according to the voltage of this second clock signal, in order to control this voltage of this second Controlling vertex, and the 5th transistor is switched on or closedown according to a voltage of one the 4th clock signal, in order to control this voltage of the 3rd Controlling vertex.

18. bidirectional shift register circuit as claimed in claim 17, wherein this control circuit also comprises:

6th transistor, is coupled to this second Controlling vertex, this first input end of clock and the 3rd Controlling vertex;

7th transistor, is coupled to this first Controlling vertex, the 3rd Controlling vertex and low operating voltage; And

8th transistor, is coupled to the 3rd Controlling vertex, this first Controlling vertex and this low operating voltage,

Wherein the 6th transistor switched on or closedown according to a voltage of this first clock signal, in order to control this voltage of this second Controlling vertex, 7th transistor is switched on or closedown according to this voltage of the 3rd Controlling vertex, in order to control this voltage of this first Controlling vertex, and the 8th transistor is switched on or closedown according to this voltage of this first Controlling vertex, in order to control this voltage of the 3rd Controlling vertex.

19. bidirectional shift register circuit as claimed in claim 18, wherein this input circuit also comprises:

9th transistor, is coupled to this high operation voltage, this second input end and this first Controlling vertex,

And this control circuit also comprises:

Tenth transistor, is coupled to this high operation voltage, the 3rd input end of clock and this second Controlling vertex.

20. bidirectional shift register circuit as claimed in claim 14, wherein the width of this transistor seconds is greater than the width of this first transistor.