CN105575306A - Display panel and bidirectional shift register circuit - Google Patents
Display panel and bidirectional shift register circuit Download PDFInfo
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- CN105575306A CN105575306A CN201410529676.XA CN201410529676A CN105575306A CN 105575306 A CN105575306 A CN 105575306A CN 201410529676 A CN201410529676 A CN 201410529676A CN 105575306 A CN105575306 A CN 105575306A
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Abstract
The invention discloses a display panel and a bidirectional shift register circuit. The display panel comprises a grid driving circuit. The grid driving circuit comprises a plurality of serially-connected shift registers. At least one shift registers comprises an input circuit, an output circuit, and a control circuit. The input circuit is coupled with a first input end and a second input end, which are respectively used for receiving a first input signal and a second input signal. The output circuit is coupled with a first clock input end, which is used for receiving a first clock signal, and a pulse signal can be output by the output end according to the first clock signal. The control circuit is coupled with the output circuit by a first control node, a second control node, and a third control node, and can be used to control the voltage of the first control node, the voltage of the second control node, and the voltage of the third control node according to the first input signal or the second input signal, and then the operation of the output circuit can be controlled.
Description
Technical field
The present invention relates to a kind of bidirectional shift register, particularly a kind of can effectively shortening exports pulse fall time and the bidirectional shift register reducing power consumption.
Background technology
Shift register (shiftregister) is widely used in data drive circuit and gate driver circuit, in order to control the sequential of each data line sampled data signal respectively, and is the sequential that each gate line produces sweep signal.In data drive circuit, shift register chooses signal to each data line in order to export one, makes view data can sequentially be written into each data line.On the other hand, in gate driver circuit, shift register in order to produce one scan signal to each gate line, in order to sequentially the picture signal being supplied to each data line to be write the pixel of a picture element matrix.
Conventional shift register only can produce sampled signal or sweep signal with single scanning order.But single scanning order cannot meet the demand of image display system product now.Such as, the display screen of some digital cameras can be rotated according to the angles of camera.In addition, some image display systems can comprise the function of Rotation screen.Therefore, need a kind of brand-new bidirectional shift register framework, it different scanning order can produce output signal.And effectively can shorten and export pulse fall time and reduce power consumption.
Summary of the invention
The present invention discloses a kind of display pannel, comprises a gate driver circuit.Gate driver circuit comprises the shift register of multiple serial connection.At least one shift register comprises an input circuit, an output circuit and a control circuit.Input circuit is coupled to first input end and the second input end, in order to receive the first input signal and the second input signal respectively.Output circuit is coupled to the first input end of clock, in order to receive the first clock signal, and according to the first clock signal at output terminal output pulse signal.Control circuit is coupled to output circuit by the first Controlling vertex, the second Controlling vertex and the 3rd Controlling vertex, and control a voltage of the first Controlling vertex, the second Controlling vertex and the 3rd Controlling vertex according to the first input signal or the second input signal, and then control the running of output circuit.
The present invention also proposes a kind of bidirectional shift register circuit, in order to produce multiple gate drive signal.Bidirectional shift register circuit comprises multiple shift register, and wherein at least one shift register comprises an input circuit, an output circuit, a control circuit, a second clock input end and one the 3rd input end of clock.Input circuit is coupled to a first input end and one second input end, in order to receive one first input signal and one second input signal respectively.Output circuit is coupled to one first input end of clock, in order to receive one first clock signal, and exports a pulse signal according to the first clock signal at an output terminal.Control circuit is coupled to output circuit by one first Controlling vertex, one second Controlling vertex and one the 3rd Controlling vertex, and control a voltage of the first Controlling vertex, the second Controlling vertex and the 3rd Controlling vertex according to the first input signal or the second input signal, and then control the running of output circuit.Second clock input end is in order to receive a second clock signal.3rd input end of clock is in order to receive one the 3rd clock signal.When shift register operations is in forward scan, one rising edge of the contiguous second clock signal of one negative edge of the first clock signal, and when shift register operations is in reverse scan, a rising edge of contiguous 3rd clock signal of a negative edge of the first clock signal.
Accompanying drawing explanation
Fig. 1 is the display equipment calcspar of display according to one embodiment of the invention.
Fig. 2 is read clock signal waveform example figure.
Fig. 3 is the bidirectional shift register circuit calcspar of display according to one embodiment of the invention.
Fig. 4 is the shift-register circuit figure of display according to the first embodiment of the present invention.
Fig. 5 is the signal and node voltage oscillogram that the shift register of display according to the first embodiment of the present invention is relevant when forward scan.
Fig. 6 is the signal and node voltage oscillogram that the shift register of display according to the first embodiment of the present invention is relevant when reverse scan.
Fig. 7 shows shift-register circuit figure described according to a second embodiment of the present invention.
Fig. 8 shows the shift register described according to a second embodiment of the present invention signal relevant when forward scan and node voltage oscillogram.
Fig. 9 shows shift register described according to a second embodiment of the present invention signal relevant when reverse scan and node voltage oscillogram.
[symbol description]
100 ~ display equipment;
101 ~ display pannel;
102 ~ input block;
110 ~ gate driver circuit;
120 ~ data drive circuit;
130 ~ picture element matrix;
140 ~ control chip;
201,202 ~ waveform;
300 ~ bidirectional shift register circuit;
400,700, SR (1), SR (2), SR (3), SR (4), SR (M) ~ shift register;
410,710 ~ input circuit;
420,720 ~ control circuit;
430,730 ~ output circuit;
440 ~ commutation circuit;
BCSV, CSV ~ control signal;
C ~ electric capacity;
C1 ~ the first input end of clock;
C2 ~ second clock input end;
C3 ~ the 3rd input end of clock;
C4 ~ the 4th input end of clock;
CKV1, CKV2, CKV3, CKV4 ~ clock signal;
G (1), G (2), G (M-1), G (M) ~ gate drive signal;
IN1 ~ first input end;
IN2 ~ the second input end;
M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M23, M24, M25, M26, M27, M28, M29, M30 ~ transistor;
N1 ~ the first Controlling vertex;
N2 ~ the second Controlling vertex;
N3 ~ the 3rd Controlling vertex;
N4 ~ the 4th Controlling vertex;
N5 ~ the 5th Controlling vertex;
OUT ~ output terminal;
STV ~ initial pulse;
T
f1, T
f2~ fall time;
VL ~ low operating voltage;
VH ~ high operation voltage;
VH1, VH1 ', VH2, VH2 ', VH3, VH3 ', VH4, VH4 ' ~ high voltage.
Embodiment
For making above and other object of the present invention, feature and advantage can become apparent, cited below particularly go out preferred embodiment, and coordinate accompanying drawing, elaborate.
Fig. 1 is the display equipment calcspar of display according to one embodiment of the invention.As shown in the figure, display equipment 100 can comprise display pannel 101, data drive circuit 120 and a control chip 140, and wherein display pannel 101 comprises gate driver circuit 110 and a picture element matrix 130.Gate driver circuit 110 is in order to produce multiple gate drive signal to drive multiple pixels of picture element matrix 130.Data drive circuit 120 is in order to produce multiple data drive signal to provide view data to multiple pixels of picture element matrix 130.Control chip 140, in order to produce multiple clock signal, comprises clock signal, reset signal and initial pulse etc.
In addition, display equipment 100 can comprise an input block 102 further.Input block 102, for receiving picture signal, shows image to control display pannel 101.According to embodiments of the invention, display equipment 100 can be applicable in an electronic installation, wherein electronic installation has numerous embodiments, comprising: a mobile phone, a digital camera, a personal digital assistant, a mobile computer, a desktop PC, a televisor, a vapour vehicle display, a portable optic disk are dialled and put device or any device comprising image display function.
According to one embodiment of the invention, gate driver circuit 110 can be designed to the gate driver circuit of monolateral driving, and be arranged on the side of picture element matrix 130, or the gate driver circuit of bilateral driving can be designed to, and be arranged on the both sides of picture element matrix 130, and the present invention is not limited to any one embodiment.
In addition, according to one embodiment of the invention, according to the design of monolateral driving or bilateral driving, gate driver circuit 110 can comprise one or more shift-register circuit, described shift-register circuit is bidirectional shift register circuit, in order to support the running of two kinds of different scanning directions (forward scan and reverse scan).In an embodiment of the present invention, bidirectional shift register circuit can comprise the shift register (ShiftRegister of multiple serial connection, be abbreviated as SR), its shift register at different levels sequentially can produce a gate drive signal to each gate line, in order to drive the pixel on each gate line.For example, when bidirectional shift register circuit operates in forward scan, shift register at different levels with one first order (such as, SR (1) ~ SR (M), wherein M represents the quantity of shift register, and M is a positive integer) sequentially export corresponding gate drive signal, and when bidirectional shift register circuit operates in reverse scan, shift register at different levels sequentially exports corresponding gate drive signal with one second order (such as, SR (M) ~ SR (1)).
Generally speaking, when the resolution of display pannel increases, required shift register quantity also must along with increase.But once shift register quantity increases, for the clock run signal being supplied to shift-register circuit, the load of bearing also can increase, and the clock signal causing distal travel register to receive is easier to the situation of waveform distortion thereupon.
Fig. 2 is read clock signal waveform example figure.Waveform 201 represents the clock signal waveform received by near-end shift register, waveform 202 represents the clock signal waveform received by distal travel register, in this, described near-end and far-end represent shift register and the relative distance of control chip providing clock signal.As can be seen from Figure, fall time (fallingtime) T of the pulse of the clock signal received by distal travel register
f2more than T fall time of the pulse of the clock signal received by near-end shift register
f1come long.But, have in the design of multiple leveled time (horizontaltime) in the pulse width of clock signal, the negative edge of clock signal is the material time point of reads image data, and therefore, the fall time of the pulse of clock signal must be more short better.
Thus, in the conventional technology in order to the pulse of one of clock signal as grid impulse transistor (such as, corresponding to the present invention the 4th, 7 figure embodiment shown in transistor M1) size cannot be reduced, to avoid extending fall time of grid impulse.But large-sized transistor M1 causes circuit area effectively to reduce, and has higher power dissipation.Because be this, the present invention proposes a kind ofly can effectively shorten grid impulse fall time and reduce the bidirectional shift register of power consumption.Following paragraph will do more detailed introduction.
Fig. 3 is the bidirectional shift register circuit calcspar of display according to one embodiment of the invention.As shown in the figure, bidirectional shift register circuit 300 can comprise shift register SR (the 1) ~ SR (M) of multiple serial connection.Each shift register at least can comprise first input end IN1, the second input end IN2, output terminal OUT, the first input end of clock C1, second clock input end C2, the 3rd input end of clock C3 and the 4th input end of clock C4.First order shift register SR (1) receives initial pulse STV as the first input signal at first input end IN1, and other grade of shift register SR (2) ~ SR (M) receives the grid impulse that (1) ~ SR (M-1) exports of previous stage shift register SR as the first input signal at first input end IN1 respectively.Afterbody shift register SR (M) receives initial pulse STV as the second input signal at the second input end IN2, and other grade of shift register SR (M-1) ~ SR (1) receives the grid impulse that (M) ~ SR (2) exports of rear stage shift register SR as the second input signal at the second input end IN2 respectively.
In addition, according to one embodiment of the invention, each shift register can receive at least four clock signals, such as, and the clock signal CKV 1 shown in figure, CKV2, CKV3 and CKV4.As shown in Figure 3, each shift register follows a set rule in each clock input clock signal.In an embodiment of the present invention, a rising edge of a clock signal is better with a negative edge of a contiguous time clock signal.In addition, when forward scan, the pulse of clock signal CKV 1 ~ CKV4 sequentially circulates and is produced, and when reverse scan, the pulse changing clock signal CKV 4 ~ CKV1 into sequentially circulates and produced.As shown in Fig. 5 and Fig. 8, when forward scan, one negative edge of one negative edge of the contiguous clock signal CKV 4 of one rising edge of clock signal CKV 1, the contiguous clock signal CKV 1 of a rising edge of clock signal CKV 2 by that analogy, and the pulse of clock signal CKV 1 ~ CKV4 sequentially circulates and is produced.In addition.As shown in Fig. 6 and Fig. 9, when reverse scan, a negative edge of the contiguous clock signal CKV 1 of a rising edge of clock signal CKV 4, the contiguous clock signal CKV 4 of a rising edge of clock signal CKV 3 and the pulse of clock signal CKV 4 ~ CKV1 sequentially circulate and are produced.
In addition, according to one embodiment of the invention, when forward scan, the running of shift register at different levels is activated in response to the first input signal received from first input end IN1, and is closed in response to the clock signal received from the 4th input end of clock C4.When reverse scan, the running of shift register at different levels is activated in response to the second input signal received from the second input end IN2, and is closed in response to the clock signal received from the 4th input end of clock C4.Following paragraph will introduce multiple shift-register circuits proposed by the invention in more detail.
Fig. 4 is the shift-register circuit figure of display according to the first embodiment of the present invention.Shift register 400 can be any one of the shift register SR (1) shown in Fig. 3 ~ SR (M), and can comprise input circuit 410, control circuit 420, output circuit 430 and commutation circuit 440.For simplicity, below shift register 400 is considered as first order shift register SR (1) to explain.
Input circuit 410 is coupled to first input end IN1 and the second input end IN2, in order to receive input signal STV and G (2) (that is, next stage shift register SR (2) export gate drive signal) respectively.Output circuit 430 is coupled to the first input end of clock C1, in order to receive clock signal CKV1, and exports a pulse signal (that is, the grid impulse of gate drive signal G (1)) according to clock signal CKV 1 at output terminal OUT.Control circuit 420 is coupled to output circuit 430 by the first Controlling vertex N1, the second Controlling vertex N2 and the 3rd Controlling vertex N3, and control a voltage of the first Controlling vertex N1, the second Controlling vertex N2 and the 3rd Controlling vertex N3 according to input signal STV or G (2), and then control the running of output circuit 430.Commutation circuit 440 is coupled to second clock input end C2 and the 3rd input end of clock C3, in order to receive clock signal CKV2 and clock signal CKV 4.
In this embodiment, input circuit 410 and commutation circuit 440 more receive two control signal CSV and BCSV.Control signal CSV and BCSV is in order to define direction of scanning.For example, when operating in forward scan, control signal CSV has the first voltage level and control signal BCSV has the second voltage level.Now, input signal STV only can be sent to control circuit 420 by input circuit 410, and clock signal CKV 2 only can be sent to control circuit 420 by commutation circuit 440.When operating in reverse scan, control signal CSV has the second voltage level and control signal BCSV has the first voltage level.Now, input signal G (2) only can be sent to control circuit 420 by input circuit 410, and clock signal CKV 4 only can be sent to control circuit 420 by commutation circuit 440.
According to one embodiment of the invention, output circuit 430 can comprise transistor M1, M2 and electric capacity C.Transistor M1 is coupled between the first input end of clock C1 and output terminal OUT, and has a control pole and be coupled to the first Controlling vertex N1.Transistor M2 is coupled between output terminal OUT and low operating voltage VL, and has a control pole and be coupled to the second Controlling vertex N2.Transistor M1 is switched on or closedown according to the voltage of the first Controlling vertex N1, and transistor M2 switched on or closedown according to the voltage of the second Controlling vertex N2.
Control circuit 420 can comprise transistor M3 ~ M8.Transistor M3 is coupled between high operation voltage VH and the first Controlling vertex N1, and has a control pole and be coupled to the 4th Controlling vertex N4.Transistor M3 is switched on or closedown according to a voltage of the 4th Controlling vertex N4, in order to control the voltage of the first Controlling vertex N1.Transistor M4 is coupled between high operation voltage VH and the second Controlling vertex N2, and has a control pole and be coupled to the 5th Controlling vertex N5.Transistor M4 is switched on or closedown according to a voltage of the 5th Controlling vertex N5, in order to control the voltage of the second Controlling vertex N2.Transistor M5 is coupled between high operation voltage VH and the 3rd Controlling vertex N3, and has a control pole and be coupled to the 4th input end of clock C4.Transistor M5 is switched on or closedown according to a voltage of clock signal CKV 3, in order to control the voltage of the 3rd Controlling vertex N3.
Transistor M6 is coupled between the first Controlling vertex N1 and low operating voltage VL, and has a control pole and be coupled to the 3rd Controlling vertex N3.Transistor M6 is switched on or closedown according to a voltage of the 3rd Controlling vertex N3, in order to control the voltage of the first Controlling vertex N1.Transistor M7 is coupled between the second Controlling vertex N2 and low operating voltage VL, and has a control pole and be coupled to the 4th Controlling vertex N4.Transistor M7 is switched on or closedown according to a voltage of the 4th Controlling vertex N4, in order to control the voltage of the second Controlling vertex N2.Transistor M8 is coupled between the 3rd Controlling vertex N3 and low operating voltage VL, and has a control pole and be coupled to the 4th Controlling vertex N4.Transistor M8 is switched on or closedown according to a voltage of the 4th Controlling vertex N4, in order to control the voltage of the 3rd Controlling vertex N3.
Input circuit 410 can comprise transistor M9 and M10.Transistor M9 is coupled between first input end IN1 and the 4th Controlling vertex N4, and has control pole reception control signal CSV.Transistor M10 is coupled between the second input end IN2 and the 4th Controlling vertex N4, and has control pole reception control signal BCSV.Transistor M9 and M10 is or closedown switched on according to the voltage level of control signal CSV and BCSV respectively, in order to selectivity, input signal STV or G (2) is sent to control circuit 420.
Commutation circuit 440 can comprise transistor M11 and M12.Transistor M11 is coupled between second clock input end C2 and the 5th Controlling vertex N5, and has control pole reception control signal CSV.Transistor M12 is coupled between the 3rd input end of clock C3 and the 5th Controlling vertex N5, and has control pole reception control signal BCSV.Transistor M11 and M12 is or closedown switched on according to the voltage level of control signal CSV and BCSV respectively, in order to selectivity, clock signal CKV 2 or CKV4 is sent to control circuit 420.
Fig. 5 is the signal and node voltage oscillogram that the shift register of display according to the first embodiment of the present invention is relevant when forward scan.Similarly, for convenience of description, the waveform shown in Fig. 5 is that first order shift register SR (1) makes corresponding waveform.Waveform shown in composition graphs 5, following paragraph does more detailed introduction by for the shift register described in the first embodiment of the present invention in the running of forward scan.
When forward scan, transistor M9 and M11 can be switched in response to the voltage level of control signal CSV.When initial pulse STV arrives at, the 4th Controlling vertex N4 is charged to the high voltage had close to high operation voltage VH, and then turn-on transistor M3, M7 and M8.When transistor M3 is switched on, the first Controlling vertex N1 is charged to the high voltage VH1 had close to high operation voltage VH, and then turn-on transistor M1.When transistor M7 and M8 is switched on, the second Controlling vertex N2 and the 3rd Controlling vertex N3 is discharged to a voltage level with low operating voltage VL.
When the pulses arrive of clock signal CKV1, the first Controlling vertex N1 further can be charged to another high voltage VH2 higher than voltage VH1.Now, output terminal OUT also can export a pulse signal (that is, the grid impulse of gate drive signal G (1)) in response to the pulse of clock signal CKV 1.In addition, because the pulse of now initial pulse STV terminates, the 4th Controlling vertex N4 is discharged to low operating voltage VL, and then closes transistor M3, M7 and M8.
When the pulses arrive of clock signal CKV2, the 5th Controlling vertex N5 is charged to the high voltage had close to high operation voltage VH, and then turn-on transistor M4.When transistor M4 is switched on, the second Controlling vertex N2 is charged to the high voltage VH3 had close to high operation voltage VH, and then turn-on transistor M2.Now, because transistor M1 and M2 is all switched on, the voltage of output terminal OUT can be discharged by transistor M1 and M2 simultaneously.Therefore, T fall time of the grid impulse of gate drive signal G (1) can effectively be shortened
f.
When the pulses arrive of clock signal CKV3, transistor M5 can be switched on, and the 3rd Controlling vertex N3 is charged to the high voltage VH4 had close to high operation voltage VH, and then turn-on transistor M6.When transistor M6 is switched on, the first Controlling vertex N1 is discharged to low operating voltage VL, and then closes transistor M1.
It should be noted that, in an embodiment of the present invention, voltage level close to high voltage VH1, VH3, VH4 etc. of high operation voltage VH can be the voltage level being equal to or slightly less than high voltage VH, and the voltage level of another high voltage VH2 can higher than the voltage level of high voltage VH, the voltage level of the grid impulse that shift register is exported can not consume (thresholdloss) to some extent because of the critical voltage of transistor M1.
Because shift register 400 only can produce pulse signal according to the clock signal waveform received when transistor M1 conducting, therefore, the first Controlling vertex N1 has and the interval of high-voltage level of turn-on transistor M1 can be regarded as the interval that shift register 400 is activated.In other words, when forward scan, the running of shift register at different levels is activated in response to the first input signal received from first input end IN1, and is closed in response to the clock signal received from the 4th input end of clock C4.In addition, when when the pulses arrive of the clock signal CKV 4 received by the 3rd input end of clock C3, because now transistor M10 and M12 can not be switched on, therefore, in this embodiment, shift register can not respond.
Fig. 6 is the signal and node voltage oscillogram that the shift register of display according to the first embodiment of the present invention is relevant when reverse scan.Waveform shown in Fig. 6 is that afterbody shift register SR (M) makes corresponding waveform.The running of shift register when reverse scan and forward scan similar, difference is only when reverse scan, and the pulse of clock signal CKV 4 ~ CKV1 sequentially circulates and produced.Those skilled in the art when can according to the above introduction for forward scan push away shift register in reverse scan time running, therefore, related description repeats no more in this.
Fig. 7 shows shift-register circuit figure described according to a second embodiment of the present invention.Shift register 700 can be any one of the shift register SR (1) shown in Fig. 3 ~ SR (M), and can comprise input circuit 710, control circuit 720 and output circuit 730.For simplicity, below shift register 700 is considered as first order shift register SR (1) to explain.
Input circuit 710 is coupled to first input end IN1 and the second input end IN2, in order to receive input signal STV and G (2) (that is, next stage shift register SR (2) export gate drive signal) respectively.Output circuit 730 is coupled to the first input end of clock C1, in order to receive clock signal CKV1, and exports a pulse signal (that is, the grid impulse of gate drive signal G (1)) according to clock signal CKV 1 in output terminal OUT.Control circuit 720 is coupled to output circuit 730 by the first Controlling vertex N1, the second Controlling vertex N2 and the 3rd Controlling vertex N3, and control a voltage of the first Controlling vertex N1, the second Controlling vertex N2 and the 3rd Controlling vertex N3 according to input signal STV or G (2), and then control the running of output circuit 730.
According to one embodiment of the invention, output circuit 730 can comprise transistor M1, M2 and electric capacity C.Transistor M1 is coupled between the first input end of clock C1 and output terminal OUT, and has a control pole and be coupled to the first Controlling vertex N1.Transistor M2 is coupled between output terminal OUT and low operating voltage VL, and has a control pole and be coupled to the second Controlling vertex N2.Transistor M1 is switched on or closedown according to the voltage of the first Controlling vertex N1, and transistor M2 switched on or closedown according to the voltage of the second Controlling vertex N2.
Input circuit 710 can comprise transistor M23 and M29.Transistor M23 is coupled between high operation voltage VH and the first Controlling vertex N1, and has a control pole and be coupled to first input end IN1.Transistor M23 according to switched on from the voltage of the input signal received by first input end IN1 or close, in order to control the voltage of the first Controlling vertex N1 when forward scan.Transistor M29 is coupled between high operation voltage VH and the first Controlling vertex N1, and has a control pole and be coupled to the second input end IN2.Transistor M29 according to switched on from the voltage of the input signal received by the second input end IN2 or close, in order to control the voltage of the first Controlling vertex N1 when reverse scan.
Control circuit 720 can comprise transistor M24, M25, M26, M27, M28 and M30.Transistor M24 is coupled between high operation voltage VH and the second Controlling vertex N2, and has a control pole and be coupled to second clock input end C2.Transistor M24 according to switched on from the voltage of the clock signal received by second clock input end C2 or close, in order to control the voltage of the second Controlling vertex N2 when forward scan.Transistor M30 is coupled between high operation voltage VH and the second Controlling vertex N2, and has a control pole and be coupled to the 3rd input end of clock C3.Transistor M30 according to switched on from the voltage of the clock signal received by the 3rd input end of clock C3 or close, in order to control the voltage of the second Controlling vertex N2 when reverse scan.
Transistor M25 is coupled between high operation voltage VH and the 3rd Controlling vertex N3, and has a control pole and be coupled to the 4th input end of clock C4.Transistor M25 is switched on according to the voltage from the clock signal received by the 4th input end of clock C4 or closes, in order to control the voltage of the 3rd Controlling vertex N3.Transistor M26 is coupled between the second Controlling vertex N2 and the 3rd Controlling vertex N3, and has a control pole and be coupled to the first input end of clock C1.Transistor M26 is switched on according to the voltage from the clock signal received by the first input end of clock C1 or closes, in order to control the voltage of the second Controlling vertex N2.
Transistor M27 is coupled between the first Controlling vertex N1 and low operating voltage VL, and has a control pole and be coupled to the 3rd Controlling vertex N3.Transistor M27 is switched on or closedown according to the voltage of the 3rd Controlling vertex N3, in order to control the voltage of the first Controlling vertex N1.Transistor M28 be coupled to the 3rd Controlling vertex N3 and and low operating voltage VL between, and there is a control pole be coupled to system first Controlling vertex N1.Transistor M28 is switched on or closedown according to the voltage of system first Controlling vertex N1, in order to control the voltage of the 3rd Controlling vertex N3.
Fig. 8 shows the shift register described according to a second embodiment of the present invention signal relevant when forward scan and node voltage oscillogram.Similarly, for convenience of description, the waveform shown in Fig. 8 is that first order shift register SR (1) makes corresponding waveform.Waveform shown in composition graphs 8, following paragraph does more detailed introduction by for the shift register described in the second embodiment of the present invention in the running of forward scan.
When initial pulse STV arrives at, transistor M23 can be switched on, and the first Controlling vertex N1 is charged to the high voltage VH1 ' had close to high operation voltage VH, and then turn-on transistor M1 and M28.When transistor M28 is switched on, the 3rd Controlling vertex N3 can be discharged to low operating voltage VL.
When the pulses arrive of clock signal CKV1, the first Controlling vertex N1 further can be charged to another high voltage VH2 ' higher than voltage VH1 '.Now, output terminal OUT also can export a pulse signal (that is, the grid impulse of gate drive signal G (1)) in response to the pulse of clock signal CKV 1.In addition, transistor M26 also can be switched in response to the pulse of clock signal CKV 1, in order to the voltage according to the 3rd Controlling vertex N3, the second Controlling vertex N2 is discharged to low operating voltage VL.In addition, because the pulse of now initial pulse STV terminates, transistor M23 can be closed.
When the pulses arrive of clock signal CKV2, transistor M24 can be switched on, and the second Controlling vertex N2 is charged to the high voltage VH3 ' had close to high operation voltage VH, and then turn-on transistor M2.Now, because transistor M1 and M2 is all switched on, the voltage of output terminal OUT can be discharged by transistor M1 and M2 simultaneously.Therefore, T fall time of the grid impulse of gate drive signal G (1) can effectively be shortened
f.
When the pulses arrive of clock signal CKV3, transistor M25 can be switched on, and the 3rd Controlling vertex N3 is charged to the high voltage VH4 ' had close to high operation voltage VH, and then turn-on transistor M27.When transistor M27 is switched on, the first Controlling vertex N1 is discharged to low operating voltage VL, and then closes transistor M1.
It should be noted that, in an embodiment of the present invention, voltage level close to high voltage VH1 ', the VH3 ', VH4 ' etc. of high operation voltage VH can be the voltage level being equal to or slightly less than high voltage VH, and the voltage level of another high voltage VH2 ' can higher than the voltage level of high voltage VH, the voltage level of the grid impulse that shift register is exported can not consume (thresholdloss) to some extent because of the critical voltage of transistor M1.
In addition, when the grid impulse of the gate drive signal G (2) that next stage shift register SR (2) exports is arrived at, transistor M29 can be switched on.But because now the first Controlling vertex N1 still has high-voltage level, therefore the grid impulse of gate drive signal G (2) can't impact shift register.
Because shift register 700 only can produce pulse signal according to the clock signal waveform received when transistor M1 conducting, therefore, the first Controlling vertex N1 has and the interval of high-voltage level of turn-on transistor M1 can be regarded as the interval that shift register 700 is activated.In other words, when forward scan, the running of shift register at different levels is activated in response to the first input signal received from first input end IN1, and is closed in response to the clock signal received from the 4th input end of clock C4.In addition, when when the pulses arrive of the clock signal CKV 4 received by the 3rd input end of clock C3, because now shift register is closed, therefore shift register can not respond.Thus, compared to the framework of the first embodiment, in a second embodiment, without the need to using control signal CSV and BCSV to define direction of scanning, only need can control by the pulses generation order changing clock signal CKV 1 ~ CKV4 and define direction of scanning.
Fig. 9 shows shift register described according to a second embodiment of the present invention signal relevant when reverse scan and node voltage oscillogram.Waveform shown in Fig. 9 is that afterbody shift register SR (M) makes corresponding waveform.The running of shift register when reverse scan and forward scan similar, difference is only when reverse scan, and the pulse of clock signal CKV 4 ~ CKV1 sequentially circulates and produced.Those skilled in the art when can according to the above introduction for forward scan push away shift register in reverse scan time running, therefore, related description does not repeat them here.
As above-mentioned, in an embodiment of the present invention, because the voltage of output terminal OUT can be discharged by transistor M1 and M2 simultaneously, T fall time of the grid impulse of gate drive signal can therefore effectively be shortened
f.In addition, in traditional design, the voltage of output terminal only can utilize transistor M1 to discharge thus to cause the restriction that the size of transistor M1 cannot be reduced, in an embodiment of the present invention, because the voltage of output terminal OUT can be discharged by transistor M1 and M2 simultaneously, transistor M1 can be effectively reduced.
Even, be different from the size of transistor M1 in traditional design (namely, breadth length ratio (W/L), or when transistor length is fixed, the width of transistor can be referred to) restriction of the size of transistor M2 must be greater than, in an embodiment of the present invention, the size of transistor M1 (namely, W/L or width) size of transistor M2 can be less than, and in an embodiment of the present invention, the size of transistor M1 and M2 all can be less than the size of transistor M1 and M2 in traditional design.Thus, the circuit area of shift register can effectively reduce, and the power dissipation of shift register also can effectively reduce.
Do not imply the order of the precedence between any right of priority, priority ranking, each element or the step performed by method in claims in order to the use of ordinal numbers such as " first ", " second " of modified elements itself, and only distinguish the different elements with same names (there is different ordinal number) with making a check mark.
Although the present invention with preferred embodiment openly as above; so itself and be not used to limit the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on appended claims confining spectrum.
Claims (20)
1. a display pannel, comprising:
Gate driver circuit, comprises the shift register of multiple serial connection, and wherein at least one shift register comprises:
Input circuit, is coupled to first input end and the second input end, in order to receive the first input signal and the second input signal respectively;
Output circuit, is coupled to the first input end of clock, in order to receive the first clock signal, and according to this first clock signal in output terminal output pulse signal; And
Control circuit, this output circuit is coupled to by the first Controlling vertex, the second Controlling vertex and the 3rd Controlling vertex, and control the voltage of this first Controlling vertex, this second Controlling vertex and the 3rd Controlling vertex according to this first input signal or this second input signal, and then control the running of this output circuit.
2. display pannel as claimed in claim 1, wherein this shift register also comprises:
Commutation circuit, be coupled to second clock input end and the 3rd input end of clock, in order to receive second clock signal and the 3rd clock signal, wherein when this shift register operations is in forward scan, this second clock signal is sent to this control circuit by this commutation circuit, and when this shift register operations is in reverse scan, the 3rd clock signal is sent to this control circuit by this commutation circuit.
3. display pannel as claimed in claim 1, wherein this control circuit is more coupled to second clock input end and the 3rd input end of clock, in order to receive second clock signal and the 3rd clock signal.
4. display pannel as claimed in claim 1, wherein this output circuit comprises:
The first transistor, is coupled to this first input end of clock, this first Controlling vertex and this output terminal; And
Transistor seconds, is coupled to this output terminal, this second Controlling vertex and low operating voltage,
Wherein this first transistor switched on or closedown according to this voltage of this first Controlling vertex, and the switched on or closedown according to this voltage of this second Controlling vertex of this transistor seconds, and
Wherein after this pulse signal of output, the voltage of this output terminal is discharged by this first transistor and this transistor seconds.
5. display pannel as claimed in claim 1, wherein this control circuit comprises:
Third transistor, is coupled to high operation voltage, the 4th Controlling vertex and this first Controlling vertex;
4th transistor, is coupled to this high operation voltage, the 5th Controlling vertex and this second Controlling vertex; And
5th transistor, is coupled to this high operation voltage, the 4th input end of clock and the 3rd Controlling vertex,
Wherein this third transistor switched on or closedown according to a voltage of the 4th Controlling vertex, in order to control this voltage of this first Controlling vertex, 4th transistor is switched on or closedown according to a voltage of the 5th Controlling vertex, in order to control this voltage of this second Controlling vertex, and the 5th transistor is switched on or closedown according to a voltage of the 4th clock signal, in order to control this voltage of the 3rd Controlling vertex.
6. display pannel as claimed in claim 5, wherein this control circuit also comprises:
6th transistor, is coupled to this first Controlling vertex, the 3rd Controlling vertex and low operating voltage;
7th transistor, is coupled to this second Controlling vertex, the 4th Controlling vertex and this low operating voltage; And
8th transistor, is coupled to the 3rd Controlling vertex, the 4th Controlling vertex and this low operating voltage,
Wherein the 6th transistor switched on or closedown according to this voltage of the 3rd Controlling vertex, in order to control this voltage of this first Controlling vertex, 7th transistor is switched on or closedown according to a voltage of the 4th Controlling vertex, in order to control this voltage of this second Controlling vertex, and the 8th transistor is switched on or closedown according to this voltage of the 4th Controlling vertex, in order to control this voltage of the 3rd Controlling vertex.
7. display pannel as claimed in claim 3, wherein this input circuit comprises:
Third transistor, is coupled to high operation voltage, this first input end and this first Controlling vertex,
And this control circuit comprises:
4th transistor, is coupled to this high operation voltage, this second clock input end and this second Controlling vertex; And
5th transistor, is coupled to this high operation voltage, the 4th input end of clock and the 3rd Controlling vertex,
Wherein this third transistor switched on or closedown according to a voltage of this first input signal, in order to control this voltage of this first Controlling vertex, 4th transistor is switched on or closedown according to the voltage of this second clock signal, in order to control this voltage of this second Controlling vertex, and the 5th transistor is switched on or closedown according to a voltage of the 4th clock signal, in order to control this voltage of the 3rd Controlling vertex.
8. display pannel as claimed in claim 7, wherein this control circuit also comprises:
6th transistor, is coupled to this second Controlling vertex, this first input end of clock and the 3rd Controlling vertex;
7th transistor, is coupled to this first Controlling vertex, the 3rd Controlling vertex and low operating voltage; And
8th transistor, is coupled to the 3rd Controlling vertex, this first Controlling vertex and this low operating voltage,
Wherein the 6th transistor switched on or closedown according to a voltage of this first clock signal, in order to control this voltage of this second Controlling vertex, 7th transistor is switched on or closedown according to this voltage of the 3rd Controlling vertex, in order to control this voltage of this first Controlling vertex, and the 8th transistor is switched on or closedown according to this voltage of this first Controlling vertex, in order to control this voltage of the 3rd Controlling vertex.
9. display pannel as claimed in claim 8, wherein this input circuit also comprises:
9th transistor, is coupled to this high operation voltage, this second input end and this first Controlling vertex,
And this control circuit also comprises:
Tenth transistor, is coupled to this high operation voltage, the 3rd input end of clock and this second Controlling vertex.
10. display pannel as claimed in claim 1, wherein each shift register receives at least four clock signals, and the negative edge of rising edge another clock signal contiguous of wherein clock signal in described clock signal.
11. display pannels as claimed in claim 4, wherein the width of this transistor seconds is greater than the width of this first transistor.
12. 1 kinds of bidirectional shift register circuit, in order to produce multiple gate drive signal, this bidirectional shift register circuit comprises multiple shift register, and wherein at least one shift register comprises:
Input circuit, is coupled to first input end and the second input end, in order to receive the first input signal and the second input signal respectively;
Output circuit, is coupled to the first input end of clock, in order to receive the first clock signal, and according to this first clock signal at output terminal output pulse signal;
Control circuit, this output circuit is coupled to by the first Controlling vertex, the second Controlling vertex and the 3rd Controlling vertex, and control the voltage of this first Controlling vertex, this second Controlling vertex and the 3rd Controlling vertex according to this first input signal or this second input signal, and then control the running of this output circuit;
Second clock input end, in order to receive second clock signal; And
3rd input end of clock, in order to receive the 3rd clock signal,
Wherein when this shift register operations is in forward scan, the rising edge of negative edge this second clock signal contiguous of this first clock signal, and when this shift register operations is in reverse scan, the rising edge of contiguous 3rd clock signal of negative edge of this first clock signal.
13. bidirectional shift register circuit as claimed in claim 12, wherein this shift register also comprises:
Commutation circuit, be coupled to this second clock input end and the 3rd input end of clock, in order to receive this second clock signal and the 3rd clock signal, wherein when this shift register operations is in forward scan, this second clock signal is sent to this control circuit by this commutation circuit, and when this shift register operations is in reverse scan, the 3rd clock signal is sent to this control circuit by this commutation circuit.
14. bidirectional shift register circuit as claimed in claim 12, wherein this output circuit comprises:
The first transistor, is coupled to this first input end of clock, this first Controlling vertex and this output terminal; And
Transistor seconds, is coupled to this output terminal, this second Controlling vertex and low operating voltage,
Wherein this first transistor switched on or closedown according to this voltage of this first Controlling vertex, and the switched on or closedown according to this voltage of this second Controlling vertex of this transistor seconds, and
Wherein after this pulse signal of output, the voltage of this output terminal is discharged by this first transistor and this transistor seconds.
15. bidirectional shift register circuit as claimed in claim 12, wherein this control circuit comprises:
Third transistor, is coupled to high operation voltage, the 4th Controlling vertex and this first Controlling vertex;
4th transistor, is coupled to this high operation voltage, the 5th Controlling vertex and this second Controlling vertex; And
5th transistor, is coupled to this high operation voltage, the 4th input end of clock and the 3rd Controlling vertex,
Wherein this third transistor switched on or closedown according to the voltage of the 4th Controlling vertex, in order to control this voltage of this first Controlling vertex, 4th transistor is switched on or closedown according to the voltage of the 5th Controlling vertex, in order to control this voltage of this second Controlling vertex, and the 5th transistor is switched on or closedown according to the voltage of the 4th clock signal, in order to control this voltage of the 3rd Controlling vertex.
16. bidirectional shift register circuit as claimed in claim 15, wherein this control circuit also comprises:
6th transistor, is coupled to this first Controlling vertex, the 3rd Controlling vertex and low operating voltage;
7th transistor, is coupled to this second Controlling vertex, the 4th Controlling vertex and this low operating voltage; And
8th transistor, is coupled to the 3rd Controlling vertex, the 4th Controlling vertex and this low operating voltage,
Wherein the 6th transistor switched on or closedown according to this voltage of the 3rd Controlling vertex, in order to control this voltage of this first Controlling vertex, 7th transistor is switched on or closedown according to the voltage of the 4th Controlling vertex, in order to control this voltage of this second Controlling vertex, and the 8th transistor is switched on or closedown according to this voltage of the 4th Controlling vertex, in order to control this voltage of the 3rd Controlling vertex.
17. bidirectional shift register circuit as claimed in claim 13, wherein this input circuit comprises:
Third transistor, is coupled to high operation voltage, this first input end and this first Controlling vertex,
And this control circuit comprises:
4th transistor, is coupled to this high operation voltage, this second clock input end and this second Controlling vertex; And
5th transistor, is coupled to this high operation voltage, the 4th input end of clock and the 3rd Controlling vertex,
Wherein this third transistor switched on or closedown according to a voltage of this first input signal, in order to control this voltage of this first Controlling vertex, 4th transistor is switched on or closedown according to the voltage of this second clock signal, in order to control this voltage of this second Controlling vertex, and the 5th transistor is switched on or closedown according to a voltage of one the 4th clock signal, in order to control this voltage of the 3rd Controlling vertex.
18. bidirectional shift register circuit as claimed in claim 17, wherein this control circuit also comprises:
6th transistor, is coupled to this second Controlling vertex, this first input end of clock and the 3rd Controlling vertex;
7th transistor, is coupled to this first Controlling vertex, the 3rd Controlling vertex and low operating voltage; And
8th transistor, is coupled to the 3rd Controlling vertex, this first Controlling vertex and this low operating voltage,
Wherein the 6th transistor switched on or closedown according to a voltage of this first clock signal, in order to control this voltage of this second Controlling vertex, 7th transistor is switched on or closedown according to this voltage of the 3rd Controlling vertex, in order to control this voltage of this first Controlling vertex, and the 8th transistor is switched on or closedown according to this voltage of this first Controlling vertex, in order to control this voltage of the 3rd Controlling vertex.
19. bidirectional shift register circuit as claimed in claim 18, wherein this input circuit also comprises:
9th transistor, is coupled to this high operation voltage, this second input end and this first Controlling vertex,
And this control circuit also comprises:
Tenth transistor, is coupled to this high operation voltage, the 3rd input end of clock and this second Controlling vertex.
20. bidirectional shift register circuit as claimed in claim 14, wherein the width of this transistor seconds is greater than the width of this first transistor.
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| CN201410529676.XA CN105575306B (en) | 2014-10-09 | 2014-10-09 | Display pannel and bidirectional shift register circuit |
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| CN201410529676.XA CN105575306B (en) | 2014-10-09 | 2014-10-09 | Display pannel and bidirectional shift register circuit |
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