CN105553466A - CPLD-based photoelectric coded disc orthogonal pulse arbitrary decimal frequency division method - Google Patents
CPLD-based photoelectric coded disc orthogonal pulse arbitrary decimal frequency division method Download PDFInfo
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- CN105553466A CN105553466A CN201510884407.XA CN201510884407A CN105553466A CN 105553466 A CN105553466 A CN 105553466A CN 201510884407 A CN201510884407 A CN 201510884407A CN 105553466 A CN105553466 A CN 105553466A
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- cpld
- frequency division
- orthogonal pulses
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
- H03K23/68—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a base which is a non-integer
Abstract
A CPLD-based arbitrary fractional frequency division method for orthogonal pulses of a photoelectric coded disc relates to an arbitrary fractional frequency division method for orthogonal pulses of a photoelectric coded disc, in particular to an arbitrary fractional frequency division method for orthogonal pulses of a photoelectric coded disc based on a CPLD. The invention aims to solve the problems that a large amount of logic resources are consumed in the implementation process, and the operation complexity and the resource consumption are increased in the conventional FPGA-based arbitrary numerical value frequency divider implementation method. The method comprises the following steps: reading a frequency division ratio value stored in the E2 PROM; the servo system main control unit DSP performs 4-frequency multiplication counting and direction identification on code disc pulses through a QEP module in each position ring period; the CPLD receives frequency division information transmitted by the DSP. The invention belongs to the field of computer software.
Description
Technical field
The present invention relates to a kind of photoelectric code disk orthogonal pulses arbitrary small number dividing method, be specifically related to a kind of photoelectric code disk orthogonal pulses arbitrary small number dividing method based on CPLD, computer software fields.
Background technology
In servo system Position Control, motor position signal need be fed back to host computer for forming closed-loop, to show running status and its operation of monitoring of servomotor; But under normal conditions, the frequency of code-disc signal is higher, host computer cannot directly receive, and again feeds back to host computer after must carrying out scaling down processing to the orthogonal pulses of code-disc, and will to ensure when the frequent rotating of motor switches not pulse-losing ensure in the right direction.Due in some occasion, the pulse frequency that code-disc output pulse frequency and host computer receive is not integral multiple relation, so simple integral frequency divisioil can not meet practical application, must design fractional frequency division.
In the design of the fractional frequency division of routine, what mainly adopt is the preposition fractional frequency division of bimodulus.Its main thought is: suppose that frequency dividing ratio is
, first select
frequency division exports
individual pulse, then selects
frequency division exports
individual pulse, and then select
frequency division exports
individual pulse, so circulates.There is more serious shortcoming in this little counting method: due to the time delay of hardware circuit,
frequency division and
on the switching point of frequency division, burr may be produced; Work as frequency dividing ratio
time, the duty ratio of its frequency division afterpulse cannot ensure to be 50% and 75%; For realizing arbitrary small number frequency division, the CPLD resource of consumption is relatively many.
Chinese patent CN101789781A " any number frequency divider implementation method based on FPGA ", this invention achieves and utilizes FPGA and peripheral matrix circuit to achieve any number frequency division, comprising fractional frequency division, overcome the problem that may produce burr on frequency division switching point simultaneously.But this invention designs for single channel pulse frequency division, and in implementation procedure, consume a large amount of logical resources: 225 LE.In addition, this invention enumerates various types of frequency division, comprises even frequency division, frequency division by odd integers, fractional frequency division, seemingly multiple functional, but its frequency division essence is the same, and its way not only increases the complexity of operation, too increases the consumption of resource.
Summary of the invention
The present invention solves the existing any number frequency divider implementation method based on FPGA in implementation procedure, consume a large amount of logical resources, and add the problem of Operating Complexity and resource consumption, and then the photoelectric code disk orthogonal pulses arbitrary small number dividing method based on CPLD is proposed.
The present invention is the technical scheme taked that solves the problem: the concrete steps of the method for the invention are as follows:
When step one, servo-driver power on, read the divider ratio value be stored in E2PROM;
After step 2, servomotor start, servo system main control unit DSP carries out 4 frequency multiplication countings and direction qualification by QEP module to code-disc pulse within each position ring cycle;
Step 3, calculate according to 4 frequency multiplication count values and divider ratio value in step 2 the pulse number and respective cycle that in this position ring cycle, CPLD should export, the formula of this process is as follows:
Wherein,
for the QEP module count value of servo system main control unit DSP in the position ring cycle;
for frequency dividing ratio;
,
for CPLD exports total time, the CPLD system clock frequency of pulse;
,
for frequency division afterpulse number and 1/4th periodic quantities thereof;
for frequency division afterpulse is detained number;
The frequency division afterpulse information of acquisition is sent to CPLD by spi bus by step 4, servo system main control unit DSP;
Step 5, CPLD, after receiving the frequency division information that servo system main control unit DSP transmission comes, namely produce direction and the fixing orthogonal pulses of number according to the characteristic of orthogonal pulses in 0.95ms.
The invention has the beneficial effects as follows: 1, the present invention does not exist the switching problem of frequency dividing ratio in implementation procedure, so there is not the problem producing burr at frequency dividing ratio switching point; 2, in the present invention, DSP calculates the umber of pulse of divided pulse and respective cycle value according to flow chart, thus to ensure that when the frequent rotating switching of the larger and motor of frequency dividing ratio not pulse-losing.3, the present invention is for realizing code-disc pulse arbitrary small number division function, consume the macrocell 124 of EPM3256 device, the resource consumed than Chinese patent CN101789781A " any number frequency divider implementation method based on FPGA " and the preposition fractional frequency division of bimodulus is few.
Accompanying drawing explanation
Fig. 1 is frequency division information calculation flow chart of the present invention.
Embodiment
Embodiment one: composition graphs 1 illustrates present embodiment, the photoelectric code disk orthogonal pulses arbitrary small number dividing method based on CPLD described in present embodiment realizes as follows:
When step one, servo-driver power on, read the divider ratio value be stored in E2PROM;
After step 2, servomotor start, servo system main control unit DSP carries out 4 frequency multiplication countings and direction qualification by QEP module to code-disc pulse within each position ring cycle;
Step 3, calculate according to 4 frequency multiplication count values and divider ratio value in step 2 the pulse number and respective cycle that in this position ring cycle, CPLD should export, the formula of this process is as follows:
Wherein,
for the QEP module count value of servo system main control unit DSP in the position ring cycle;
for frequency dividing ratio;
,
for CPLD exports total time, the CPLD system clock frequency of pulse;
,
for frequency division afterpulse number and 1/4th periodic quantities thereof;
for frequency division afterpulse is detained number;
The frequency division afterpulse information of acquisition is sent to CPLD by spi bus by step 4, servo system main control unit DSP;
Step 5, CPLD, after receiving the frequency division information that servo system main control unit DSP transmission comes, namely produce direction and the fixing orthogonal pulses of number according to the characteristic of orthogonal pulses in 0.95ms.
Within the position ring cycle, the umber of pulse of fixed number is exported complete in order to ensure CPLD in present embodiment, have selected the total time product of frequency division afterpulse cycle and pulse number (this time be) that CPLD exports pulse is 0.95ms, thus the upper limit (UL) frequency that result in frequency division afterpulse is 20KHz.For adopting precision not to be the servo system of extra high incremental encoder, the upper limit (UL) frequency of 20KHz can meet the requirement that major part is referred and synthesized.In existing servo-driver product, the servo-driver of band code-disc pulse arbitrary small number division function is just few; And with in the servo-driver product of this function, the upper limit (UL) frequency of frequency division afterpulse is also less than 15KHz.Upper limit (UL) frequency as the J3 series of driver frequency division afterpulse of Mitsubishi is only 5KHz.
Embodiment two: composition graphs 1 illustrates present embodiment is as follows based on the control flow of servo system main control unit DSP in the step one of the photoelectric code disk orthogonal pulses arbitrary small number dividing method of CPLD described in present embodiment:
Step 3 (one), when servo system power-up initializing, servo system main control unit DSP(1) read the preset division ratio that is stored in E2PROM;
Step 3 (two), calculating code-disc feedback pulse number and direction thereof;
Step 3 (three), the accumulative feedback pulse number of calculating;
Step 3 (four), foundation frequency dividing ratio calculate the umber of pulse after frequency division and cycle;
Step 3 (five), by spi bus (3), the result of calculation in step 3 (four) is transferred to CPLD, and calculates and be detained umber of pulse.
Other composition and annexation identical with embodiment one.
Embodiment three: composition graphs 1 illustrates present embodiment is 1ms based on servo system main control unit DSP in the step 3 (two) of the photoelectric code disk orthogonal pulses arbitrary small number dividing method of CPLD in the ring cycle of each position described in present embodiment.Other composition and annexation identical with embodiment two.
Embodiment four: composition graphs 1 illustrates present embodiment, realizes producing the concrete steps of the orthogonal pulses that direction and number are fixed based on CPLD in the step 3 of the photoelectric code disk orthogonal pulses arbitrary small number dividing method of CPLD described in present embodiment as follows:
Step 5 (one), a definition pulse-period counter and pulse number counter;
When step 5 (two), CPLD system clock arrive, pulse-period counter cumulative 1; And being added to 1/4,2/4,3/4,4/4 pulse period value at pulse-period counter, the state of output orthogonal pulse changes once according to pulse direction: pulse direction is timing, and the state of output orthogonal pulse is followed successively by 10,11,01 and 00; Pulse direction is for time negative, and the state of output orthogonal pulse is followed successively by 11,10,00 and 01;
Step 5 (three), change a cycle when the state of output orthogonal pulse, pulse number counter cumulative 1; Until when pulse number counter is added to pulse number, orthogonal pulses is stopped to export.
Other composition and annexation identical with embodiment one.
Claims (4)
1. based on the photoelectric code disk orthogonal pulses arbitrary small number dividing method of CPLD, it is characterized in that: the described photoelectric code disk orthogonal pulses arbitrary small number dividing method based on CPLD realizes as follows:
When step one, servo-driver power on, read the divider ratio value be stored in E2PROM;
After step 2, servomotor start, servo system main control unit DSP carries out 4 frequency multiplication countings and direction qualification by QEP module to code-disc pulse within each position ring cycle;
Step 3, calculate according to 4 frequency multiplication count values and divider ratio value in step 2 the pulse number and respective cycle that in this position ring cycle, CPLD should export, the formula of this process is as follows:
Wherein,
for the QEP module count value of servo system main control unit DSP in the position ring cycle;
for frequency dividing ratio;
,
for CPLD exports total time, the CPLD system clock frequency of pulse;
,
for frequency division afterpulse number and 1/4th periodic quantities thereof;
for frequency division afterpulse is detained number;
The frequency division afterpulse information of acquisition is sent to CPLD by spi bus by step 4, servo system main control unit DSP;
Step 5, CPLD, after receiving the frequency division information that servo system main control unit DSP transmission comes, namely produce direction and the fixing orthogonal pulses of number according to the characteristic of orthogonal pulses in 0.95ms.
2. according to claim 1 based on the photoelectric code disk orthogonal pulses arbitrary small number dividing method of CPLD, it is characterized in that: the step calculating pulse number that in this position ring cycle, CPLD should export and respective cycle in step 3 is as follows:
Step 3 (one), when servo system power-up initializing, servo system main control unit DSP(1) read the preset division ratio that is stored in E2PROM;
Step 3 (two), calculating code-disc feedback pulse number and direction thereof;
Step 3 (three), the accumulative feedback pulse number of calculating;
Step 3 (four), foundation frequency dividing ratio calculate the umber of pulse after frequency division and cycle;
Step 3 (five), by spi bus (3), the result of calculation in step 3 (four) is transferred to CPLD, and calculates and be detained umber of pulse.
3. according to claim 2 based on the photoelectric code disk orthogonal pulses arbitrary small number dividing method of CPLD, it is characterized in that: in step 3 (two), servo system main control unit DSP is 1ms in the ring cycle of each position.
4. according to claim 1 based on the photoelectric code disk orthogonal pulses arbitrary small number dividing method of CPLD, it is characterized in that: the orthogonal pulses that in step 5, CPLD generation direction and number are fixed realizes as follows:
Step 5 (one), a definition pulse-period counter and pulse number counter;
When step 5 (two), CPLD system clock arrive, pulse-period counter cumulative 1; And being added to 1/4,2/4,3/4,4/4 pulse period value at pulse-period counter, the state of output orthogonal pulse changes once according to pulse direction: pulse direction is timing, and the state of output orthogonal pulse is followed successively by 10,11,01 and 00; Pulse direction is for time negative, and the state of output orthogonal pulse is followed successively by 11,10,00 and 01;
Step 5 (three), change a cycle when the state of output orthogonal pulse, pulse number counter cumulative 1; Until when pulse number counter is added to pulse number, orthogonal pulses is stopped to export.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106774147A (en) * | 2016-11-28 | 2017-05-31 | 金舜 | The given pulse gear in servo-driver position than automatic setting method |
| CN108336993A (en) * | 2018-01-09 | 2018-07-27 | 深圳市四方电气技术有限公司 | Encoder frequency dividing circuit |
| CN109245637A (en) * | 2018-11-16 | 2019-01-18 | 庸博（厦门）电气技术有限公司 | Servo-driver arbitrarily divides output method and servo-driver |
| CN111147069A (en) * | 2019-12-25 | 2020-05-12 | 深圳万讯自控股份有限公司 | Frequency division output method for arbitrary pulse |
| CN112653427A (en) * | 2020-12-11 | 2021-04-13 | 深圳市英威腾电气股份有限公司 | Frequency division method, frequency division device and computer readable storage medium |
-
2015
- 2015-12-03 CN CN201510884407.XA patent/CN105553466A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106774147A (en) * | 2016-11-28 | 2017-05-31 | 金舜 | The given pulse gear in servo-driver position than automatic setting method |
| CN108336993A (en) * | 2018-01-09 | 2018-07-27 | 深圳市四方电气技术有限公司 | Encoder frequency dividing circuit |
| CN109245637A (en) * | 2018-11-16 | 2019-01-18 | 庸博（厦门）电气技术有限公司 | Servo-driver arbitrarily divides output method and servo-driver |
| CN111147069A (en) * | 2019-12-25 | 2020-05-12 | 深圳万讯自控股份有限公司 | Frequency division output method for arbitrary pulse |
| CN112653427A (en) * | 2020-12-11 | 2021-04-13 | 深圳市英威腾电气股份有限公司 | Frequency division method, frequency division device and computer readable storage medium |
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Application publication date: 20160504 |