CN105514169B - Super steep doping Flouride-resistani acid phesphatase metal-oxide-semiconductor field effect transistor based on 65nm techniques - Google Patents
Super steep doping Flouride-resistani acid phesphatase metal-oxide-semiconductor field effect transistor based on 65nm techniques Download PDFInfo
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Abstract
The invention discloses a kind of based on 65nm techniques it is super it is steep fall doping Flouride-resistani acid phesphatase metal-oxide-semiconductor field effect transistor, mainly solves the problem of tradition 65nm metal-oxide-semiconductor field effect transistors OFF leakage current increase, threshold voltage shift and subthreshold swing degeneration under total dose irradiation environment.It includes P type substrate (1), epitaxial layer (2) on substrate, isolation channel (3) is surrounded by above epitaxial layer, the upper center of epitaxial layer is equipped with grid (4), source region (5) and drain region (6) are equipped in the grid both sides boundary to the epitaxial layer between isolation channel inner boundary, it is equipped with lightly-doped source drain region (7) in epitaxial layer below the boundary of grid both sides, the region being located at immediately below grid between two lightly-doped source drain regions forms raceway groove, the super steep doped region (8) of heavy doping is equipped with below raceway groove between two lightly-doped source drain regions.The present invention improves device preventing total dose radiation ability, can be used for the preparation of large scale integrated circuit.
Description
Technical field
The invention belongs to technical field of semiconductor device, more particularly to a kind of MOS field-effect transistors can be used for extensive
The preparation of integrated circuit.
Background technology
MOS field-effect transistors are one of the basic components for constituting integrated circuit, with low in energy consumption, speed is fast, integrated
The advantages that high is spent, is widely used in military and aerospace field.Total radiation dose in the spacecraft service life can
To reach hundreds of thousands ladd, therefore, the research of total extreme is critically important.Total extreme is due to radiation ionization
The electron hole pair of generation generates trap positive charge in oxide layer and generates interface trap electricity in oxide layer silicon substrate interface
Lotus, under long-term irradiation, the trapped charge of accumulation, which reaches a certain concentration, leads to the variation of OFF leakage current, I-E characteristic
Change, due to the variation of noise margin and propagation delay, total dose effects may further result in disabler.
With the diminution of device feature size, when integrated circuit enters deep-submicron field, MOS field-effect transistors
Total extreme show some new features：Gate oxide is more and more thinner, due to gate oxide itself size and
The influence of tunnelling current, gate oxide influence very little to MOS field-effect transistor Radiation Characteristics.But shallow-trench isolation STI oxidations
The ability and oxide layer for the fixed positive charge that the thickness of layer is about generated than two orders of magnitude of gate oxidation floor height, oxide layer accumulation irradiation
Thickness it is closely related, thickness is bigger, and the fixed positive charge of accumulation is more, so thick STI region is that MOS field-effect transistors exist
The region of most serious is influenced under prolonged effect of irradiation.
Cmos circuit is due to the characteristic extensive use in integrated circuits of low-power consumption, and cmos circuit is by pMOS field effect transistors
Pipe is formed as upper pull-up network, nMOS field-effect transistors as pulldown network.PMOS field-effect transistors are n-type substrate, p-type
Channel doping, the MOS field-effect transistors by hole as current-carrying subconductivity, nMOS field-effect transistors are p-substrate, N-shaped
Channel doping, the MOS field-effect transistors by electronics as current-carrying subconductivity.In cmos circuit under 65nm techniques, pMOS
Field-effect transistor has good radiation-resisting performance, but nMOS field-effect transistor anti-irradiation characteristics are bad.Thin grid oxygen
Change layer the total dose irradiation characteristic of nMOS field-effect transistors is had little effect, as shown in Figure 1, irradiation with substrate contact
STI region side wall in the trapped charge that generates leak channel can be generated in the substrate of nMOS field-effect transistors, and then cause
The threshold voltage of nMOS field-effect transistors reduces, off-state leakage current increases and Sub-Threshold Characteristic is degenerated.Studies have shown that low
Compared with low density current, substrate surface is formed near STI side walls under irradiation dose, and high-density current is in the sides STI under high irradiation dose
It is formed in the leak channel of substrate depths near wall, and the severe exacerbation of nMOS field-effect transistor Radiation Characteristics is mainly by serving as a contrast
Caused by the electric leakage of bottom depths.
Invention content
It is an object of the invention to the deficiencies for above-mentioned existing 65nm metal-oxide-semiconductor field effect transistors, propose a kind of based on 65nm works
The super steep doping Flouride-resistani acid phesphatase metal-oxide-semiconductor field effect transistor of skill, reduces substrate depths caused by irradiation and leaks electricity, improve device in radiation environment
Under reliability.
To achieve the above object, super steep doping Flouride-resistani acid phesphatase metal-oxide-semiconductor field effect transistor of the invention includes P type substrate 1 and extension
Layer 2, the top surrounding of the epitaxial layer be isolation channel 3, epitaxial layer upper center be grid 4, grid both sides boundary to isolation channel
It is source region 5 and drain region 6 in epitaxial layer between inner boundary, is lightly-doped source drain region 7 in the epitaxial layer below the boundary of grid both sides,
The region being located at immediately below grid between two lightly-doped source drain regions forms raceway groove, it is characterised in that：Two lightly-doped source drain regions
Between raceway groove below be equipped with doping concentration be 6 × 1017cm-3To 2 × 1018cm-3Heavy doping it is super it is steep fall doped region 8, with realize
Radiation hardened.
To achieve the above object, the present invention prepares the super steep doping Flouride-resistani acid phesphatase metal-oxide-semiconductor field effect transistor based on 65nm techniques
Method comprises the following processes：
1) doped epitaxial layer
Using the method for chemical vapor deposition with SiH at a temperature of 500-650 DEG C4It is reactant in p-type Si substrates
(100) epitaxial layer that growth thickness is 600-1000nm in crystal orientation, then it is 100-200nm, a concentration of 2 to carry out depth to epitaxial layer
×1017cm-3To 9 × 1017cm-3Doping；
2) isolation channel window is etched on the epitaxial layer of doping
Grow the thin SiO of 3-6nm thickness successively by dry-oxygen oxidation technique on epitaxial layer2Buffer layer and 20-25nm are thick
The Si of degree3N4Protective layer；Again in Si3N4A layer photoresist is deposited on protective layer, adds mask plate post-exposure etching photoresist to make wide
The isolation channel window of 200-400nm is spent, then removes the SiO in isolation channel window in 175-185 DEG C of hot phosphoric acid2Buffer layer with
Si3N4Protective layer；
3) isolation channel is filled, super steep doped region is made
The oxide S iO of deposit is filled in isolation channel window after cleaning2, and polish；Again in 1100-1200 DEG C of temperature
The lower thin SiO for growing 4-6nm thickness on epitaxial layer, that is, active area other than isolation channel by dry-oxygen oxidation technique of degree2Layer, meter
Calculate thin SiO2In the lower active area of layer it is super it is steep fall doping peak concentration position and diffusion length, then using doping process according to
The peak concentration position and diffusion length adulterate 6 × 10 in active area17cm-3To 2 × 1018cm-3Boron, and use HF solution
Remove thin SiO2Layer；
4) gate oxide and polysilicon gate are deposited
Deposit the HfO that equivalent gate oxide thickness is 0.7-0.9nm successively on epitaxial layer2And SiO2Gatestack oxide layer
With the polysilicon layer of 50-80nm thickness, then deposit photoresist, be added after mask plate pass through exposure, lithographic glue makes polycrystalline
Si-gate window, the polysilicon other than etching window form polysilicon gate；
5) lightly-doped source drain region and heavy-doped source drain region are made
3-5nm thickness is grown on polysilicon gate and active area by thermal oxidation technology at a temperature of 1100-1250 DEG C
SiO2Separation layer is buffered, then a layer photoresist is made on buffering separation layer, is carved by being exposed on the photoresist of grid both sides
Lose the injection window in lightly-doped source drain region, and implantation concentration is 1 × 10 in the window18-5×1018cm-3Arsenic ion, with
Make the lightly-doped source drain region for forming 30-40nm depth in the active area not covered by grid, then washes photoresist；
The Si of 20-25nm thickness is grown on buffering separation layer3N4Protective layer, then photoresist is deposited, lead to after mask plate is added
Overexposure, development, etching photoresist form heavy-doped source drain region injection window on the protective layer of grid Yu grid both sides, pass through
Reactive ion etching process removes the Si in window3N4Protective layer, the then remaining Si in grid both sides3N4Protective layer forms side wall, then
Wash photoresist；
Side wall is used to inject 1 × 10 in heavy-doped source drain region injection window as mask19-5×1019cm-3Concentration Arsenic from
Son forms the heavy-doped source drain region of 50-60nm depth；
6) after heavy-doped source drain region is formed, the SiO of polysilicon gate and epi-layer surface is removed using HF solution2Layer is completed
The super steep making for adulterating Flouride-resistani acid phesphatase nMOS field-effect tube based on 65nm techniques.
The invention has the advantages that：
1. the present invention is carried due to being equipped with the super steep doped region of heavy doping below the raceway groove between two lightly-doped source drain regions
High anti-radiation performance.
2. the present invention compared with traditional 65nm nMOS techniques, increases only a substrate and falls doping process, complex process
Spend low, the cost brought increases few, and does not bring the increase on area, does not influence the integrated level of integrated circuit.
3. the present invention increases the doping concentration of substrate depths by super steep doping process so that shallow slot under effect of irradiation
Substrate depths near isolation STI side wall is not easy transoid, reduces device caused by the electric leakage of substrate depths under high irradiation dose
Radiation Characteristics severe exacerbation, therefore, the OFF leakage current of device reduces after irradiation, and the drift of threshold voltage negative sense reduces, subthreshold value
It degenerates and reduces, enhance the ability of the preventing total dose radiation of device.
The super steep method for adulterating start position and final position is determined 4. being proposed in the present invention, by super steep doping
Starting point is selected as space charge zone position when semiconductor surface fermi level is overlapped with intrinsic Fermi level, not only increases anti-
Radiation Characteristics, and the working characteristics having had.
Simulation result shows that the present invention has stronger preventing total dose radiation ability, under the conditions of identical total dose irradiation,
The more common MOS device of OFF leakage current of super steep doping device is substantially reduced；When irradiation dose is less than 200krad, OFF state leakage
Electric current is almost without raising, and under 400krad irradiation doses, the leakage current of device also only has about 1010cm-3, than what is commonly adulterated
Device has dropped about 5 orders of magnitude, shows very good preventing total dose radiation characteristic.
Description of the drawings
Fig. 1 is to irradiate the schematic diagram that parasitic path is generated in nMOS field-effect transistors；
Fig. 2 is the super steep doping 65nm nMOS field-effect tube structure schematic diagrames of the present invention；
Fig. 3 is that the present invention prepares the super steep process flow chart for adulterating 65nm nMOS field-effect tube；
Fig. 4 is nMOS effects of 65nm nMOS field-effect tube of the present invention and routine 65nm under the conditions of high oxide trap
It should Electrical characteristic simulation figure of the pipe under various irradiation doses；
Fig. 5 is nMOS effects of 65nm nMOS field-effect tube of the present invention and routine 65nm under the conditions of protoxide trap
It should Electrical characteristic simulation figure of the pipe under various irradiation doses；
Fig. 6 is 65nm nMOS field-effect tube and routine 65nm nMOS field-effect tube of the present invention under different channel dopant concentrations
Electrical characteristic simulation figure under various irradiation doses.
Specific implementation mode
Technical solutions and effects of the present invention is described in further detail below in conjunction with attached drawing.
With reference to Fig. 2, super steep doping Flouride-resistani acid phesphatase metal-oxide-semiconductor field effect transistor of the invention includes：P type substrate 1, epitaxial layer 2, shallow slot
Isolation STI area 3, grid 4, source region 5, drain region 6, lightly-doped source drain region 7 and super steep doped region 8.P-type epitaxial layer 2 is located at substrate 1
Top, shallow-trench isolation STI region 3 is located at the top surrounding of epitaxial layer 2, and grid 4 is located at the upper center of epitaxial layer 2,4 liang of grid
It is respectively source region 5 and drain region 6 in lateral boundaries to the epitaxial layer 2 between shallow-trench isolation STI region inner boundary, under 4 both sides boundary of grid
It is lightly-doped source drain region 7 in the epitaxial layer 2 of side, super steep doped region 8 is located at two lightly-doped source drain regions, 7 lower section, this two light
Region between immediately below doped source drain region 7 and grid 4 forms raceway groove.The doping concentration of super steep doped region 8 is 6 × 1017cm-3To 2 × 1018cm-3；The region that 2 top of epitaxial layer is surrounded by shallow trench isolation region 3 is active area, on being parallel to epitaxial layer direction
The length and width of super steep doped region 8 is not by the length and width of the active area of source-drain area covering, perpendicular to epitaxial layer
The depth of super steep doped region 8 is determined by the peak depth H and diffusion length L of super steep doping in active area on direction：
Wherein εsFor the dielectric constant of semiconductor Si, k is Boltzmann constant, and T is kelvin degree, and e is electron charge
Amount, niFor intrinsic carrier concentration, NaFor substrate doping, CpeakFor lightly-doped source drain region Gauss doping peak concentration,
ypeakPeak value is adulterated with a distance from substrate surface for lightly-doped source drain region Gauss, LdiffFor the diffusion length of source-drain area.
It is similar with conventional MOS device in the operation principle of device of the present invention, but due under two lightly-doped source drain regions
In the presence of so that the substrate depths under effect of irradiation near shallow-trench isolation STI side walls is not easy transoid, reduces shallow under high irradiation dose
Device Radiation Characteristics deteriorate caused by substrate depths electric leakage near slot isolation STI side wall, therefore enhance anti-total agent of device
Measure the ability of irradiation.There are distances for super steep doped region and the channel region of epi-layer surface, to the mobility and device of carrier
Threshold voltage influence it is small, then on the working characteristics of device influence it is small.
With reference to Fig. 3, the preparation of device of the present invention provides following three kinds of embodiments：
Example 1：It is 2 × 10 to make substrate doping17cm-3, source-drain area doping concentration is 1 × 1019cm-3, source-drain area expansion
It is 50nm to dissipate length, and super steep doping concentration is 6 × 1017cm-3, super steep doping depth is 58nm, and super steep doping length is
The 65nm nMOS field-effect transistors of 5nm.
Step 1, grown epitaxial layer.
First use chemical vapor deposition method at a temperature of 650 DEG C with SiH4It is reactant in p-type Si substrates (100)
Growth thickness is the epitaxial layer of 600nm in crystal orientation；
Again 2 × 10 are adulterated by diffusion technique17cm-3The boron ion of concentration forms the p of 100nm depth in epi-layer surface
Type doped region, to adjust channel concentration.
Step 2, isolation channel is etched.
First grow the thin SiO of 3nm thickness on epitaxial layer by dry-oxygen oxidation technique at a temperature of 1200 DEG C2Buffering
Layer, then by chemical vapor deposition method with SiH4And N2It is reactant in SiO2The Si of 25nm thickness is grown on buffer layer3N4It protects
Sheath；
Then in Si3N4It deposits a layer photoresist on protective layer, is added after mask plate through exposure technology exposure photo-etching glue,
Etch Si3N4The photoresist on protective layer periphery, two isolation channel windows and two parallel with channel direction of formation width 400nm
A isolation channel window vertical with channel direction, finally cleaning removes the SiO in isolation channel window in 185 DEG C of hot phosphoric acid2
Buffer layer and Si3N4Protective layer.
Step 3, isolation channel is filled
After phosphoric acid cleaning, using chemical vapor deposition process with O at 600 DEG C2With SiH4Isolation oxidation is grown for reactant
Object SiO2, to fill isolation channel, and chemically-mechanicapolish polished；
Cleaning removes SiO in 175 DEG C of hot phosphoric acid liquid again after the completion of polishing2Buffer layer and Si3N4Protective layer.
Step 4, make doped region.
After phosphoric acid cleaning, do not covered by shallow-trench isolation STI region by dry-oxygen oxidation technique at a temperature of 1100 DEG C first
Epitaxial layer, that is, active area on grow 4nm thickness thin SiO2Layer, then calculate thin SiO2The peak of super steep doping in the lower active area of layer
It is worth concentration position H and diffusion length L：
By technological parameter：Substrate doping Na=2 × 1017cm-3, lightly-doped source drain region Gauss doping peak concentration
Cpeak=1 × 1018cm-3, source-drain area diffusion length Ldiff=50nm, lightly-doped source drain region Gauss adulterate peak value from substrate surface
Distance ypeak=0 and constant parameter：The permittivity ε of semiconductor Sis=1.036 × 10-12F/cm, Boltzmann constant
K=1.381 × 10-23J/K, kelvin degree T=300K, electronic charge e=1.602 × 10-19C, intrinsic carrier concentration
Ni=1.5 × 1010cm-3It is brought into the calculation formula of the peak depth H and diffusion length L of super steep doping, obtains：
Then existed according to the peak concentration position and diffusion length using doping process on epitaxial layer direction
Doping 6 × 10 in active area17cm-3Boron；
Finally HF solution is used to remove thin SiO2Layer.
Step 5, gate oxide is grown.
After the completion of super steep doping, first use atomic layer deposition processes on the active area with O at a temperature of 425 DEG C2With
SiH4The SiO of 0.2nm thickness is deposited for reactant2Layer；
Use atomic layer deposition processes in SiO at a temperature of 600 DEG C again2With H on layer2O and HfCl4It is deposited for reactant
The HfO of 2.8nm thickness2, i.e., the HfO that equivalent gate oxide thickness is 0.7nm is made on epitaxial layer2And SiO2Gatestack oxide layer.
Step 6, polysilicon gate is made.
With chemical vapor deposition process with SiH at a temperature of 500 DEG C4It is reactant in HfO2And SiO2Gatestack oxide layer
The polysilicon layer of upper growth 50nm thickness；
Then, the SiO of 5nm thickness is grown at a temperature of 1250 DEG C by dry-oxygen oxidation technique on the polysilicon layer2It is slow
Layer is rushed, in SiO2The Si of 30nm thickness is grown on buffer layer3N4Protective layer；
Then, in Si3N4Photoresist is deposited on protective layer, is added after mask plate and polycrystalline is made by exposure, lithographic glue
Si-gate window, the polysilicon other than etching window form polysilicon gate；
Then, the cleaning removal SiO in 180 DEG C of hot phosphoric acid liquid2Buffer layer and Si3N4Protective layer.
Step 7, lightly-doped source drain region is made.
4nm thickness SiO is grown on polysilicon gate and active area by thermal oxidation technology at a temperature of 1175 DEG C2Buffering
Separation layer；
A layer photoresist is made on buffering separation layer again, is gently mixed by being exposed on to etch on the photoresist of grid both sides
The injection window of miscellaneous source-drain area, and implantation concentration is 1 × 10 in the window18cm-3Arsenic ion so that not by grid covering
The lightly-doped source drain region of 30nm depth is formed in active area；
Finally wash photoresist.
Step 8, side wall is made.
The Si of 20nm thickness is grown on buffering separation layer3N4Photoresist is deposited after protective layer；
It is added after mask plate and weight is formed on the protective layer of grid Yu grid both sides by exposure, development, etching photoresist
Window is injected in doped source drain region；
Remove the Si in window by reactive ion etching process3N4Protective layer, the then remaining Si in grid both sides3N4Protection
Layer forms side wall, then washes photoresist.
Step 9, source and drain active area is made.
Side wall is used to inject 1 × 10 in heavy-doped source drain region injection window as mask19It is deep to form 50nm for concentration arsenic ion
The heavy-doped source drain region of degree.
Step 10, after source-drain area is formed, the SiO of polysilicon gate and epi-layer surface is removed using HF solution2Layer completes base
In the super steep doping Flouride-resistani acid phesphatase for the 65nm techniques that the super steep doping depth of this example is 58nm, super steep doping length is 5nm
NMOS field-effect tube makes.
Example 2：It is 5 × 10 to make substrate doping17cm-3, source-drain area doping concentration is 3 × 1019cm-3, source-drain area expansion
It is 55nm to dissipate length, and source-drain area diffusion length is 50nm, and super steep doping concentration is 1 × 1018cm-3, it is super it is steep fall doping depth be
54nm, the 65nm nMOS field-effect transistors that super steep doping length is 20nm.
Step 1, grown epitaxial layer.
1.1) use chemical vapor deposition method at a temperature of 600 DEG C with SiH4It is raw in P type substrate for reactant
Long thickness is the epitaxial layer of 800nm；
1.2) 5 × 10 are adulterated by diffusion technique17cm-3The boron ion of concentration forms 150nm depth in epi-layer surface
P-type doped region, to adjust channel concentration.
Step 2 etches isolation channel.
2.1) the thin SiO of 6nm thickness is grown on epitaxial layer by dry-oxygen oxidation technique at a temperature of 1100 DEG C2Buffering
Layer, then by chemical vapor deposition method with SiH4And N2It is reactant in SiO2The Si of 22nm thickness is grown on buffer layer3N4It protects
Sheath；
2.2) in Si3N4It deposits a layer photoresist on protective layer, is added after mask plate through exposure technology exposure photo-etching glue,
Etch Si3N4The photoresist on protective layer periphery, two isolation channel windows and two parallel with channel direction of formation width 200nm
A isolation channel window vertical with channel direction；
2.3) SiO in 175 DEG C of hot phosphoric acid in cleaning removal isolation channel window2Buffer layer and Si3N4Protective layer.
Step 3 fills isolation channel
3.1) after the completion of polishing, the cleaning removal SiO in 175 DEG C of hot phosphoric acid liquid2Buffer layer and Si3N4Protective layer；
3.2) after phosphoric acid cleaning, using chemical vapor deposition process with O at 500 DEG C2With SiH4It grows and is isolated for reactant
Oxide S iO2, to fill isolation channel, and chemically-mechanicapolish polished；
3.3) after the completion of polishing, the cleaning removal SiO in 185 DEG C of hot phosphoric acid liquid2Buffer layer and Si3N4Protective layer.
Step 4 makes doped region.
4.1) thin SiO is calculated2The peak concentration position H and diffusion length L of super steep doping in the lower active area of layer：
If substrate doping Na=5 × 1017cm-3, lightly-doped source drain region Gauss doping peak concentration Cpeak=3 ×
1019cm-3, source-drain area diffusion length Ldiff=55nm, lightly-doped source drain region Gauss adulterate peak value with a distance from substrate surface
ypeak=0, take the permittivity ε of semiconductor Sis=1.036 × 10-12F/cm, Boltzmann constant k=1.381 × 10-23J/K、
Kelvin degree T=300K, electronic charge e=1.602 × 10-19C, intrinsic carrier concentration ni=1.5 × 1010cm-3；
Above-mentioned parameter is brought into the calculation formula of the peak depth H and diffusion length L of super steep doping, is obtained：
4.2) existed according to the peak concentration position and diffusion length using doping process on epitaxial layer direction
Doping 1 × 10 in active area18cm-3Boron；
4.3) HF solution is used to remove thin SiO2Layer.
Step 5 grows gate oxide.
5.1) after the completion of super steep doping, use atomic layer deposition processes on the active area with O2With SiH4It forms sediment for reactant
Product 0.25nm thickness SiO2Layer, deposition temperature are 400 DEG C；
5.2) at a temperature of 500 DEG C, using atomic layer deposition processes in SiO2With H on layer2O and HfCl4It forms sediment for reactant
Product 3.1nm thickness HfO2, i.e., the HfO that equivalent gate oxide thickness is 0.8nm is made on epitaxial layer2And SiO2Gatestack oxide layer.
Step 6 makes polysilicon gate.
6.1) use chemical vapor deposition process under 400 DEG C of temperature condition, with SiH4It is reactant in HfO2And SiO2It is folded
The polysilicon layer of 65nm thickness is grown on gate oxide；
6.2) SiO of 4nm thickness is grown at a temperature of 1100 DEG C by dry-oxygen oxidation technique on the polysilicon layer2Buffering
Layer, in SiO2The Si of 40nm thickness is grown on buffer layer3N4Protective layer；
6.3) in Si3N4Photoresist is deposited on protective layer, and adds mask plate on a photoresist；
6.4) polysilicon gate window is made by exposure, lithographic glue, the polysilicon other than etching window forms polycrystalline
Si-gate；
6.5) the cleaning removal SiO in 175 DEG C of hot phosphoric acid liquid2Buffer layer and Si3N4Protective layer.
Step 7 makes lightly-doped source drain region.
7.1) 3nm thickness SiO is grown on polysilicon gate and active area by thermal oxidation technology at a temperature of 1250 DEG C2
Buffer separation layer；
7.2) layer photoresist is made on buffering separation layer, is etched gently by being exposed on the photoresist of grid both sides
The injection window in doped source drain region, and implantation concentration is 3 × 10 in the window18cm-3Arsenic ion, so as to not covered by grid
Active area in formed 35nm depth lightly-doped source drain region；
7.3) photoresist is washed.
Step 8 makes side wall.
8.1) Si of 30nm thickness is grown on buffering separation layer3N4Photoresist is deposited after protective layer, and is added on a photoresist
Mask plate；
8.2) heavy doping source and drain is formed on the protective layer of grid Yu grid both sides by exposure, development, etching photoresist
Window is injected in area；
8.3) remove the Si in window by reactive ion etching process3N4Protective layer, the then remaining Si in grid both sides3N4
Protective layer forms side wall；
8.4) photoresist is washed.
Step 9 makes source and drain active area.
Side wall is used to inject 3 × 10 in heavy-doped source drain region injection window as mask19cm-3Concentration arsenic ion is formed
The heavy-doped source drain region of 55nm depth.
After source-drain area is formed, the SiO of polysilicon gate and epi-layer surface is removed using HF solution for step 102Layer completes base
In the super steep doping Flouride-resistani acid phesphatase for the 65nm techniques that the super steep doping depth of this example is 54nm, super steep doping length is 20nm
NMOS field-effect tube makes.
Example 3：It is 9 × 10 to make substrate doping17cm-3, source-drain area doping concentration is 5 × 1019cm-3, source-drain area expansion
It is 60nm to dissipate length, and super steep doping concentration is 2 × 1018cm-3, super steep doping depth is 53nm, and super steep doping length is
The 65nm nMOS field-effect transistors of 27nm.
Step a, grown epitaxial layer.
Using the method for chemical vapor deposition with SiH at a temperature of 500 DEG C4Thickness is grown in P type substrate for reactant
Degree is the epitaxial layer of 1000nm；9 × 10 are adulterated by diffusion technique17cm-3The boron ion of concentration is formed in epi-layer surface
The p-type doped region of 150nm depth, to adjust channel concentration.
Step b etches isolation channel.
Grow the thin SiO of 5nm thickness on epitaxial layer by dry-oxygen oxidation technique at a temperature of 1250 DEG C2Buffer layer,
Again by chemical vapor deposition method with SiH4And N2It is reactant in SiO2The Si of 20nm thickness is grown on buffer layer3N4Protection
Layer；Then in Si3N4A layer photoresist is deposited on protective layer, is added after mask plate through exposure technology exposure photo-etching glue, etching
Si3N4The photoresist on protective layer periphery, two isolation channel windows parallel with channel direction of formation width 300nm and two with
The vertical isolation channel window of channel direction, finally cleaning removes the SiO in isolation channel window in 180 DEG C of hot phosphoric acid2Buffering
Layer and Si3N4Protective layer.
Step c fills isolation channel
Cleaning removes SiO in 185 DEG C of hot phosphoric acid liquid again after the completion of polishing2Buffer layer and Si3N4Protective layer；It reuses
Chemical vapor deposition process is at 400 DEG C with O2With SiH4Isolation oxide SiO is grown for reactant2, to fill isolation channel, and
It is chemically-mechanicapolish polished；Cleaning removes SiO in 185 DEG C of hot phosphoric acid liquid again after the completion of polishing2Buffer layer and Si3N4Protection
Layer.
Step d makes doped region.
Substrate doping N is seta=9 × 1017cm-3, lightly-doped source drain region Gauss doping peak concentration Cpeak=5 ×
1019cm-3, source-drain area diffusion length Ldiff=60nm, lightly-doped source drain region Gauss adulterate peak value with a distance from substrate surface
ypeak=0；
Obtain the permittivity ε of semiconductor Sis=1.036 × 10-12F/cm, Boltzmann constant k=1.381 × 10- 23J/K, kelvin degree T=300K, electronic charge e=1.602 × 10-19C, intrinsic carrier concentration ni=1.5 ×
1010cm-3
By the known constant parameter of the parameter of above-mentioned design and acquisition be brought into it is following it is super it is steep fall the peak depth H that adulterates with
In the calculation formula of diffusion length L, obtain：
Used down on epitaxial layer direction doping process in active area according to peak concentration depth for 52nm and
Diffusion length is that 60nm adulterates 2 × 1018cm-3Boron；It reuses HF solution and removes thin SiO2Layer.
Step e grows gate oxide.
After the completion of super steep doping, first use atomic layer deposition processes on the active area with O at a temperature of 450 DEG C2With
SiH40.3nm thickness SiO is deposited for reactant2Layer；Use atomic layer deposition processes in SiO at a temperature of 500 DEG C again2On layer
With H2O and HfCl43.4nm thickness HfO is deposited for reactant2, i.e., it is 0.9nm that equivalent gate oxide thickness is made on epitaxial layer
HfO2And SiO2Gatestack oxide layer.
Step f makes polysilicon gate.
With chemical vapor deposition process with SiH at a temperature of 600 DEG C4It is reactant in HfO2And SiO2Gatestack oxide layer
The polysilicon layer of upper growth 80nm thickness；It is grown at a temperature of 1175 DEG C by dry-oxygen oxidation technique on the polysilicon layer again
The SiO of 3nm thickness2Buffer layer, in SiO2The Si of 20nm thickness is grown on buffer layer3N4Protective layer；Then in Si3N4On protective layer
Photoresist is deposited, is added after mask plate and polysilicon gate window, the polycrystalline other than etching window is made by exposure, lithographic glue
Silicon forms polysilicon gate；The finally cleaning removal SiO in 185 DEG C of hot phosphoric acid liquid2Buffer layer and Si3N4Protective layer；
Step g makes lightly-doped source drain region.
5nm thickness SiO is grown on polysilicon gate and active area by thermal oxidation technology at a temperature of 1100 DEG C2Buffering
Separation layer；A layer photoresist is made on buffering separation layer again, is gently mixed by being exposed on to etch on the photoresist of grid both sides
The injection window of miscellaneous source-drain area, and implantation concentration is 5 × 10 in the window18cm-3Arsenic ion so that not by grid covering
The lightly-doped source drain region of 40nm depth is formed in active area；Finally wash photoresist.
Step h makes side wall.
The Si of 40nm thickness is grown on buffering separation layer3N4Photoresist is deposited after protective layer and mask plate is added；Addition is covered
The injection of heavy-doped source drain region is formed on the protective layer of grid Yu grid both sides by exposure, development, etching photoresist after film version
Window, then remove by reactive ion etching process the Si in window3N4Protective layer makes the remaining Si in grid both sides3N4Protective layer
Side wall is formed, and washes photoresist
Step i makes source and drain active area.
Side wall is used to inject 1 × 10 in heavy-doped source drain region injection window as mask19It is deep to form 50nm for concentration arsenic ion
The heavy-doped source drain region of degree.
After source-drain area is formed, the SiO of polysilicon gate and epi-layer surface is removed using HF solution by step g2Layer completes base
In the super steep doping Flouride-resistani acid phesphatase for the 65nm techniques that the super steep doping depth of this example is 53nm, super steep doping length is 27nm
NMOS field-effect tube makes.
The effect of the present invention can be further illustrated by following emulation：
One, simulated conditions：
First group of parameter：Oxide trap maximum concentration is 5 × 1018cm-3, irradiation dose 0,100krad, 200krad,
300krad、400krad、600krad；
Second group of parameter：Oxide trap maximum concentration is 5 × 1017cm-3, irradiation dose 0,100krad, 200krad,
300krad、400krad、600krad；
Third group parameter：Channel dopant concentration is 9 × 1017cm-3, 5 × 1017cm-3, 2 × 1017cm-3, irradiation dose 0,
100krad、200krad、300krad、400krad、600krad、1Mrad。
The threedimensional model of nMOS FET devices of the present invention and routine nMOS FET devices passes through
The device description instrument DEVICES of ISE-TCAD softwares is generated, and emulated physics environment is arranged by device simulation tool DESSIS.
NMOS FET devices of the present invention and routine are generated by ISE-TCAD software description tools DEVICES
NMOS FET devices.
Two, emulation contents：
Emulation 1
Using the electrical characteristics of device and conventional device that first group of parameters simulation present example 2 makes, as a result such as Fig. 4,
Wherein Fig. 4 (a) is the variation diagram that device of the present invention accumulates leakage current with conventional device with accumulated dose；Fig. 4 (b) is conventional device
Transfer characteristic curve figure；Fig. 4 (c) is the transfer characteristic curve for the device that present example 2 makes.
It can be seen that conventional device increases sharply with accumulated dose accumulation OFF state electric leakage, when accumulated dose is accumulated from Fig. 4 (a)
When to 400krad, has there is apparent OFF leakage current in conventional device, when irradiation dose is 600krad, OFF leakage current
Increase to close to device operation current；And device of the present invention irradiation dose be less than 400krad when, with accumulated dose accumulate OFF state
Leakage current hardly increases, and when irradiation dose is accumulate to 600krad, the OFF leakage current of device of the present invention only rises 2
The order of magnitude, 8 orders of magnitude smaller than conventional device OFF leakage current.
It can be seen that from Fig. 4 (b), Fig. 4 (c) in the case where aoxidizing the highly concentrated severe process conditions of object space trapped charge,
No matter device of the present invention is substantially better than conventional device in terms of OFF state electric leakage, threshold voltage shift and Sub-Threshold Characteristic degeneration
Part.
Emulation 2
Using the electrical characteristics of device and conventional device that second group of parameters simulation present example 2 makes, as a result such as Fig. 5,
Wherein Fig. 5 (a) is that device of the present invention is accumulated with conventional device with accumulated dose, the growth trend of leakage current；Wherein Fig. 5 (b) is
The transfer characteristic curve of conventional device；Wherein Fig. 5 (c) is the transfer characteristic curve for the device that present example 2 makes.
It can be seen that conventional device is accumulated with accumulated dose from Fig. 5 (a), leakage current increases sharply, when accumulated dose is tired
When product is to 600krad, has there is apparent OFF leakage current in conventional device；And device of the present invention is in 400krad irradiation doses
Following OFF state electric leakage hardly increases, and in 600krad irradiation doses, the OFF state electric leakage of device of the present invention is smaller than conventional device by 7
A order of magnitude.
From in Fig. 5 (b), Fig. 5 (c) as can be seen that under the low excellent process conditions of oxidation object space trapped charge concentration,
No matter device of the present invention is substantially better than conventional device in terms of OFF state electric leakage, threshold voltage shift and Sub-Threshold Characteristic degeneration
Part.
Emulation 3
Utilize the device for the different channel dopant concentrations that third group parameters simulation present example 1, example 2, example 3 make
Part obtains the curve that the OFF leakage current of device changes with accumulated dose, as a result such as Fig. 6.
From fig. 6 it can be seen that present example 1, example 2, example 3 make different channel dopant concentrations device with
The accumulation of irradiation dose, OFF state electric leakage all increases slow, the radiation-resisting performance shown.
Above description is only three specific examples of the present invention, does not constitute any limitation of the invention.Obviously for this
It, all may be without departing substantially from the principle of the present invention, structure after understand the content of present invention and principle for the professional in field
In the case of, various modifications and variations in form and details are carried out, but these modifications and variations based on invention thought still exist
Within the claims of the present invention.
Claims (4)
1. a kind of super steep method for adulterating Flouride-resistani acid phesphatase metal-oxide-semiconductor field effect transistor prepared based on 65nm techniques, comprises the following processes：
1) doped epitaxial layer
Using the method for chemical vapor deposition with SiH at a temperature of 500-650 DEG C4It is that reactant is brilliant in p-type Si substrates (100)
Grow up the epitaxial layer that thickness is 600-1000nm, then to epitaxial layer carry out depth be 100-200nm, it is a concentration of 2 ×
1017cm-3To 9 × 1017cm-3Doping；
2) isolation channel window is etched on the epitaxial layer of doping
Grow the thin SiO of 3-6nm thickness successively by dry-oxygen oxidation technique on epitaxial layer2Buffer layer and 20-25nm thickness
Si3N4Protective layer；Again in Si3N4A layer photoresist is deposited on protective layer, and mask plate post-exposure etching photoresist is added to make width
The isolation channel window of 200-400nm, then the SiO in 175-185 DEG C of hot phosphoric acid in removal isolation channel window2Buffer layer with
Si3N4Protective layer；
3) isolation channel is filled, super steep doped region is made
The oxide S iO of deposit is filled in isolation channel window after cleaning2, and polish；Again at a temperature of 1100-1200 DEG C
The thin SiO of 4-6nm thickness is grown on epitaxial layer, that is, active area other than isolation channel by dry-oxygen oxidation technique2Layer calculates thin
SiO2The peak concentration position H and diffusion length L of super steep doping in the lower active area of layer, then use doping process according to the peak
Value concentration position H and diffusion length L adulterate 6 × 10 in active area17cm-3To 2 × 1018cm-3Boron, and gone using HF solution
Except thin SiO2Layer；
4) gate oxide and polysilicon gate are deposited
Deposit the HfO that equivalent gate oxide thickness is 0.7-0.9nm successively on epitaxial layer2And SiO2Gatestack oxide layer and 50-
The polysilicon layer of 80nm thickness, then photoresist is deposited, it is added after mask plate and polysilicon gate window is made by exposure, lithographic glue
Mouthful, the polysilicon other than etching window forms polysilicon gate；
5) lightly-doped source drain region and heavy-doped source drain region are made
3-5nm thickness SiO is grown on polysilicon gate and active area by thermal oxidation technology at a temperature of 1100-1250 DEG C2It is slow
Separation layer is rushed, then a layer photoresist is made on buffering separation layer, is etched gently by being exposed on the photoresist of grid both sides
The injection window in doped source drain region, and implantation concentration is 1 × 10 in the window18-5×1018cm-3Arsenic ion so that not by
The lightly-doped source drain region of 30-40nm depth is formed in the active area of grid covering, then washes photoresist；
The Si of 20-25nm thickness is grown on buffering separation layer3N4Protective layer, then photoresist is deposited, pass through exposure after mask plate is added
Light, development, etching photoresist form heavy-doped source drain region injection window on the protective layer of grid Yu grid both sides, pass through reaction
Ion etch process removes the Si in window3N4Protective layer, the then remaining Si in grid both sides3N4Protective layer forms side wall, then cleans
Fall photoresist；
Side wall is used to inject 1 × 10 in heavy-doped source drain region injection window as mask19-5×1019cm-3Concentration arsenic ion, shape
At the heavy-doped source drain region of 50-60nm depth；
6) after heavy-doped source drain region is formed, the SiO of polysilicon gate and epi-layer surface is removed using HF solution2Layer, completes to be based on
The super steep making for adulterating Flouride-resistani acid phesphatase nMOS field-effect tube of 65nm techniques；
3) the middle thin SiO of calculating2The peak depth H and diffusion length L of super steep doping in the lower active area of layer, by as follows
Formula calculates：
Wherein εsFor the dielectric constant of semiconductor Si, k is Boltzmann constant, and T is kelvin degree, and e is electronic charge, ni
For intrinsic carrier concentration, NaFor substrate doping, CpeakFor the peak concentration of lightly-doped source drain region Gauss doping, ypeakFor
Lightly-doped source drain region Gauss adulterates peak value with a distance from substrate surface, LdiffFor the diffusion length of source-drain area.
2. according to the method described in claim 1, wherein filling the oxidation of deposit in the isolation channel window of step 3) after cleaning
Object SiO2, using chemical vapor deposition method, process conditions are：Reactant is O2With SiH4；Temperature is 400-450 DEG C.
3. according to the method described in claim 1, wherein depositing HfO on epitaxial layer in step 4)2And SiO2Gatestack oxidation
Layer, using atomic layer deposition processes：
Deposit SiO2Process conditions are：Reactant is O2With SiH4, temperature is 400-450 DEG C；
Deposit HfO2Process conditions be：Reactant is H2O and HfCl4, temperature is 500-600 DEG C.
4. according to the method described in claim 1, wherein in step 4) in gatestack oxide layer depositing polysilicon layer, using chemistry
Vapor deposition process, process conditions are：Reactant is SiH4, temperature be 400-500 DEG C.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6426279B1 (en) * | 1999-08-18 | 2002-07-30 | Advanced Micro Devices, Inc. | Epitaxial delta doping for retrograde channel profile |
| CN102194869A (en) * | 2010-03-16 | 2011-09-21 | 北京大学 | Ultra-steep reverse doped metal oxide semiconductor (MOS) device with improved anti-irradiation property |
| CN103367128A (en) * | 2012-03-29 | 2013-10-23 | 中国科学院微电子研究所 | Method for forming ultra-steep inverted doped channel, semiconductor device and manufacturing method thereof |
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| US6426279B1 (en) * | 1999-08-18 | 2002-07-30 | Advanced Micro Devices, Inc. | Epitaxial delta doping for retrograde channel profile |
| CN102194869A (en) * | 2010-03-16 | 2011-09-21 | 北京大学 | Ultra-steep reverse doped metal oxide semiconductor (MOS) device with improved anti-irradiation property |
| CN103367128A (en) * | 2012-03-29 | 2013-10-23 | 中国科学院微电子研究所 | Method for forming ultra-steep inverted doped channel, semiconductor device and manufacturing method thereof |
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