CN105514169B - Super steep doping Flouride-resistani acid phesphatase metal-oxide-semiconductor field effect transistor based on 65nm techniques - Google Patents

Abstract

The invention discloses an ultra-steep reverse-doped anti-irradiation MOS field effect transistor based on a 65nm process, which mainly solves the problems of increased off-state leakage current, threshold voltage drift and The problem of subthreshold swing degradation. It comprises a P-type substrate (1), an epitaxial layer (2) located on the substrate, isolation grooves (3) are arranged around the top of the epitaxial layer, and a gate (4) is provided in the upper middle of the epitaxial layer. A source region (5) and a drain region (6) are arranged in the epitaxial layer between the boundary on both sides and the inner boundary of the isolation groove, and lightly doped source and drain regions (7) are arranged in the epitaxial layer below the boundary on both sides of the gate, The region directly below the gate between the two lightly doped source and drain regions forms a channel, and a heavily doped ultra-steep retrograde region (8) is provided under the channel between the two lightly doped source and drain regions . The invention improves the anti-total dose radiation ability of the device and can be used in the preparation of large-scale integrated circuits.

Description

Ultra-steep inverted doping anti-irradiation MOS field effect transistor based on 65nm process

technical field

The invention belongs to the technical field of semiconductor devices, in particular to a MOS field effect transistor, which can be used in the preparation of large-scale integrated circuits.

Background technique

MOS field effect transistors are one of the basic components of integrated circuits. They have the advantages of low power consumption, high speed, and high integration, and are widely used in military and aerospace fields. The total radiation dose in the life of a spacecraft can reach hundreds of thousands of rads. Therefore, the research on the radiation effect of the total dose is very important. The total dose radiation effect is due to the electron-hole pairs generated by radiation ionization to generate trap positive charges in the oxide layer and interface trap charges at the oxide layer silicon substrate interface. Under long-term irradiation, the accumulated trap charges reach a certain concentration and lead to an off state. Variations in leakage currents, changes in current-voltage characteristics, total dose irradiation effects due to noise margins and variations in propagation delays can also lead to functional failures.

With the reduction of device feature size, when the integrated circuit enters the deep submicron field, the total dose radiation effect of MOS field effect transistors shows some new characteristics: the gate oxide layer is getting thinner and thinner, due to the size of the gate oxide layer itself and tunneling current, the gate oxide layer has little effect on the radiation characteristics of MOS field effect transistors. However, the thickness of the shallow trench isolation STI oxide layer is about two orders of magnitude higher than that of the gate oxide layer. The ability of the oxide layer to accumulate fixed positive charges generated by irradiation is closely related to the thickness of the oxide layer. The larger the thickness, the more the accumulated fixed positive charges , so the thick STI region is the most severely affected region of the MOS field effect transistor under long-term irradiation.

CMOS circuits are widely used in integrated circuits due to their low power consumption. CMOS circuits are composed of pMOS field effect transistors as pull-up networks and nMOS field effect transistors as pull-down networks. A pMOS field effect transistor is a MOS field effect transistor with an n-type substrate, a p-type channel doping, and holes as carriers for conduction, and an nMOS field effect transistor is a p-type substrate, an n-type channel doping, and is conducted by electrons. MOS Field Effect Transistors that conduct as carriers. In CMOS circuits under the 65nm process, pMOS field effect transistors have good radiation resistance characteristics, but nMOS field effect transistors have poor radiation resistance characteristics. The thin gate oxide layer has almost no effect on the total dose irradiation characteristics of nMOS FETs. As shown in Figure 1, the trap charges generated in the sidewalls of the STI region in contact with the substrate will be generated in the nMOS FETs. Leakage channels are generated in the substrate, which leads to the reduction of threshold voltage, increase of off-state leakage current and degradation of subthreshold characteristics of nMOS field effect transistors. Studies have shown that low-density currents are formed on the surface of the substrate near the STI sidewalls under low irradiation doses, and high-density currents are formed in the leakage channels deep in the substrate near the STI sidewalls under high irradiation doses, while nMOS field effect transistors are irradiated The severe deterioration of the characteristics is mainly caused by leakage current deep in the substrate.

Contents of the invention

The purpose of the present invention is to address the above-mentioned deficiencies of the existing 65nm MOS field effect transistors, and propose an ultra-steep inverted doped anti-irradiation MOS field effect transistor based on a 65nm process, which can reduce the leakage in the deep substrate caused by irradiation, and improve Device reliability in irradiated environments.

In order to achieve the above object, the ultra-steep retrograde doped anti-radiation MOS field effect transistor of the present invention comprises a P-type substrate 1, and an epitaxial layer 2, the top of the epitaxial layer is surrounded by isolation grooves 3, and the upper middle of the epitaxial layer is a gate Pole 4, source region 5 and drain region 6 in the epitaxial layer between the boundary on both sides of the gate and the inner boundary of the isolation groove, lightly doped source and drain regions 7 in the epitaxial layer below the boundary on both sides of the gate, and the positive electrode of the gate The region below between the two lightly doped source and drain regions forms a channel, which is characterized in that: the channel between the two lightly doped source and drain regions is provided with a doping concentration of 6×10 ¹⁷ cm ^-3 to 2×10 ¹⁸ cm ^-3 heavily doped ultra-steep retrograde doping region 8 to achieve radiation resistance strengthening.

In order to achieve the above object, the present invention prepares the method for ultra-steep inverted doped anti-irradiation MOS field effect transistor based on 65nm process, including the following process:

1) Doped epitaxial layer

Use chemical vapor deposition method to grow an epitaxial layer with a thickness of 600-1000nm in the (100) crystal direction of a P-type Si substrate at a temperature of 500-650°C with _SiH4 as a reactant, and then carry out a depth of 100 nm on the epitaxial layer. -200nm doping with a concentration of 2×10 ¹⁷ cm ^-3 to 9×10 ¹⁷ cm ^-3 ;

2) Etching the isolation trench window on the doped epitaxial layer

On the epitaxial layer, grow a thin SiO ₂ buffer layer with a thickness of 3-6nm and a protective layer of Si ₃ N ₄ with a thickness of 20-25nm in sequence by dry oxygen oxidation process; then deposit a layer of photoresist on the protective layer of Si ₃ N ₄ After adding a mask, expose and etch the photoresist to make an isolation slot window with a width of 200-400nm, and then remove the SiO ₂ buffer layer and Si ₃ N ₄ protective layer in the isolation slot window in hot phosphoric acid at 175-185°C;

3) Fill the isolation groove and make an ultra-steep doped region

Fill the deposited oxide SiO ₂ in the cleaned isolation trench window, and polish; then grow 4-6nm on the epitaxial layer outside the isolation trench, that is, the active region, by dry oxygen oxidation process at a temperature of 1100-1200°C thick thin _SiO2 layer, calculate the peak concentration position and diffusion length of the ultra-steep inversion doping in the active region under the thin _SiO2 layer, and then use the inversion doping process in the active region according to the peak concentration position and diffusion length Doping 6×10 ¹⁷ cm ^-3 to 2×10 ¹⁸ cm ^-3 boron, and using HF solution to remove the thin SiO ₂ layer;

4) Deposit gate oxide layer and polysilicon gate

On the epitaxial layer, sequentially deposit the stacked gate oxide layer of HfO ₂ and SiO ₂ with an equivalent gate oxide thickness of 0.7-0.9nm and a polysilicon layer with a thickness of 50-80nm, then deposit photoresist, and add the mask plate Make a polysilicon gate window by exposing and developing photoresist, and etch the polysilicon outside the window to form a polysilicon gate;

5) Make lightly doped source and drain regions and heavily doped source and drain regions

At a temperature of 1100-1250°C, a 3-5nm thick SiO ₂ buffer isolation layer is grown on the polysilicon gate and the active region through a thermal oxidation process, and then a layer of photoresist is made on the buffer isolation layer, which is exposed on the gate The lightly doped source and drain region implantation window is etched on the photoresist on both sides, and arsenic ions with a concentration of 1×10 ¹⁸ -5×10 ¹⁸ cm ^-3 are implanted in the window so that it is not covered by the gate Form a lightly doped source and drain region with a depth of 30-40nm in the active region, and then wash off the photoresist;

Grow a 20-25nm thick Si ₃ N ₄ protective layer on the buffer isolation layer, then deposit a photoresist, add a mask plate, and then protect the gate and both sides of the gate by exposing, developing, and etching the photoresist The heavily doped source and drain region implantation window is formed on the gate layer, and the Si ₃ N ₄ protective layer in the window is removed by reactive ion etching process, and the remaining Si ₃ N ₄ protective layer on both sides of the gate forms sidewalls, and then the light is washed away. Engraving;

Use the sidewall as a mask to implant arsenic ions with a concentration of 1×10 ¹⁹ -5×10 ¹⁹ cm ^-3 in the implantation window of the heavily doped source and drain region to form a heavily doped source and drain region with a depth of 50-60nm;

6) After the heavily doped source and drain regions are formed, use HF solution to remove the _SiO2 layer on the surface of the polysilicon gate and the epitaxial layer, and complete the fabrication of the ultra-steep inverted doped radiation-resistant nMOS field effect transistor based on the 65nm process.

The present invention has the following advantages:

1. The present invention improves the anti-radiation performance because a heavily doped ultra-steep doped region is provided under the channel between two lightly doped source and drain regions.

2. Compared with the traditional 65nm nMOS process, the present invention only adds a substrate doping process, the process complexity is low, the cost increase is small, and the area is not increased, and the integrated circuit is not affected. Integration.

3. The present invention increases the doping concentration in the depth of the substrate through the ultra-steep inversion doping process, so that the depth of the substrate near the side wall of the shallow trench isolation STI is not easy to be inverted under the action of irradiation, and the substrate under high irradiation dose is weakened. The radiation characteristics of the device are seriously deteriorated due to deep leakage. Therefore, after irradiation, the off-state leakage current of the device is reduced, the negative drift of the threshold voltage is reduced, and the subthreshold degradation is reduced, which enhances the device's resistance to total dose irradiation. Ability.

4. The present invention proposes a method for determining the start position and end position of super-steep inversion doping, and the starting point of super-steep inversion doping is selected as the space charge region when the Fermi energy level of the semiconductor surface coincides with the intrinsic Fermi energy level The position not only improves the anti-radiation characteristics, but also has good working characteristics.

The simulation results show that the present invention has a strong ability to resist total dose irradiation, and under the same total dose irradiation condition, the off-state leakage current of the ultra-steep retrograde doped device is significantly lower than that of ordinary MOS devices; when the irradiation dose is less than 200krad , the off-state leakage current hardly increased. Under the irradiation dose of 400krad, the leakage current of the device was only about 10 ¹⁰ cm ^-3 , which was about 5 orders of magnitude lower than that of ordinary doped devices, showing very good anti-total Dose radiation properties.

Description of drawings

Figure 1 is a schematic diagram of radiation generating parasitic channels in nMOS field effect transistors;

Fig. 2 is a schematic diagram of the structure of the ultra-steep backward doped 65nm nMOS field effect transistor of the present invention;

Fig. 3 is the process flow chart of the present invention to prepare ultra-steep backward doped 65nm nMOS field effect transistor;

Fig. 4 is a simulation diagram of the electrical characteristics of the 65nm nMOS field effect transistor of the present invention and the conventional 65nm nMOS field effect transistor under various irradiation doses under the condition of high oxide trap concentration;

Fig. 5 is a simulation diagram of the electrical characteristics of the 65nm nMOS field effect transistor of the present invention and the conventional 65nm nMOS field effect transistor under various irradiation doses under the condition of low oxide trap concentration;

Fig. 6 is a simulation diagram of electrical characteristics of a 65nm nMOS field effect transistor of the present invention and a conventional 65nm nMOS field effect transistor under various irradiation doses under different channel doping concentrations.

Detailed ways

The technical solutions and effects of the present invention will be further described in detail below in conjunction with the accompanying drawings.

Referring to Fig. 2, the ultra-steep retrograde doped anti-irradiation MOS field effect transistor of the present invention includes: a P-type substrate 1, an epitaxial layer 2, a shallow trench isolation STI region 3, a gate 4, a source region 5, a drain region 6, Lightly doped source and drain regions 7 and super-steep retrograde doped regions 8 . The P-type epitaxial layer 2 is located above the substrate 1, the shallow trench isolation STI region 3 is located around the top of the epitaxial layer 2, the gate 4 is located in the upper middle of the epitaxial layer 2, and the borders on both sides of the gate 4 are in the shallow trench isolation STI region. In the epitaxial layer 2 between the boundaries are the source region 5 and the drain region 6 respectively, in the epitaxial layer 2 below the boundaries on both sides of the gate 4 are the lightly doped source and drain regions 7, and the ultra-steep retrograde doping region 8 is located between the two lightly doped Under the doped source and drain regions 7 , the region between the two lightly doped source and drain regions 7 and directly under the gate 4 forms a channel. The doping concentration of the ultra-steep retrograde doping region 8 is 6×10 ¹⁷ cm ^-3 to 2×10 ¹⁸ cm ^-3 ; the region above the epitaxial layer 2 surrounded by the shallow trench isolation region 3 is the active region, which is parallel to the epitaxial The length and width of the ultra-steep retrograde doping region 8 in the layer direction are the length and width of the active region not covered by the source and drain regions, and the depth of the super-steep retrograde doping region 8 in the direction perpendicular to the epitaxial layer is defined by the active region The peak depth H and diffusion length L of inner ultra-steep doping determine:

where ε _s is the dielectric constant of the semiconductor Si, k is the Boltzmann constant, T is the Kelvin temperature, e is the electronic charge, n _i is the intrinsic carrier concentration, _Na is the substrate doping concentration, C _peak is the peak concentration of Gaussian doping in the lightly doped source and drain region, y _peak is the distance between the Gaussian doping peak of the lightly doped source and drain region and the substrate surface, and L _diff is the diffusion length of the source and drain region.

The working principle of the device of the present invention is similar to that of a conventional MOS device, but due to the existence of two lightly doped source and drain regions, the depth of the substrate near the shallow trench isolation STI sidewall is not easy to invert under the action of irradiation, weakening the Under high radiation dose, the device radiation characteristics are deteriorated due to the deep substrate leakage near the shallow trench isolation STI sidewall, thus enhancing the device's ability to resist total dose radiation. There is a distance between the ultra-steep retrograde doping region and the channel region on the surface of the epitaxial layer, which has little influence on the mobility of carriers and the threshold voltage of the device, and has little influence on the working characteristics of the device.

With reference to Fig. 3, the preparation of device of the present invention provides following three kinds of embodiments:

Example 1: The doping concentration of the substrate is 2×10 ¹⁷ cm ^-3 , the doping concentration of the source and drain regions is 1×10 ¹⁹ cm ^-3 , the diffusion length of the source and drain regions is 50nm, and the super-steep retrograde doping concentration is 6× 10 ¹⁷ cm ^-3 , a 65nm nMOS field effect transistor with a super-steep retrodoping depth of 58nm and a super-steep retrodoping length of 5nm.

Step 1, growing an epitaxial layer.

First use the chemical vapor deposition method to grow an epitaxial layer with a thickness of 600nm in the crystal direction of the P-type Si substrate (100) at a temperature of 650°C with _SiH4 as the reactant;

Boron ions at a concentration of 2×10 ¹⁷ cm ^-3 are then doped through a diffusion process to form a p-type doped region with a depth of 100 nm on the surface of the epitaxial layer to adjust the channel concentration.

Step 2, etching the isolation groove.

First grow a thin _SiO2 buffer layer with a thickness of 3nm on the epitaxial layer by a dry oxygen oxidation process at a temperature of 1200°C, and then grow a 25nm SiO2 buffer layer on the _SiO2 buffer layer by a chemical vapor deposition process using _SiH4 and _N2 as reactants thick Si ₃ N ₄ protective layer;

Then deposit a layer of photoresist on the Si ₃ N ₄ protective layer, add a mask and expose the photoresist through the exposure process, etch the photoresist around the Si ₃ N ₄ protective layer to form two 400nm-width The isolation trench windows parallel to the channel direction and the two isolation trench windows perpendicular to the channel direction are finally cleaned in hot phosphoric acid at 185°C to remove the SiO ₂ buffer layer and Si ₃ N ₄ protective layer in the isolation trench windows.

Step 3, filling the isolation tank

After cleaning with phosphoric acid, use a chemical vapor deposition process to grow isolation oxide SiO ₂ at 600°C with O ₂ and SiH ₄ as reactants to fill the isolation groove, and perform chemical mechanical polishing;

After the polishing is completed, the SiO ₂ buffer layer and the Si ₃ N ₄ protective layer are cleaned and removed in a hot phosphoric acid solution at 175°C.

Step 4, making the doped region.

After phosphoric acid cleaning, a thin _SiO2 layer with a thickness of 4nm was grown on the epitaxial layer not covered by the shallow trench isolation STI region, that is, the active region, by dry oxygen oxidation process at a _temperature of 1100 °C, and then calculated the The peak concentration position H and diffusion length L of ultra-steep retrodoping in the source region:

Process parameters: substrate doping concentration _Na = 2×10 ¹⁷ cm ^-3 , lightly doped source and drain region Gaussian doping peak concentration C _peak = 1×10 ¹⁸ cm ^-3 , source and drain region diffusion length L _diff = 50nm, the distance between the lightly doped source-drain region Gaussian doping peak and the substrate surface ypeak = 0, and constant parameters: dielectric constant ε _s of semiconductor Si = 1.036×10 ^-12 F/cm, Boltzmann constant k=1.381×10 ^-23 J/K, Kelvin temperature T=300K, electronic charge e=1.602×10 ^-19 C, intrinsic carrier concentration ni=1.5×10 ¹⁰ cm ^-3 brought into the ultra-steep inverted In the calculation formula of doping peak depth H and diffusion length L, get:

Then doping 6×10 ¹⁷ cm ^-3 of boron in the active region according to the peak concentration position and diffusion length in the direction perpendicular to the epitaxial layer;

Finally the thin _SiO2 layer was removed using HF solution.

Step 5, growing a gate oxide layer.

After the ultra-steep inversion doping is completed, a SiO ₂ layer with a thickness of 0.2nm is deposited on the active region by using an atomic layer deposition process at a temperature of 425°C with O ₂ and SiH ₄ as reactants;

Then at a temperature of 600°C, HfO ₂ with a thickness of 2.8nm was deposited on the SiO ₂ layer by using atomic layer deposition technology with H ₂ O and HfCl ₄ as reactants, that is, the thickness of the equivalent gate oxide layer on the epitaxial layer was 0.7nm HfO ₂ and SiO ₂ stacked gate oxide.

Step 6, making a polysilicon gate.

A polysilicon layer with a thickness of 50nm is grown on the HfO ₂ and SiO ₂ stack gate oxide layer at a temperature of 500°C with SiH ₄ as a reactant by chemical vapor deposition;

Next, grow a _SiO2 buffer layer with a thickness of 5nm at a temperature of 1250°C on the polysilicon layer through a dry oxygen oxidation process, and grow a _Si3N4 protective layer with a thickness of _30nm on the _SiO2 buffer layer;

Next, deposit a photoresist on the Si ₃ N ₄ protective layer, add a mask and make a polysilicon gate window by exposing and developing the photoresist, and etch the polysilicon outside the window to form a polysilicon gate;

Next, the SiO ₂ buffer layer and the Si ₃ N ₄ protective layer are removed by washing in a hot phosphoric acid solution at 180°C.

Step 7, making lightly doped source and drain regions.

A 4nm-thick SiO ₂ buffer isolation layer is grown on the polysilicon gate and the active region through a thermal oxidation process at a temperature of 1175°C;

Then make a layer of photoresist on the buffer isolation layer, and etch the injection window of lightly doped source and drain regions by exposing the photoresist on both sides of the gate, and implant the concentration in this window to 1×10 ¹⁸ cm ^-3 of arsenic ions, so that a lightly doped source and drain region with a depth of 30nm is formed in the active region not covered by the gate;

Finally, the photoresist is cleaned off.

Step 8, making side walls.

Deposit photoresist after growing a 20nm thick Si ₃ N ₄ protective layer on the buffer isolation layer;

After adding the mask plate, the heavily doped source and drain region injection windows are formed on the gate and the protective layer on both sides of the gate by exposing, developing, and etching the photoresist;

The Si ₃ N ₄ protective layer in the window is removed by a reactive ion etching process, and the remaining Si ₃ N ₄ protective layer on both sides of the gate forms sidewalls, and then the photoresist is washed away.

Step 9, making source and drain active regions.

Use the sidewall as a mask to implant arsenic ions with a concentration of 1×10 ¹⁹ into the implantation window of the heavily doped source and drain region to form a heavily doped source and drain region with a depth of 50nm.

Step 10, after the source and drain regions are formed, use HF solution to remove the _SiO2 layer on the surface of the polysilicon gate and the epitaxial layer, and complete the ultra-steep retrodoping based on the 65nm process with a super-steep retrodoping depth of 58nm and a super-steep retrodoping length of 5nm. Fabrication of Steep Reverse Doped Radiation Resistant nMOS Field Effect Transistor.

Example 2: The doping concentration of the substrate is 5×10 ¹⁷ cm ^-3 , the doping concentration of the source and drain regions is 3×10 ¹⁹ cm ^-3 , the diffusion length of the source and drain regions is 55nm, and the diffusion length of the source and drain regions is 50nm. A 65nm nMOS field effect transistor with a steep doping concentration of 1×10 ¹⁸ cm ^-3 , a super-steep doping depth of 54nm, and a super-steep doping length of 20nm.

Step 1, growing an epitaxial layer.

1.1) Using chemical vapor deposition method to grow an epitaxial layer with a thickness of 800nm on a P-type substrate at a temperature of 600°C with _SiH4 as a reactant;

1.2) Doping boron ions with a concentration of 5×10 ¹⁷ cm ^-3 through a diffusion process to form a p-type doped region with a depth of 150 nm on the surface of the epitaxial layer to adjust the channel concentration.

Step 2, etching the isolation groove.

2.1) A thin _SiO2 buffer layer with a thickness of 6 nm was grown on the epitaxial layer by a dry oxygen oxidation process at a temperature of 1100 ° C, and then grown on the _SiO2 buffer layer by a chemical vapor deposition process using _SiH4 and _N2 as reactants 22nm thick Si ₃ N ₄ protective layer;

2.2) Deposit a layer of photoresist on the Si ₃ N ₄ protective layer, add a mask and expose the photoresist through an exposure process, etch the photoresist around the Si ₃ N ₄ protective layer to form two layers with a width of 200nm. One isolation trench window parallel to the channel direction and two isolation trench windows perpendicular to the channel direction;

2.3) Clean and remove the SiO ₂ buffer layer and Si ₃ N ₄ protective layer in the window of the isolation tank in hot phosphoric acid at 175°C.

Step 3, fill the isolation tank

3.1) After polishing, wash and remove the SiO ₂ buffer layer and Si ₃ N ₄ protective layer in hot phosphoric acid solution at 175°C;

3.2) After cleaning with phosphoric acid, use a chemical vapor deposition process to grow isolation oxide SiO ₂ at 500°C with O ₂ and SiH ₄ as reactants to fill the isolation groove, and perform chemical mechanical polishing;

3.3) After polishing, wash and remove the SiO ₂ buffer layer and Si ₃ N ₄ protective layer in hot phosphoric acid solution at 185°C.

Step 4, fabricate the doped region.

4.1) Calculate the peak concentration position H and diffusion length L of ultra-steep retrodoping in the active region under the thin _SiO2 layer:

Set substrate doping concentration _Na =5×10 ¹⁷ cm ^-3 , lightly doped source and drain region Gaussian doping peak concentration C _peak =3×10 ¹⁹ cm ^-3 , source and drain region diffusion length L _diff =55nm , The distance y _peak of the Gaussian doping peak in the lightly doped source and drain region from the substrate surface = 0, the dielectric constant ε _s of the semiconductor Si = 1.036×10 ^-12 F/cm, and the Boltzmann constant k = 1.381× 10 ^-23 J/K, Kelvin temperature T=300K, electron charge e=1.602×10 ^-19 C, intrinsic carrier concentration n _i =1.5×10 ¹⁰ cm ^-3 ;

Bringing the above parameters into the calculation formula of the peak depth H and diffusion length L of ultra-steep inversion doping, we get:

4.2) Doping 1×10 ¹⁸ cm ^-3 boron in the active region according to the peak concentration position and diffusion length in the direction perpendicular to the epitaxial layer by reverse doping process;

4.3) Use HF solution to remove the thin _SiO2 layer.

Step five, growing a gate oxide layer.

5.1) After the ultra-steep inversion doping is completed, a 0.25nm-thick SiO ₂ layer is deposited on the active region by using an atomic layer deposition process with O ₂ and SiH ₄ as reactants, and the deposition temperature is 400°C;

5.2) At a temperature of 500°C, use the atomic layer deposition process to deposit HfO ₂ with a thickness of 3.1nm on the SiO ₂ layer using H ₂ O and HfCl ₄ as reactants, that is, create an equivalent gate oxide layer thickness on the epitaxial layer 0.8nm HfO ₂ and SiO ₂ stacked gate oxide.

Step six, fabricating the polysilicon gate.

6.1) Using a chemical vapor deposition process at a temperature of 400° C., using SiH ₄ as a reactant to grow a polysilicon layer with a thickness of 65 nm on the stacked gate oxide layer of HfO ₂ and SiO ₂ ;

6.2) On the polysilicon layer, a _SiO2 buffer layer with a thickness of 4nm is grown at a temperature of 1100°C by a dry oxygen oxidation process, and a _Si3N4 protective layer with a thickness of _40nm is grown on the _SiO2 buffer layer;

6.3) Deposit photoresist on the Si ₃ N ₄ protective layer, and add a mask on the photoresist;

6.4) Make a polysilicon gate window by exposing and developing photoresist, and etch the polysilicon outside the window to form a polysilicon gate;

6.5) Wash and remove the SiO ₂ buffer layer and Si ₃ N ₄ protective layer in hot phosphoric acid solution at 175°C.

Step seven, making lightly doped source and drain regions.

7.1) A 3nm-thick SiO ₂ buffer isolation layer is grown on the polysilicon gate and the active region through a thermal oxidation process at a temperature of 1250°C;

7.2) Make a layer of photoresist on the buffer isolation layer, etch the injection window of the lightly doped source and drain region by exposing the photoresist on both sides of the gate, and implant the concentration in this window to 3×10 ¹⁸ cm ^-3 of arsenic ions, so that a lightly doped source and drain region with a depth of 35nm is formed in the active region not covered by the gate;

7.3) Wash away the photoresist.

Step eight, making side walls.

8.1) Deposit photoresist after growing a 30nm thick Si ₃ N ₄ protective layer on the buffer isolation layer, and add a mask on the photoresist;

8.2) Forming heavily doped source and drain region injection windows on the gate and the protective layer on both sides of the gate by exposing, developing, and etching the photoresist;

8.3) Removing the Si ₃ N ₄ protective layer in the window by reactive ion etching process, the remaining Si ₃ N ₄ protective layer on both sides of the gate forms sidewalls;

8.4) Wash away the photoresist.

Step 9, making source and drain active regions.

Use the sidewall as a mask to implant arsenic ions with a concentration of 3×10 ¹⁹ cm ^-3 in the implantation window of the heavily doped source and drain region to form a heavily doped source and drain region with a depth of 55nm.

Step ten, after the source and drain regions are formed, use HF solution to remove the _SiO2 layer on the surface of the polysilicon gate and the epitaxial layer, and complete the ultra-steep retrograde doping based on the 65nm process with a depth of 54nm and a length of 20nm. Fabrication of Steep Reverse Doped Radiation Resistant nMOS Field Effect Transistor.

Example 3: The doping concentration of the substrate is 9×10 ¹⁷ cm ^-3 , the doping concentration of the source and drain regions is 5×10 ¹⁹ cm ^-3 , the diffusion length of the source and drain regions is 60nm, and the super-steep retrograde doping concentration is 2× 10 ¹⁸ cm ^-3 , a 65nm nMOS field effect transistor with a super-steep retrograde doping depth of 53nm and a super-steep retrograde doping length of 27nm.

Step a, growing an epitaxial layer.

Using the chemical vapor deposition method to grow an epitaxial layer with a thickness of 1000nm on a P-type substrate at a temperature of 500°C with SiH ₄ as a reactant; doping boron ions with a concentration of 9×10 ¹⁷ cm ^-3 through a diffusion process, A p-type doped region with a depth of 150nm is formed on the surface of the epitaxial layer to adjust the channel concentration.

Step b, etching the isolation groove.

A thin SiO2 buffer layer with a thickness of 5nm was grown on the epitaxial layer by a dry oxygen oxidation process at a temperature of 1250°C, and then a 20nm thick _SiO2 buffer layer was grown on the _SiO2 buffer layer by a chemical vapor deposition process using _SiH4 and _N2 as reactants Si ₃ N ₄ protective layer; then deposit a layer of photoresist on the Si ₃ N ₄ protective layer, add a mask and expose the photoresist through the exposure process, and etch the photoresist around the Si ₃ N ₄ protective layer Glue to form two isolation trench windows parallel to the channel direction and two isolation trench windows perpendicular to the channel direction with a width of 300nm, and finally wash in hot phosphoric acid at 180°C to remove the _SiO2 buffer layer and Si ₃ N ₄ protective layer.

Step c, filling the isolation tank

After polishing, clean and remove the SiO ₂ buffer layer and Si ₃ N ₄ protective layer in a hot phosphoric acid solution at 185°C; then use a chemical vapor deposition process to grow isolation oxidation at 400°C with O ₂ and SiH ₄ as reactants. SiO ₂ is used to fill the isolation groove, and chemical mechanical polishing is performed; after polishing, the SiO ₂ buffer layer and Si ₃ N ₄ protective layer are removed by cleaning in hot phosphoric acid solution at 185°C.

Step d, fabricate the doped region.

Set substrate doping concentration _Na = 9×10 ¹⁷ cm ^-3 , lightly doped source and drain region Gaussian doping peak concentration C _peak = 5×10 ¹⁹ cm ^-3 , source and drain region diffusion length L _diff =60nm , the distance y _{peak of} the Gaussian doping peak of the lightly doped source and drain region from the substrate surface =0;

Obtain the dielectric constant ε _s of semiconductor Si = 1.036×10 ^-12 F/cm, Boltzmann's constant k = 1.381×10 ^{- 23} J/K, Kelvin temperature T = 300K, electron charge e = 1.602×10 ^{- 19} C, intrinsic carrier concentration n _i =1.5×10 ¹⁰ cm ^-3

Putting the above-mentioned designed parameters and the obtained known constant parameters into the following calculation formulas of the peak depth H and diffusion length L of ultra-steep inversion doping, we can get:

In the direction perpendicular to the epitaxial layer, the reverse doping process is used to dope 2×10 ¹⁸ cm ^-3 boron in the active region according to the peak concentration depth of 52nm and the diffusion length of 60nm; then use HF solution to remove the thin SiO ₂ layer.

Step e, growing a gate oxide layer.

After the ultra-steep inversion doping is completed, first use the atomic layer deposition process at a temperature of 450 ° C to deposit a 0.3nm thick SiO ₂ layer on the active region with O ₂ and SiH ₄ as reactants; and then at a temperature of 500 ° C Next, use the atomic layer deposition process to deposit HfO ₂ with a thickness of 3.4nm on the SiO ₂ layer with H ₂ O and HfCl ₄ as reactants, that is, make HfO ₂ and SiO with an equivalent gate oxide layer thickness of 0.9 nm on the epitaxial layer. ₂ stack gate oxide layer.

Step f, making a polysilicon gate.

A polysilicon layer with a thickness of 80nm is grown on the HfO ₂ and SiO ₂ stacked gate oxide layer with a chemical vapor deposition process at a temperature of 600°C using SiH ₄ as a reactant; grow a 3nm-thick SiO ₂ buffer layer at a temperature of 3nm, and grow a 20nm-thick Si ₃ N ₄ protective layer on the SiO ₂ buffer layer; then deposit a photoresist on the Si ₃ N ₄ protective layer, add a mask and pass Expose and develop the photoresist to make a polysilicon gate window, etch the polysilicon outside the window to form a polysilicon gate; finally, wash and remove the SiO ₂ buffer layer and Si ₃ N ₄ protective layer in a hot phosphoric acid solution at 185°C;

Step g, making lightly doped source and drain regions.

At a temperature of 1100°C, a 5nm-thick SiO ₂ buffer isolation layer is grown on the polysilicon gate and the active region through a thermal oxidation process; The implantation window of the lightly doped source and drain regions is etched on the resist, and arsenic ions with a concentration of 5×10 ¹⁸ cm ^-3 are implanted in the window, so that a 40nm deep Lightly doped source and drain regions; finally wash off the photoresist.

Step h, making side walls.

After growing a 40nm-thick Si ₃ N ₄ protective layer on the buffer isolation layer, deposit photoresist and add a mask; after adding the mask, expose, develop, and etch the photoresist on both sides of the gate and the gate The heavily doped source and drain region implantation window is formed on the protective layer of the gate, and then the Si ₃ N ₄ protective layer in the window is removed by reactive ion etching process, so that the remaining Si ₃ N ₄ protective layer on both sides of the gate forms side walls, and wash off photoresist

Step i, making source and drain active regions.

Use the sidewall as a mask to implant arsenic ions with a concentration of 1×10 ¹⁹ into the implantation window of the heavily doped source and drain region to form a heavily doped source and drain region with a depth of 50nm.

Step g, after the source and drain regions are formed, use HF solution to remove the _SiO2 layer on the surface of the polysilicon gate and the epitaxial layer, and complete the ultra-steep retro-doping based on the 65nm process with a super-steep retro-doping depth of 53nm and a super-steep retro-doping length of 27nm in this example. Fabrication of Steep Reverse Doped Radiation Resistant nMOS Field Effect Transistor.

Effect of the present invention can be further illustrated by following simulation:

1. Simulation conditions:

The first set of parameters: the maximum concentration of oxide traps is 5×10 ¹⁸ cm ^-3 , and the irradiation dose is 0, 100krad, 200krad, 300krad, 400krad, 600krad;

The second set of parameters: the maximum concentration of oxide traps is 5×10 ¹⁷ cm ^-3 , and the irradiation dose is 0, 100krad, 200krad, 300krad, 400krad, 600krad;

The third group of parameters: the channel doping concentration is 9×10 ¹⁷ cm ^-3 , 5×10 ¹⁷ cm ^-3 , 2×10 ¹⁷ cm ^-3 , the irradiation dose is 0, 100krad, 200krad, 300krad, 400krad, 600krad, 1 Mrad.

The three-dimensional models of the nMOS field effect transistor device of the present invention and the conventional nMOS field effect transistor device are generated by the device description tool DEVICES of the ISE-TCAD software, and the simulation physical environment is set by the device simulation tool DESSIS.

The nMOS field effect transistor device of the present invention and the conventional nMOS field effect transistor device are generated by the ISE-TCAD software description tool DEVICES.

2. Simulation content:

Simulation 1

Utilize the first group of parameters to simulate the electrical characteristics of the device and the conventional device made by the example of the present invention 2, the result is as shown in Figure 4, wherein Fig. 4 (a) is the change figure of the device of the present invention and the conventional device with the cumulative leakage current of the total dose; Fig. 4 (b) is a transfer characteristic curve of a conventional device; FIG. 4(c) is a transfer characteristic curve of a device made in Example 2 of the present invention.

It can be seen from Figure 4(a) that the off-state leakage of the conventional device increases rapidly with the cumulative total dose. When the total dose is accumulated to 400krad, the conventional device has an obvious off-state leakage current. When the irradiation dose is 600krad, The off-state leakage current increases to close to the device operating current; and the device of the present invention is less than 400krad when the radiation dose is less than 400krad. The off-state leakage current only increases by 2 orders of magnitude, which is 8 orders of magnitude smaller than the off-state leakage current of conventional devices.

It can be seen from Fig. 4(b) and Fig. 4(c) that under the harsh process conditions with high oxide space trap charge concentration, the device of the present invention is excellent in terms of off-state leakage, threshold voltage drift and subthreshold characteristic degradation. Much better than conventional devices.

Simulation 2

Utilize the second group of parameters to simulate the electrical characteristics of the device and the conventional device made by the example of the present invention 2, the result is as shown in Figure 5, wherein Figure 5 (a) is the device of the present invention and the conventional device with the total dose accumulation, the growth trend of the leakage current; wherein Fig. 5(b) is the transfer characteristic curve of the conventional device; wherein Fig. 5(c) is the transfer characteristic curve of the device made in Example 2 of the present invention.

As can be seen from Fig. 5(a), the leakage current of the conventional device increases rapidly with the total dose accumulation, and when the total dose is accumulated to 600krad, the conventional device has obvious off-state leakage current; and the device of the present invention is irradiated at 400krad The off-state leakage hardly increases below the dose, and the off-state leakage of the device of the present invention is 7 orders of magnitude smaller than that of the conventional device when the radiation dose is 600krad.

It can be seen from Fig. 5(b) and Fig. 5(c) that under the excellent process conditions of low oxide space trap charge concentration, the device of the present invention is excellent in terms of off-state leakage, threshold voltage drift and subthreshold characteristic degradation. Much better than conventional devices.

Simulation 3

Using the third set of parameters to simulate the devices with different channel doping concentrations produced in Example 1, Example 2, and Example 3 of the present invention, the curve of the off-state leakage current of the device changing with the total dose is obtained, and the result is shown in FIG. 6 .

As can be seen from Figure 6, the devices with different channel doping concentrations produced by Example 1, Example 2, and Example 3 of the present invention increase slowly with the accumulation of radiation dose, and all show good radiation resistance. According to characteristics.

The above descriptions are only three specific examples of the present invention, and do not constitute any limitation to the present invention. Obviously, for those skilled in the art, after understanding the content and principle of the present invention, it is possible to make various modifications and changes in form and details without departing from the principle and structure of the present invention, but these are based on the invention The modification and change of thought are still within the protection scope of the claims of the present invention.

Claims (4)

1. a kind of super steep method for adulterating Flouride-resistani acid phesphatase metal-oxide-semiconductor field effect transistor prepared based on 65nm techniques, comprises the following processes：

1) doped epitaxial layer

Using the method for chemical vapor deposition with SiH at a temperature of 500-650 DEG C₄It is that reactant is brilliant in p-type Si substrates (100) Grow up the epitaxial layer that thickness is 600-1000nm, then to epitaxial layer carry out depth be 100-200nm, it is a concentration of 2 × 10¹⁷cm^-3To 9 × 10¹⁷cm^-3Doping；

2) isolation channel window is etched on the epitaxial layer of doping

Grow the thin SiO of 3-6nm thickness successively by dry-oxygen oxidation technique on epitaxial layer₂Buffer layer and 20-25nm thickness Si₃N₄Protective layer；Again in Si₃N₄A layer photoresist is deposited on protective layer, and mask plate post-exposure etching photoresist is added to make width The isolation channel window of 200-400nm, then the SiO in 175-185 DEG C of hot phosphoric acid in removal isolation channel window₂Buffer layer with Si₃N₄Protective layer；

3) isolation channel is filled, super steep doped region is made

The oxide S iO of deposit is filled in isolation channel window after cleaning₂, and polish；Again at a temperature of 1100-1200 DEG C The thin SiO of 4-6nm thickness is grown on epitaxial layer, that is, active area other than isolation channel by dry-oxygen oxidation technique₂Layer calculates thin SiO₂The peak concentration position H and diffusion length L of super steep doping in the lower active area of layer, then use doping process according to the peak Value concentration position H and diffusion length L adulterate 6 × 10 in active area¹⁷cm^-3To 2 × 10¹⁸cm^-3Boron, and gone using HF solution Except thin SiO₂Layer；

4) gate oxide and polysilicon gate are deposited

Deposit the HfO that equivalent gate oxide thickness is 0.7-0.9nm successively on epitaxial layer₂And SiO₂Gatestack oxide layer and 50- The polysilicon layer of 80nm thickness, then photoresist is deposited, it is added after mask plate and polysilicon gate window is made by exposure, lithographic glue Mouthful, the polysilicon other than etching window forms polysilicon gate；

5) lightly-doped source drain region and heavy-doped source drain region are made

3-5nm thickness SiO is grown on polysilicon gate and active area by thermal oxidation technology at a temperature of 1100-1250 DEG C₂It is slow Separation layer is rushed, then a layer photoresist is made on buffering separation layer, is etched gently by being exposed on the photoresist of grid both sides The injection window in doped source drain region, and implantation concentration is 1 × 10 in the window¹⁸-5×10¹⁸cm^-3Arsenic ion so that not by The lightly-doped source drain region of 30-40nm depth is formed in the active area of grid covering, then washes photoresist；

The Si of 20-25nm thickness is grown on buffering separation layer₃N₄Protective layer, then photoresist is deposited, pass through exposure after mask plate is added Light, development, etching photoresist form heavy-doped source drain region injection window on the protective layer of grid Yu grid both sides, pass through reaction Ion etch process removes the Si in window₃N₄Protective layer, the then remaining Si in grid both sides₃N₄Protective layer forms side wall, then cleans Fall photoresist；

Side wall is used to inject 1 × 10 in heavy-doped source drain region injection window as mask¹⁹-5×10¹⁹cm^-3Concentration arsenic ion, shape At the heavy-doped source drain region of 50-60nm depth；

6) after heavy-doped source drain region is formed, the SiO of polysilicon gate and epi-layer surface is removed using HF solution₂Layer, completes to be based on The super steep making for adulterating Flouride-resistani acid phesphatase nMOS field-effect tube of 65nm techniques；

3) the middle thin SiO of calculating₂The peak depth H and diffusion length L of super steep doping in the lower active area of layer, by as follows Formula calculates：

Wherein ε_sFor the dielectric constant of semiconductor Si, k is Boltzmann constant, and T is kelvin degree, and e is electronic charge, n_i For intrinsic carrier concentration, N_aFor substrate doping, C_peakFor the peak concentration of lightly-doped source drain region Gauss doping, y_peakFor Lightly-doped source drain region Gauss adulterates peak value with a distance from substrate surface, L_diffFor the diffusion length of source-drain area.

2. according to the method described in claim 1, wherein filling the oxidation of deposit in the isolation channel window of step 3) after cleaning Object SiO₂, using chemical vapor deposition method, process conditions are：Reactant is O₂With SiH₄；Temperature is 400-450 DEG C.

3. according to the method described in claim 1, wherein depositing HfO on epitaxial layer in step 4)₂And SiO₂Gatestack oxidation Layer, using atomic layer deposition processes：

Deposit SiO₂Process conditions are：Reactant is O₂With SiH₄, temperature is 400-450 DEG C；

Deposit HfO₂Process conditions be：Reactant is H₂O and HfCl₄, temperature is 500-600 DEG C.

4. according to the method described in claim 1, wherein in step 4) in gatestack oxide layer depositing polysilicon layer, using chemistry Vapor deposition process, process conditions are：Reactant is SiH₄, temperature be 400-500 DEG C.