CN103779280B - The manufacture method of high dielectric layer metal gate device - Google Patents
The manufacture method of high dielectric layer metal gate device Download PDFInfo
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- CN103779280B CN103779280B CN201210415303.0A CN201210415303A CN103779280B CN 103779280 B CN103779280 B CN 103779280B CN 201210415303 A CN201210415303 A CN 201210415303A CN 103779280 B CN103779280 B CN 103779280B
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- 239000002184 metal Substances 0.000 title claims abstract description 30
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 30
- 238000000034 method Methods 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 30
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 claims abstract description 25
- 238000002347 injection Methods 0.000 claims abstract description 11
- 239000007924 injection Substances 0.000 claims abstract description 11
- 238000000137 annealing Methods 0.000 claims abstract description 8
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 96
- 239000011229 interlayer Substances 0.000 claims description 9
- 230000008021 deposition Effects 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 229910017052 cobalt Inorganic materials 0.000 claims description 3
- 239000010941 cobalt Substances 0.000 claims description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- VDRSDNINOSAWIV-UHFFFAOYSA-N [F].[Si] Chemical group [F].[Si] VDRSDNINOSAWIV-UHFFFAOYSA-N 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 description 9
- 230000000694 effects Effects 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- DYCJFJRCWPVDHY-LSCFUAHRSA-N NBMPR Chemical compound O[C@@H]1[C@H](O)[C@@H](CO)O[C@H]1N1C2=NC=NC(SCC=3C=CC(=CC=3)[N+]([O-])=O)=C2N=C1 DYCJFJRCWPVDHY-LSCFUAHRSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- ZHPNWZCWUUJAJC-UHFFFAOYSA-N fluorosilicon Chemical compound [Si]F ZHPNWZCWUUJAJC-UHFFFAOYSA-N 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000002776 aggregation Effects 0.000 description 1
- 238000004220 aggregation Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000000686 essence Substances 0.000 description 1
- 230000009931 harmful effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- -1 oxonium ion Chemical class 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/2822—Making the insulator with substrate doping, e.g. N, Ge, C implantation, before formation of the insulator
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a kind of manufacture method of high dielectric layer metal gate device, fluorine ion injection is performed after dummy poly and dielectric layer is removed, and first time annealing is carried out after pad oxide is formed, perform second and anneal after high dielectric layer is formed, fluorine ion is set to diffuse to cushion oxide layer and high dielectric layer by the channel region of substrate, with unstable Hydrogenbond formation fluorine silicon group, reduce fluorine ion by dummy poly diffuse into high dielectric layer during technique uncontrollability and technology difficulty.
Description
Technical field
The present invention relates to the system of field of manufacturing semiconductor devices, more particularly to a kind of high dielectric layer metal gate (HKMG) device
Make method.
Background technology
With the development of semiconductor integrated circuit, such as existing semiconductor devices, complementary metal oxide semiconductor
(CMOS) polysilicon gate generally used in device gradually manifests problems with：Because grid loss causes gate insulator to have
Thickness increase is imitated, dopant penetrates into substrate easily by polysilicon gate and causes threshold voltage to change, it is difficult to realize tiny width
Low-resistance value etc. on degree.To solve the above problems, semiconductor technology has developed substitutes existing polysilicon gate with metal gates
Semiconductor devices, and high-k (high k) material is used as the semiconductor devices of gate insulation layer, referred to as high dielectric
Layer metal gate (HKMG, high-k metal-gate) device.
High dielectric layer metal gate device has substantial amounts of interfacial state at the interface of high dielectric layer and silicon, and this is due to partly to lead
Unstable hydrogen bond can be formed in system journey, causes to produce a large amount of interfaces in nmos pass transistor and the PMOS transistor course of work
State, so as to change MOS transistor performance, is embodied in nmos pass transistor HCI (Hot Carrier Injection, hot current-carrying
Son injection) (Negative Bias Temperature Instability, back bias voltage is or not the NBTI of effect and PMOS transistor
Stability) effect.
In order to solve a large amount of interfacial states caused by unstable hydrogen bond, prior art generally by injecting fluorine ion, makes fluorine
Ion enters high dielectric layer and replaces part oxonium ion in high dielectric layer, and unstable Hydrogenbond, so as to form fluorine silicon substrate
Group, it is right this improves the interface quality between high dielectric layer and Semiconductor substrate because fluorine silicon is strong more more firm than si-h bond
For nmos pass transistor, prevention forms charge trap, prevents that aggregation electric charge in source/drain region is lightly doped under making alive, so that
The HCI effects of nmos pass transistor are substantially improved, for PMOS transistor, can prevent from generating silicon dangling bonds at high temperature,
So as to mitigate due to the influence of NBTI effect pair pmos transistors.
The content of the invention
In view of problem of the prior art, the invention provides a kind of manufacture method of high dielectric layer metal gate device, to solve
Certainly existing process realizes the problem of difficulty is high.
The technical solution adopted by the present invention is as follows：A kind of manufacture method of high dielectric layer metal gate device, including：
Being formed on substrate includes the grid structure of dielectric layer, dummy poly and sidewall oxide；
Deposition forms interlayer insulative layer on substrate, and carries out cmp to expose the dummy poly；
Etching removes dummy poly and dielectric layer, to form the groove of bottom-exposed substrate corresponding with dummy poly；
Fluorine ion injection is performed to be doped exposed substrate；
Form cushion oxide layer in the bottom portion of groove and perform and anneal for the first time；
Deposition forms high dielectric layer and performs second and anneals in the cushion oxide layer；
Metal gates are formed on the high dielectric layer.
Further, being formed on substrate includes the grid structure of dielectric layer, dummy poly and sidewall oxide and includes：
NMOS active areas and PMOS active areas are formed on substrate, and is formed between NMOS active areas and PMOS active areas
Shallow trench is isolated；Form NMOS dielectric layers and PMOS dielectric layers, and NMOS puppets respectively on NMOS active areas and PMOS active areas
Polysilicon and PMOS dummy polies, and in NMOS dielectric layers, the both sides of NMOS dummy polies and PMOS dielectric layers, the pseudo- polycrystalline of PMOS
The both sides of silicon form sidewall oxide；
Include in bottom portion of groove formation cushion oxide layer by thermal oxide or chemical oxidation in the bottom portion of groove shape
Into cushion oxide layer；
Metal gates are formed on high dielectric layer to be included：Metal work function layer is formed on high dielectric layer；In the metal
Deposited metal layer in work-function layer；Cmp is performed to expose interlayer insulative layer.
Further, after performing fluorine ion injection to be doped to exposed substrate, the concentration of fluorine ion impurity is less than
3e15atom/cm3。
Further, the first time is annealed into the Millisecond annealing of 900 degrees Celsius to 1200 degrees Celsius of temperature range；It is described
The short annealing of 600 degrees Celsius to 800 degrees Celsius of temperature range is annealed into for the second time.
Further, the material of the metal level is cobalt.
Using the manufacture method in high dielectric layer metal gate device provided by the present invention, dummy poly and dielectric are being removed
Fluorine ion injection is performed after layer, and first time annealing is carried out after pad oxide is formed, the is performed after high dielectric layer is formed
Double annealing, makes fluorine ion diffuse to cushion oxide layer and high dielectric layer by the channel region of substrate, with unstable Hydrogenbond
Form fluorine silicon group, reduce fluorine ion by dummy poly diffuse into high dielectric layer during technique uncontrollability and technique it is difficult
Degree.
Brief description of the drawings
Fig. 1 is a kind of manufacture method flow chart of high dielectric layer metal gate device of the present invention；
Fig. 2 a~Fig. 2 e are the manufacture method flowage structure schematic diagram of exemplary embodiments of the present invention.
Embodiment
The principle and feature of the present invention are described below in conjunction with accompanying drawing, the given examples are served only to explain the present invention, and
It is non-to be used to limit the scope of the present invention.
As shown in figure 1, the invention provides a kind of manufacture method of high dielectric layer metal gate device, including：
Being formed on substrate includes the grid structure of dielectric layer, dummy poly and sidewall oxide；
Deposition forms interlayer insulative layer on substrate, and carries out cmp to expose the dummy poly；
Etching removes dummy poly and dielectric layer, to form the groove of bottom-exposed substrate corresponding with dummy poly；
Fluorine ion injection is performed to be doped exposed substrate；
Form cushion oxide layer in the bottom portion of groove and perform and anneal for the first time；
Deposition forms high dielectric layer and performs second and anneals in the cushion oxide layer；
Metal gates are formed on the high dielectric layer.
As the exemplary embodiments of the present invention, below in conjunction with Fig. 2 a~the present invention will be described in detail by Fig. 2 e.
As shown in Figure 2 a, Semiconductor substrate is provided first, formation NMOS active areas and PMOS active areas on substrate, and
Shallow trench isolation 8 is formed between NMOS active areas and PMOS active areas；Formed respectively on NMOS active areas and PMOS active areas
NMOS dielectric layers 1 and PMOS dielectric layers 2, and NMOS dummy polies 6 and PMOS dummy polies 7, and in NMOS dielectric layers 1, NMOS
The both sides of dummy poly 6 and PMOS dielectric layers 2, the both sides of PMOS dummy polies 7 form sidewall oxide 4 and 5；Then in substrate
Upper deposition forms interlayer insulative layer 3, and carries out cmp to expose dummy poly 6 and 7；
Dummy poly 6,7 and dielectric layer 1,2 are removed using dry etching, it is corresponding with dummy poly to form bottom-exposed
The groove 9 and 10 of substrate；Wherein, light is formed on the surface on the surface of interlayer insulative layer 3, dummy poly 6 and 7 before dry etching
Photoresist (not shown), patterning photoresist carries out dry method to expose dummy poly 6 and 7 with the photoresist (not shown) of patterning
Etching；When carrying out dry etching, first using dielectric layer 1 and 2 as etching barrier layer, etching removes dummy poly 6 and 7, is further continued for
Etch to remove dielectric layer 1 and 2；The bottom-exposed of groove 9 and 10 go out with the corresponding substrate of dummy poly 6 and 7, and exposure lining
Bottom is the position of nmos pass transistor and PMOS transistor channel region；
Then, fluorine ion injection is performed to be doped to exposed substrate, as having choosing, the concentration of fluorine ion impurity
Less than 3e15atom/cm3, the energy of fluorine ion injection should not exceed the energy for making fluorine ion pass through interlayer insulative layer 3, to avoid
Harmful effect is produced to forming source-drain area in subsequent technique；
As shown in Figure 2 c, cushion oxide layer 11 and 12 is formed in the bottom of groove 9 and 10 by thermal oxide or chemical oxidation, and
Perform and anneal for the first time, as preferred, the Millisecond that 900 degrees Celsius to 1200 degrees Celsius of temperature range is annealed into for the first time is moved back
Fire, cushion oxide layer 11 and 12 is diffused to by fluorine ion by channel region；
As shown in Figure 2 d, deposition forms high dielectric layer 13 and 14 in cushion oxide layer 11 and 12, and execution is moved back for the second time
Fire, as preferred, be annealed into the short annealing of 600 degrees Celsius to 800 degrees Celsius of temperature range, fluorine ion is expanded for the second time
High dielectric layer 13 and 14 is spilt into, and activates fluorine ion, replaces the oxygen atom in high dielectric layer；
As shown in Figure 2 e, metal work function layer 15 and 16 is formed on high dielectric layer, on metal work function layer 15 and 16
Deposited metal cobalt layers (not shown)；Perform cmp to expose interlayer insulative layer 3, form metal gates 17 and 18.
The manufacture method of high dielectric layer metal gate device provided by the present invention, holds after dummy poly and dielectric layer is removed
Row fluorine ion injects, and carries out first time annealing after pad oxide is formed, and performs and moves back for the second time after high dielectric layer is formed
Fire, makes fluorine ion diffuse to cushion oxide layer and high dielectric layer by the channel region of substrate, with unstable Hydrogenbond formation fluorine
Silicon group, reduce fluorine ion by dummy poly diffuse into high dielectric layer during technique uncontrollability and technology difficulty.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
God is with principle, and any modification, equivalent substitution and improvements done etc. should be included within the scope of protection of the invention.
Claims (7)
1. a kind of manufacture method of high dielectric layer metal gate device, including：
Being formed on substrate includes the grid structure of dielectric layer, dummy poly and sidewall oxide；
Deposition forms interlayer insulative layer on substrate, and carries out cmp to expose the dummy poly；
Etching removes dummy poly and dielectric layer, to form the groove of bottom-exposed substrate corresponding with dummy poly；
Fluorine ion injection is performed to be doped exposed substrate；
Form cushion oxide layer in the bottom portion of groove and perform and anneal for the first time；
Deposition forms high dielectric layer and performs second and anneals in the cushion oxide layer；
Metal gates are formed on the high dielectric layer；Wherein,
The substrate is silicon.
2. according to the method described in claim 1, it is characterised in that being formed on substrate includes dielectric layer, dummy poly and side
The grid structure of wall oxide layer includes：
NMOS active areas and PMOS active areas are formed on substrate, and shallow ridges is formed between NMOS active areas and PMOS active areas
Groove is isolated；Form NMOS dielectric layers and PMOS dielectric layers, and the pseudo- polycrystalline of NMOS respectively on NMOS active areas and PMOS active areas
Silicon and PMOS dummy polies, and in NMOS dielectric layers, the both sides of NMOS dummy polies and PMOS dielectric layers, PMOS dummy polies
Both sides form sidewall oxide.
3. method according to claim 2, it is characterised in that include passing through in bottom portion of groove formation cushion oxide layer
Thermal oxide or chemical oxidation are in bottom portion of groove formation cushion oxide layer.
4. method according to claim 3, it is characterised in that forming metal gates on high dielectric layer includes：In Gao Jie
Metal work function layer is formed in electric layer；The deposited metal layer on metal work function layer；Cmp is performed with exposure
Interlayer insulative layer.
5. the method according to any one of Claims 1-4, it is characterised in that perform fluorine ion injection with to exposed lining
After bottom is doped, the concentration of fluorine ion impurity is less than 3e15atom/cm3。
6. method according to claim 5, it is characterised in that the first time is annealed into 900 degrees Celsius of temperature range extremely
1200 degrees Celsius of Millisecond annealing；It is described to be annealed into quickly moving back for 600 degrees Celsius to 800 degrees Celsius of temperature range for the second time
Fire.
7. method according to claim 6, it is characterised in that the material of the metal level is cobalt.
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| CN201210415303.0A CN103779280B (en) | 2012-10-26 | 2012-10-26 | The manufacture method of high dielectric layer metal gate device |
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| CN201210415303.0A CN103779280B (en) | 2012-10-26 | 2012-10-26 | The manufacture method of high dielectric layer metal gate device |
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| CN105633070B (en) * | 2014-10-29 | 2018-12-21 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof |
| US10134873B2 (en) * | 2016-11-18 | 2018-11-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device gate structure and method of fabricating thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102206799A (en) * | 2011-04-20 | 2011-10-05 | 北京大学 | Surface passivation method for germanium-based MOS (Metal Oxide Semiconductor) device substrate |
| CN102738221A (en) * | 2011-04-14 | 2012-10-17 | 台湾积体电路制造股份有限公司 | Method of fabricating a gate dielectric layer |
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| KR100788361B1 (en) * | 2006-12-12 | 2008-01-02 | 동부일렉트로닉스 주식회사 | Method of forming mosfet device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102738221A (en) * | 2011-04-14 | 2012-10-17 | 台湾积体电路制造股份有限公司 | Method of fabricating a gate dielectric layer |
| CN102206799A (en) * | 2011-04-20 | 2011-10-05 | 北京大学 | Surface passivation method for germanium-based MOS (Metal Oxide Semiconductor) device substrate |
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