CN105514103A - 静电放大保护器件 - Google Patents

静电放大保护器件 Download PDF

Info

Publication number
CN105514103A
CN105514103A CN201510632924.8A CN201510632924A CN105514103A CN 105514103 A CN105514103 A CN 105514103A CN 201510632924 A CN201510632924 A CN 201510632924A CN 105514103 A CN105514103 A CN 105514103A
Authority
CN
China
Prior art keywords
semiconductor
region
electrostatic discharge
diode
array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201510632924.8A
Other languages
English (en)
Other versions
CN105514103B (zh
Inventor
霍德弗里德·亨克里斯·约瑟夫斯·诺特曼斯
汉斯-马丁·里特
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Naizhiya Co Ltd
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV filed Critical NXP BV
Publication of CN105514103A publication Critical patent/CN105514103A/zh
Application granted granted Critical
Publication of CN105514103B publication Critical patent/CN105514103B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
    • H01L27/0647—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
    • H01L27/067—Lateral bipolar transistor in combination with diodes, or capacitors, or resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/87—Thyristor diodes, e.g. Shockley diodes, break-over diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0626—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a localised breakdown region, e.g. built-in avalanching region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/7404—Thyristor-type devices, e.g. having four-zone regenerative action structurally associated with at least one other device
    • H01L29/7412—Thyristor-type devices, e.g. having four-zone regenerative action structurally associated with at least one other device the device being a diode
    • H01L29/7416—Thyristor-type devices, e.g. having four-zone regenerative action structurally associated with at least one other device the device being a diode the device being an antiparallel diode, e.g. RCT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/7436—Lateral thyristors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本公开涉及一种静电放电(ESD)保护器件。所述静电放电保护器件可以包括：半导体控制型整流器以及p-n二极管。在半导体衬底的主表面上横向一体布置所述半导体控制型整流器和所述二极管；并且所述半导体控制型整流器的电流通路与所述二极管的电流通路相分离。

Description

静电放大保护器件
技术领域
本公开涉及一种半导体静电放电保护器件。具体地，本公开涉及这种静电放电保护器件的阵列。更具体地，本公开涉及一种包括这种静电放电保护器件或者这种静电放电保护器件的阵列的数据传输线或数据接口。
背景技术
诸如电过应力或静电放电(ESD)瞬时脉冲的电涌是电子设备损坏的常见原因。为保护对抗这些瞬时电涌，通常通过电涌或ESD保护器件来保护电子设备。这些器件提供对抗电过应力或静电放电的保护，一般用于便携式/消费电子设备(例如个人计算机、音频和视频设备、或者移动电话)。这些器件还可以用于在这些便携式/消费电子设备中使用的数据传输线或数据接口。根据国际电子技术委员会(InternationalElectrotechnicalCommission)标准IEC61000-4-2(也称为“gun测试”)，这些设备应当在高达8kV的系统级ESD应力下得到保护。
然而，便携式/消费电子设备的原始设备制造商(OEM)开始要求高达15kV放电的保护。为实现提高的保护级别，ESD设备可以简单地造得更大。然而，较大的设备将导致设备电容增加。必须在不妨碍设备正常操作的同时，根据IEC标准保护便携式/消费电子设备不受ESD事件影响。在包括高速接口(例如通用串行总线USB或高清多媒体接口HDMI)的应用中，ESD设备必须具有较小的设备电容，以便保持沿数据传输线或数据接口处的信号完整性。
发明内容
已知使用所谓的半导体控制型整流器(SCR)和二极管作为ESD设备的基础。
一种涉及半导体静电放电保护设备的实施例，包括：半导体控制型整流器；以及
p-n二极管；其中所述半导体控制型整流器和所述二极管在半导体衬底的主表面上横向一体布置；并且所述半导体控制型整流器的电流通路(currentpath)与所述二极管的电流通路相分离。
所述半导体控制型整流器可以包括相反类型的第一晶体管和第二晶体管，其中：所述第一晶体管的基极和发射极布置为第一输入端；所述第二晶体管的基极和发射极布置为第二输入端；并且所述二极管连接在所述第一输入端和第二输入端之间。
所述二极管可以布置在所述第一晶体管的基极和所述第二晶体管的基极之间。
所述半导体控制型整流器可以包括具有第一导电类型的第一半导体区和具有与第一导电类型相反的第二导电类型的第二半导体区；其中所述p-n二极管包括第二半导体区和具有第一导电类型的第三半导体区。
第一半导体区、第二半导体区以及第三半导体区可以各自包括相应的相反导电类型的第一掺杂区和第二掺杂区。
所述p-n二极管包括第三半导体区的第一掺杂区和第二半导体区的第二掺杂区
第一半导体区的相应第一掺杂区和第二掺杂区和第三半导体区的相应第一和第三掺杂区可以包括第一输入端，并且第二半导体区的相应第一掺杂区和第二掺杂区可以包括第二输入端。
实施例可以涉及一种半导体静电放电保护器件的阵列，可以包括在衬底上横向一体布置的半导体控制型整流器和二极管的交替阵列。
实施例可以涉及半导体静电放电保护器件的阵列，其中所述阵列包括相反导电性的第一半导体区和第二半导体区的横向布置。
第一半导体区的相应第一掺杂区和第二掺杂区可以形成所述阵列的第一输入端子，并且第二半导体区的相应第一掺杂区和第二掺杂区可以形成所述阵列的第二输入端子
所述半导体控制型整流器还可以包括低电压触发注入物或扩散物。
一种数据传输线，可以包括根据实施例的静电放电保护器件或者根据实施例的静电放电保护器件的阵列。
一种数据接口，包括根据实施例的静电放电保护器件或者根据实施例的静电放电保护器件的阵列。
附图说明
在附图和以下描述中，相似的附图标记指代相似的特征。以下仅通过示例方式，参考附图进一步描述实施例，其中：
图1示出了SCR和p-n二极管ESD保护器件的等效电路图；
图2-1示出了图1所示类型的SCR和p-n二极管ESD保护器件的示意横截面；
图2-2示出了图2-1的ESD保护器件的任意阵列的示意横截面结构；
图3-1示出了ESD保护器件的SCR的电流通路；
图3-2示出了ESD保护器件阵列中SCR的电流通路；
图4-1示出了ESD保护器件的二极管的电流通路；
图4-2示出了ESD保护器件阵列中二极管的电流通路；
图5-1示出了ESD保护器件的SCR和二极管的共享电流通路；
图5-2示出了ESD保护器件阵列中SCR和二极管的共享电流通路；
图6-1示出了SCR和p-n二极管ESD保护器件的共享电流通路；
图6-2示出了形成ESD保护器件阵列的SCR和p-n阵列的示意横截面；
图7-1示出了ESD保护器件的SCR的电流通路；
图7-2示出了ESD保护器件阵列的SCR的电流通路；
图8-1示出了ESD保护器件的二极管的电流通路；
图8-2示出了ESD保护器件阵列的二极管的电流通路；
图9-1示出了ESD保护器件的SCR和二极管的分离电流通路；以及
图9-2示出了ESD保护器件阵列的SCR和二极管的分离电流通路。
具体实施方式
图1中示出了ESD保护器件100的等效电路。总体上，ESD保护器件100可以包括信号端子104和接地端子102。ESD保护器件100可以有效地被认为是其中p-n-p晶体管106连接到n-p-n晶体管108形成SCR110的装置，并且该装置上还跨接p-n二极管112，如下文所述。
p-n-p晶体管106的集电极可以连接到n-p-n晶体管108的基极，并且p-n-p晶体管106的基极可以连接到n-p-n晶体管108的集电极。通过这种方式，ESD保护器件100可以被认为包括硅控制型整流器(SCR)110。n-p-n晶体管108的发射极可以形成ESD保护器件100的接地端子102，并且p-n-p晶体管106的发射极可以形成ESD保护器件的信号端子104。p-n二极管112，也称为反向二极管(back-diode)可以跨接在信号端子104和接地端子102之间。Rnw和Rpw是相应n型和p型阱的扩展(spreading)电阻，如下文所述。图2-1示出了ESD保护器件100的示意横截面结构，ESD保护器件100包括在图1的电路图中示出SCR110和p-n二极管。ESD保护器件100可以形成在其中形成有n型阱区(nw)220的p型衬底240之中。p+型扩散区210和n+型扩散区225可以形成在n型阱区220之中。p型衬底240中也可以形成p型阱区(pw)230。n+型扩散区250和p+型扩散区235可以形成在p型阱区230之中。图2-2示出了图2-1所示的ESD保护器件100的阵列的示意横截面结构。
根据图2-1和图2-2的示意横截面结构以及图1的电路图，SCR110可以被认为由四个横向布置的交替的n型和p型半导体材料层组成，形成p-n-p-n结构。p-n-p晶体管106的发射极可以由p+型扩散区210形成，p-n-p晶体管106的基极可以由n型阱区(nw)220形成，并且p-n-p晶体管106的集电极可以由p型阱区(pw)230和p+扩散区235形成。经由n+扩散区225接触p-n-p晶体管106的基极。n-p-n晶体管108的发射极可以由n+扩散区250形成，n-p-n晶体管108的基极可以由p型阱区(pw)230和p型衬底240形成。n-p-n晶体管108的集电极可以由n型阱区(nw)220和n+型扩散区225形成。经由p+区域234接触n-p-n晶体管108的基极。在这一方面，本领域技术人员将认识到，n型阱区(nw)220可以在p-n-p晶体管106的基极和n-p-n晶体管108的集电极之间共享，并且可以一体形成p-n-p晶体管106的基极和n-p-n晶体管108的集电极。本领域技术人员还将认识到，p型阱区230可以在p-n-p晶体管106的集电极和n-p-n晶体管108的基极之间共享，并且可以一体形成p-n-p晶体管106的集电极和n-p-n晶体管108的基极。因此，p-n-p-n层中的某些层可以在p-n-p晶体管106和n-p-n晶体管108之间共享。
ESD器件100的p-n二极管112可以由p+型扩散区235和n+型扩散区225形成，其中p+型扩散区235形成在p型阱区(pw)230和p型衬底240中，可以形成p-n二极管112的阳极，n+型扩散区225形成在n型阱区(nw)220中，可以形成p-n二极管112的阴极。通过这种方式，p-n二极管112可以和SCR100一体形成在衬底240中。p+扩散区235可以同时用作n-p-n晶体管108的基极接触和p-n二极管112的阳极。在p型阱区(pw)230中形成的p+扩散区235可以连接到n+扩散区250，形成ESD保护器件110的接地端子102。n+扩散区225可以同时用作p-n-p晶体管106的基极接触和p-n二极管112的阴极。在n型阱区220中形成的n+扩散区225可以连接到p+扩散区210，形成ESD器件的信号端子104。因此，本领域技术人员将看出，共享SCR110和二极管112的电流通路，如图5-1和5-2所示。
可以由信号端子104上相对于接地端子102的可能由ESD事件引起的正应力电压激活SCR110。电流可以从p+扩散区210流向n+扩散区250，如图3-1和3-2所示。通过这种方式，端子104上的过多电流可以漏至接地，并且可以限制信号端子104上的电压，以保护连接到端子104的任何外部设备不受由正ESD事件引起的过电压和过电流。在该上下文中，电压被限制为ESD保护器件100的钳位电压(clampingvoltage)。钳位电压可以被认为是相对于击穿电压的SCR110的扣回电压(snap-backvoltage)以及由流过器件的电流和器件导通电阻引起的电压降之和。可以选择钳位电压，使其低于可能损坏要保护的系统的临界电压。
针对信号端子104上相对于接地端子102的可能由ESD事件引起的负应力电压，ESD保护器件100操作为在p型阱区(pw)230中形成的p+扩散区235和在n型阱区(nw)220中形成的n+扩散区225之间的p-n二极管，如图4-1和4-2所示。通过这种方式，端子104上来自ESD事件的过多电流可以漏至接地，并限制端子104上的电压，以保护连接到端子104的任何外部设备不受由负ESD事件引起的过电压和过电流。
图5-1和5-2示出SCR110和p-n二极管112共享电流通路。图5-1和5-2是将图3-1、3-2和4-1、4-2重叠的图，示出当SCR导通或激活时正应力电压的电流通路以及当二极管导通或激活时负应力电压的电流通路。
ESD性能(也称为ESD强度或健壮度)是指ESD器件耐受增加的ESD电流(通常是宽度在100ns范围内的脉冲)直到出现ESD器件的热损害的能力。ESD性能可以用所谓的二次击穿电流It2(指代瞬态线路脉冲(TLP)测试)来表示，或者备选地用所施加的ESD事件的千伏(kV)(指代IEC“gun测试”)来表示。二次击穿电流也称为故障电流It2，是指处于这一电流时器件温度超过硅的熔化温度，1414摄氏度。
p-n二极管112的健壮度可能比SCR110的健壮度低得多。为实现两种极性ESD事件的特定健壮级别，例如针对正应力脉冲和反应力脉冲，It2＞30A或ESD＞15kV，整个器件就必须变大，使得二极管满足健壮度要求。然而，变大导致SCR可能比所需要的更大，因此，ESD器件的总电容可能增大。
可能存在需要具有相似健壮度的SCR和p-n二极管的组合的应用。
参考图6-1和图6-2，示出了根据实施例的ESD器件100的横截面。ESD保护器件100可以形成在其中形成有n型阱区(nw)220的p型衬底240中。p+型扩散区210和n+型扩散区225可以形成在n型阱区220中。第一p型阱区(pw)230-1也可以形成在p型衬底240中。n+型扩散区250-1和p+型扩散区235-1可以形成在第一p型阱区(pw)230-1中。第二p型阱区(pw)230-2也可以形成在p型衬底240中。n+型扩散区250-2和p+型扩散区235-2可以形成在第二p型阱区(pw)230-2中。
n型阱区(nw)220、第一p型阱区(pw)230-1以及第二p型阱区(pw)230-2可以沿p型衬底240的第一主表面相对彼此地横向布置。第一p型阱区(pw)230-1和第二p型阱区(pw)230-2可以形成在n型阱区(nw)220的相对侧。换句话说，n型阱区(nw)220布置在第一p型阱区(pw)230-1和第二p型阱区(pw)230-2之间。
SCR110可以由四个横向布置的交替的n型和p型半导体材料层组成，以形成p-n-p-n结构。p-n-p晶体管106的发射极可以由p型扩散区210形成，p-n-p晶体管106的基极可以由n型阱区(nw)220形成，并且p-n-p晶体管106的集电极可以由p型阱区(pw)230-1和p+扩散区235-1形成。经由n+扩散区225接触p-n-p晶体管106的基极。n-p-n晶体管108的发射极可以由p+扩散区235-1形成，n-p-n晶体管108的基极可以由p型阱区(pw)230-1和p衬底240形成，并且n-p-n晶体管108的集电极可以由n型阱区(nw)220和n+型扩散区225形成。经由p+区域235-1接触n-p-n晶体管108的基极。
ESD器件100的p-n二极管112可以由p+型扩散区235-2和n+型扩散区225形成，其中p+型扩散区235-2形成在p型阱区(pw)230-2和p型衬底240中，可以形成p-n二极管112的阳极，n+型扩散区225形成在n型阱区(nw)220中，可以形成p-n二极管112的阴极。通过这种方式，p-n二极管112可以和SCR100一体形成在衬底240中。
图6-2示出了包括图6-1所示类型器件的阵列的多指状物阵列(multi-fingerarray)，其为n和p阱的交替结构，其中每一个n阱或p阱包括相应的n+和p扩散区。因重复的相同结构，连接到接地端子(或输入端)102的p型阱区(pw)可以被认为具有平移对称性。也就是说，第一指状物的p型阱区230-1可以与下一指状物的p型阱区230-3重叠或相同。相应地，第一指状物的n+扩散区250-1可以与下一指状物的n+扩散区250-2重叠或相同。该布置使得一个指状物的p型阱区(pw)230-2可以与下一个指状物的p型阱区(pw)230-1相同。对n+扩散区250-1和250-2以及p+扩散区235-1和235-2，同样如此。该结构可以在必要时重复。
在阵列或多指状物布局的情形中，p+型扩散区235-2可以同时用作n-p-n晶体管108的基极接触和p-n二极管112的阳极。在p型阱区(pw)230-1和230-2中形成的p+型扩散区235-1和235-2可以连接到n+扩散区250-1和250-2，以形成ESD器件110的接地端子102。n+扩散区225同时用作p-n-p晶体管106的基极接触和p-n二极管112的阴极。在n型阱区220中形成的n+型扩散区225可以连接到p+型扩散区210，以形成ESD器件的信号端子(或输入端)104。
图7-1和7-2示出了当信号端子上施加相对接地端子102为正的过电压(或ESD事件)时器件的功能。在图7-1和7-2中，可以由信号端子104上相对接地端子102的正应力电压激活SCR110。电流可以从p+扩散210流到n+扩散250，如图7-1和7-2所示。通过这种方式，端子104上的过多电流可以漏至接地，并且可以限制信号端子104上的电压，以保护连接到端子104的任何外部设备不受过电压和过电流。
针对信号端子104上相对于接地端子102的负电压，ESD保护器件100操作为在p型阱区(pw)230中形成的p+扩散区235和在n型阱区(nw)220中形成的n+扩散区225之间的p-n二极管，如图8-1和8-2所示。通过这种方式，端子104上的过多电流可以漏至接地，并限制端子104上的电压，以保护连接到端子104的任何外部设备不受过电压和过电流。
图9-1和9-2示出SCR和二极管可以不共享电流通路。图9-1和9-2是将图7-1、7-2和8-1、8-2重叠的图，示出当SCR导通时正脉冲的电流通路以及当二极管导通时负脉冲的电流通路。
因此，本领域技术人员将看出，SCR110和二极管112不共享电流通路，如图7-1、7-2、8-1、8-2以及9-1、9-2所示。
ESD保护器件100可以布置为多指状物的阵列，即交替导电类型的指状物或区域，使得指状物单位宽度的最大电流健壮度(TLP测量)典型地在每微米宽度50至100mA的范围中。为实现30A的总电流健壮度，阵列的总宽度可以在300至600微米的范围中。由于器件金属化的布局限制，具有该总宽度的单个器件不可用，这限制了具体金属化的最大总电流。因此，可以将多个器件相互平行布置，其中包括例如5至10个指状物，每个指状物宽度是例如30微米至60微米。
当将多个指状物相互紧靠着布置时，作为良好实践，通过部署上述平移对称性，将相似的扩散区重叠，可以最小化总使用面积。
然而，本领域技术人员将理解，可以根据所需要的ESD和电容性能来选择多器件阵列中ESD器件100的数量，其中，通过在结构中增加更多的ESD器件100，可以实现更高的ESD性能，但这将付出电容增加的代价。
上文讨论的ESD器件或阵列可以并入在高数据速率互连或接口中，例如HDMI、USB、MHL。通过将信号线连接到具体数据连接或接口的数据线，可以将ESD器件或阵列并入。ESD器件或阵列的接地连接可以连接到具体数据连接或接口的相应接地连接。
在所附的独立权利要求中阐述了本发明的具体和优选方面。可以将从属和/或独立权利要求的特征组合进行适当组合，而不仅限于权利要求所述。
虽然上述讨论参考了通过在衬底中扩散形成各种p型区和n型区，本领域技术人员将理解，这些区可以通过已知的适当外延生长技术来形成。在这一方面，对扩散的任何参考不将所述装置限制为仅通过扩散形成的结构，还包括仅外延生长结构，或者外延生长和扩展的组合。此外，对衬底中区域结构的参考也可以理解为在衬底处或衬底上。
此外，虽然上文对p型区和n型区的具体布置进行参考，本领域技术人员将理解，以上布置不限于该方式。在这一方面，本领域技术人员将理解，p型衬底也可以是n型衬底，并且相应的n和p型区合适地调换为p和n型区。
本公开的范围包括明确或含蓄公开的任何新特征的或特征组合或者其概括，不论它是否涉及所要求保护的发明或者减轻本发明提出的任何或全部问题。申请人在此给出通知，在本申请或由其衍生的任何此类进一步申请的审查过程中，可以形成新的权利要求。具体地，参考所附的权利要求，来自从属权利要求的特征可以与独立权利要求的特征相组合，并且来自各独立权利要求的特征可以以适当方式相组合，而不仅限于权利要求所列的特定组合。
这在各分离实施例的上下文中描述的特征也可以组合在单个实施例中提供。相反，为了简洁起见而在单个实施例的上下文中描述的各种特征，也可以分离或以任何合适的子组合方式提供。
术语“包括”不排除其他元件或步骤，术语“一”或“一个”并不排除多个。权利要求中附图标记不应当被解释为对权利要求的范围的限制。

Claims (13)

1.一种半导体静电放电保护器件，包括：
半导体控制型整流器；以及
p-n二极管；
其中在半导体衬底的主表面上横向一体布置所述半导体控制型整流器和所述二极管；并且所述半导体控制型整流器的电流通路与所述二极管的电流通路相分离。
2.根据权利要求1所述的半导体静电放电保护器件，所述半导体控制型整流器包括相反类型的第一晶体管和第二晶体管，其中
所述第一晶体管的基极和发射极布置为第一输入端；
所述第二晶体管的基极和发射极布置为第二输入端；以及
所述二极管连接在所述第一输入端和第二输入端之间。
3.根据权利要求2所述的半导体静电放电保护器件，其中所述二极管布置在所述第一晶体管的基极和所述第二晶体管的基极之间。
4.根据前述任一项权利要求所述的半导体静电放电保护器件，
其中所述半导体控制型整流器包括具有第一导电类型的第一半导体区和具有与第一导电类型相反的第二导电类型的第二半导体区；并且所述p-n二极管包括第二半导体区和具有第一导电类型的第三半导体区。
5.根据权利要求4所述的半导体静电放电保护器件，其中第一半导体区、第二半导体区以及第三半导体区各自包括相应相反导电类型的第一掺杂区和第二掺杂区。
6.根据权利要求5所述的半导体静电放电保护器件，其中所述p-n二极管包括第三半导体区的第一掺杂区和第二半导体区的第二掺杂区。
7.根据权利要求2至5之一所述的半导体静电放电保护器件，其中第一半导体区的相应第一掺杂区和第二掺杂区以及第三半导体区的相应第一掺杂区和第三掺杂区各自包括第一输入端，并且第二半导体区的相应第一掺杂区和第二掺杂区包括第二输入端。
8.一种根据权利要求1至7之一所述的半导体静电放电保护器件的阵列，包括在衬底上横向一体布置的半导体控制型整流器和二极管的交替阵列。
9.根据权利要求8所述的半导体静电放电保护器件的阵列，其中所述阵列包括相反导电性的第一半导体区和第二半导体区的横向布置。
10.根据权利要求9所述的半导体静电放电保护器件的阵列，其中第一半导体区的相应第一掺杂区和第二掺杂区形成所述阵列的第一输入端子，并且第二半导体区的相应第一掺杂区和第二掺杂区形成所述阵列的第二输入端子。
11.根据权利要求8至10之一所述的阵列，其中所述半导体控制型整流器还包括低电压触发注入物或扩散物。
12.一种数据传输线，包括根据权利要求1至7之一所述的静电放电保护器件或者根据权利要求8至11之一所述的静电放电保护器件的阵列。
13.一种数据接口，包括根据权利要求1至7之一所述的静电放电保护器件或者根据权利要求8至11之一所述的静电放电保护器件的阵列。
CN201510632924.8A 2014-10-08 2015-09-29 静电放电保护器件 Active CN105514103B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP14188198.7A EP3007232A1 (en) 2014-10-08 2014-10-08 Electrostatic discharge protection device
EP14188198.7 2014-10-08

Publications (2)

Publication Number Publication Date
CN105514103A true CN105514103A (zh) 2016-04-20
CN105514103B CN105514103B (zh) 2018-08-28

Family

ID=51661980

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510632924.8A Active CN105514103B (zh) 2014-10-08 2015-09-29 静电放电保护器件

Country Status (3)

Country Link
US (1) US9385115B2 (zh)
EP (1) EP3007232A1 (zh)
CN (1) CN105514103B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10141300B1 (en) 2017-10-19 2018-11-27 Alpha And Omega Semiconductor (Cayman) Ltd. Low capacitance transient voltage suppressor
FR3079347B1 (fr) 2018-03-26 2021-02-19 St Microelectronics Tours Sas Protection contre les decharges electrostatiques et filtrage
KR20200074581A (ko) 2018-12-17 2020-06-25 에스케이하이닉스 주식회사 Esd 보호 장치
CN112310066A (zh) * 2019-07-29 2021-02-02 力特半导体（无锡）有限公司 具有二极管和硅控制整流器布置的半导体放电防护装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040082832A (ko) * 2003-03-20 2004-09-30 주식회사 하이닉스반도체 반도체장치의 보호소자
US20060097321A1 (en) * 2004-11-10 2006-05-11 Kil-Ho Kim Electrostatic discharge protection device
US20110303947A1 (en) * 2010-06-09 2011-12-15 Analog Devices, Inc. Apparatus and method for protecting electronic circuits
CN103490399A (zh) * 2012-04-24 2014-01-01 Nxp股份有限公司 保护电路
US20140138735A1 (en) * 2012-11-20 2014-05-22 Analog Devices, Inc. Junction-isolated blocking voltage devices with integrated protection structures and methods of forming the same
US20140167104A1 (en) * 2012-12-19 2014-06-19 Analog Devices, Inc. Interface protection device with integrated supply clamp and method of forming the same

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8432651B2 (en) * 2010-06-09 2013-04-30 Analog Devices, Inc. Apparatus and method for electronic systems reliability

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040082832A (ko) * 2003-03-20 2004-09-30 주식회사 하이닉스반도체 반도체장치의 보호소자
US20060097321A1 (en) * 2004-11-10 2006-05-11 Kil-Ho Kim Electrostatic discharge protection device
US20110303947A1 (en) * 2010-06-09 2011-12-15 Analog Devices, Inc. Apparatus and method for protecting electronic circuits
CN103490399A (zh) * 2012-04-24 2014-01-01 Nxp股份有限公司 保护电路
US20140138735A1 (en) * 2012-11-20 2014-05-22 Analog Devices, Inc. Junction-isolated blocking voltage devices with integrated protection structures and methods of forming the same
US20140167104A1 (en) * 2012-12-19 2014-06-19 Analog Devices, Inc. Interface protection device with integrated supply clamp and method of forming the same

Also Published As

Publication number Publication date
EP3007232A1 (en) 2016-04-13
US20160104700A1 (en) 2016-04-14
US9385115B2 (en) 2016-07-05
CN105514103B (zh) 2018-08-28

Similar Documents

Publication Publication Date Title
KR101784061B1 (ko) 과도 전압 보호 회로 및 디바이스
US8232601B1 (en) Transient voltage suppressors
CN102593122B (zh) 半导体esd电路和方法
EP2789012B1 (en) A high holding voltage, mixed-voltage domain electrostatic discharge clamp
US8237193B2 (en) Lateral transient voltage suppressor for low-voltage applications
US8552530B2 (en) Vertical transient voltage suppressors
US8169000B2 (en) Lateral transient voltage suppressor with ultra low capacitance
CN111106107A (zh) 低电容瞬态电压抑制器
US9171833B2 (en) Semiconductor structure for enhanced ESD protection
CN103579224B (zh) Esd保护
CN104205345A (zh) 具有交替导电类型的区域的用于静电放电保护的半导体装置
CN105514103A (zh) 静电放大保护器件
CN105552873A (zh) 一种浪涌防护器件
US8735979B2 (en) Multi-channel homogenous path for enhanced mutual triggering of electrostatic discharge fingers
CN203983979U (zh) 使电路免受瞬态电事件损坏的装置和保护电路
CN104576638A (zh) Esd保护器件
CN103094273B (zh) 静电放电保护元件
TW202301771A (zh) 具有二極體的故障安全輸入/輸出靜電放電防護
Zhan et al. High-voltage asymmetrical bi-directional device for system-level ESD protection of automotive applications on a BiCMOS technology
EP3772102A1 (en) Semiconductor discharge protection device with diode and silicon controlled rectifier arrangements
CN102810849B (zh) 欠压保护系统
Notermans et al. An off-chip ESD protection for high-speed interfaces
US20190244953A1 (en) Suppression of parasitic discharge path in an electrical circuit
Lai et al. DNW-controllable triggered voltage of the integrated diode triggered SCR (IDT-SCR) ESD protection device
US20230215860A1 (en) Semiconductor device and bidirectional esd protection device

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20160914

Address after: Holland Ian Deho Finn

Applicant after: Naizhiya Co., Ltd.

Address before: Holland high tech park, Eindhoven 60 zip code: 5656AG

Applicant before: NXP BV

CB02 Change of applicant information

Address after: Nijmegen

Applicant after: Yasuyo Co. Ltd.

Address before: Holland Ian Deho Finn

Applicant before: Naizhiya Co., Ltd.

CB02 Change of applicant information
GR01 Patent grant
GR01 Patent grant