CN105511994A - Startup/shutdown and reset test card for computer motherboard - Google Patents
Startup/shutdown and reset test card for computer motherboard Download PDFInfo
- Publication number
- CN105511994A CN105511994A CN201511014430.XA CN201511014430A CN105511994A CN 105511994 A CN105511994 A CN 105511994A CN 201511014430 A CN201511014430 A CN 201511014430A CN 105511994 A CN105511994 A CN 105511994A
- Authority
- CN
- China
- Prior art keywords
- test card
- reset
- test
- shutdown
- startup
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 40
- 238000000034 method Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000011990 functional testing Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
The invention provides a startup/shutdown and reset test card for a computer motherboard. The startup/shutdown and reset test card for the computer motherboard comprises a test card body, wherein a Complex Programmable Logic Device (CPLD) chip, a Light Emitting Diode (LED) indicator lamp, an RS232 serial port, a reset circuit interface and a power interface are arranged on the test card body; the CPLD chip is connected with the RS232 serial port, the LED indicator lamp, the reset circuit interface and the power interface; the CPLD chip is connected with the motherboard through the RS232 serial port; the CPLD chip is connected with an ATX power supply, connected with the motherboard, through the power interface; the CPLD chip passes through the reset circuit interface. Compared with the prior art, the startup/shutdown and reset test card for the computer motherboard has the advantages that automatic testing is realized, and the manpower cost is reduced; long-time continuous testing can be performed, the test efficiency is improved, and the test time is shortened; the wrong time frequency can be automatically recorded, a test report is generated, and errors caused by human factors are reduced.
Description
Technical field
The invention belongs to computer motherboard technical field of measurement and test, especially relates to a kind of computer main-board on-off and reset test card.
Background technology
For the computer motherboard designed, all will carry out long switching on and shutting down test and reset test, verify the stability of main-board on-off and reset, with or without can not the situation of normal boot-strap, whether reset circuit can reset computing machine at every turn reliably; Generally will through the test of up to ten thousand times, statistics failure rate, for the application that ask for something is high, requires that failure rate is 0.Traditional main-board on-off test is all that by being accessed by motherboard, ATX power supply (or AT power supply) manually powers on, power-off realizes switching on and shutting down test, this method not only wastes manpower but also when switching on and shutting down number of times reaches certain value, tester is also difficult to accurate recording.
Summary of the invention
In view of this, the invention is intended to propose a kind of computer main-board on-off and reset test card, to save switching on and shutting down and reset test time and manpower.
For achieving the above object, the technical scheme of the invention is achieved in that
A kind of computer main-board on-off and reset test card, comprise test card body, described test card body be provided with CPLD chip, LED light, for connect mainboard RS232 serial ports, for connecting the reset circuit interface of mainboard reset circuit and the power interface for being connected mainboard ATX power supply, described CPLD chip connects RS232 serial ports, LED light, reset circuit interface and power interface.
Further, described CPLD chip selection selects model to be EPM1270CPLD chip.
Relative to prior art, the invention has following advantage:
Realize automatic test, save human cost; Long-time continuous can test, improve testing efficiency, shorten the test duration; Can the time number of times of misregistration automatically, produce test report, decrease because the mistake that causes of human factor.
Accompanying drawing explanation
The accompanying drawing of the part of formation the invention is used to provide the further understanding to the invention, and the schematic description and description of the invention, for explaining the invention, does not form the improper restriction to the invention.In the accompanying drawings:
The theory diagram that Fig. 1 is computer main-board on-off described in the invention embodiment and reset test card.
Embodiment
It should be noted that, when not conflicting, the embodiment in the invention and the feature in embodiment can combine mutually.
Below with reference to the accompanying drawings and describe the invention in detail in conjunction with the embodiments.
A kind of computer main-board on-off and reset test card, as shown in Figure 1, comprise test card body, described test card body is provided with CPLD chip, LED light, RS232 serial ports, reset circuit interface and power interface, described CPLD chip connects RS232 serial ports, LED light, reset circuit interface and power interface, and CPLD chip connects mainboard by RS232 serial ports; Described CPLD chip connects the ATX power supply be connected with mainboard by power interface, described CPLD chip is by reset circuit interface.
Described CPLD chip selection selects model to be EPM1270CPLD chip.
Mainboard guides inner BIOS after the power-up automatically, BIOS is used for the various hardware resources of initialization mainboard, RS232 is exactly the one of hardware resource, BIOS can send data " AA55 " by the TXD signal of RS232 after mainboard is started shooting smoothly, CPLD chip now on test card body captures this data, LED light accumulates once, the DOS program record switching on and shutting down number of times of host computer also accumulates once simultaneously, CPLD chip exports the PS_ON signal that high level realizes cutting off ATX power supply simultaneously, mainboard power-off, the PS_ON signal of CPLD chip time delay 10 seconds control ATX power supply afterwards becomes low level, such mainboard switches on power, repeat step above, realize switching on and shutting down.
This process not only achieves switch and test, and upper computer software also realizes the functional test to motherboard inside real time clock (RTC) by the record switching on and shutting down moment each time.
After Test Switchboard machine terminates, tester can open host computer procedure and check switching on and shutting down time each time and switching on and shutting down total degree, realizes automatically recording, shows, the object of main control system switching plate machine.
The foregoing is only the preferred embodiment of the invention; not in order to limit the invention; within all spirit in the invention and principle, any amendment done, equivalent replacement, improvement etc., within the protection domain that all should be included in the invention.
Claims (2)
1. a computer main-board on-off and reset test card, it is characterized in that: comprise test card body, described test card body be provided with CPLD chip, LED light, for connect mainboard RS232 serial ports, for connecting the reset circuit interface of mainboard reset circuit and the power interface for being connected mainboard ATX power supply, described CPLD chip connects RS232 serial ports, LED light, reset circuit interface and power interface.
2. computer main-board on-off according to claim 1 and reset test card, is characterized in that: described CPLD chip selection selects model to be EPM1270CPLD chip.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201511014430.XA CN105511994A (en) | 2015-12-28 | 2015-12-28 | Startup/shutdown and reset test card for computer motherboard |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201511014430.XA CN105511994A (en) | 2015-12-28 | 2015-12-28 | Startup/shutdown and reset test card for computer motherboard |
Publications (1)
Publication Number | Publication Date |
---|---|
CN105511994A true CN105511994A (en) | 2016-04-20 |
Family
ID=55719996
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201511014430.XA Pending CN105511994A (en) | 2015-12-28 | 2015-12-28 | Startup/shutdown and reset test card for computer motherboard |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN105511994A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110857959A (en) * | 2018-08-24 | 2020-03-03 | 西安恩狄集成电路有限公司 | Chip reset test board and test method |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1391164A (en) * | 2002-06-04 | 2003-01-15 | 威盛电子股份有限公司 | On-off test method for motherboard of computer |
US20030204790A1 (en) * | 2002-04-30 | 2003-10-30 | Via Technologies, Inc. | Computer main board on/off testing device, method and system |
US20130268708A1 (en) * | 2012-04-09 | 2013-10-10 | Feng-Chieh Huang | Motherboard test device and connection module thereof |
CN103376396A (en) * | 2012-04-16 | 2013-10-30 | 鸿富锦精密工业(深圳)有限公司 | Test circuit for motherboard |
CN104461816A (en) * | 2014-12-29 | 2015-03-25 | 合肥宝龙达信息技术有限公司 | Novel automatic startup and shutdown testing card for computer mainboard |
CN104657241A (en) * | 2013-11-18 | 2015-05-27 | 鸿富锦精密工业(深圳)有限公司 | Mainboard startup/shutdown testing circuit |
-
2015
- 2015-12-28 CN CN201511014430.XA patent/CN105511994A/en active Pending
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030204790A1 (en) * | 2002-04-30 | 2003-10-30 | Via Technologies, Inc. | Computer main board on/off testing device, method and system |
CN1391164A (en) * | 2002-06-04 | 2003-01-15 | 威盛电子股份有限公司 | On-off test method for motherboard of computer |
US20130268708A1 (en) * | 2012-04-09 | 2013-10-10 | Feng-Chieh Huang | Motherboard test device and connection module thereof |
CN103376396A (en) * | 2012-04-16 | 2013-10-30 | 鸿富锦精密工业(深圳)有限公司 | Test circuit for motherboard |
CN104657241A (en) * | 2013-11-18 | 2015-05-27 | 鸿富锦精密工业(深圳)有限公司 | Mainboard startup/shutdown testing circuit |
CN104461816A (en) * | 2014-12-29 | 2015-03-25 | 合肥宝龙达信息技术有限公司 | Novel automatic startup and shutdown testing card for computer mainboard |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110857959A (en) * | 2018-08-24 | 2020-03-03 | 西安恩狄集成电路有限公司 | Chip reset test board and test method |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN102023912B (en) | Dormancy wake-up testing system and method | |
CN104991629B (en) | Power-fail detecting system and its method | |
CN104572371A (en) | Abnormal power-down testing system for hard disk | |
KR20110124617A (en) | System-on-chip and debugging method thereof | |
CN106055440B (en) | A kind of test method and system for realizing server exception power-off by BMC | |
CN102520272B (en) | Test system of power down protection function of smart card and method | |
CN101937381B (en) | Test method of SGPIO (Serial General Purpose Input/Output) signal on SAS backboard | |
CN108009062A (en) | A kind of enterprise-level SSD system power failures function test method, apparatus and system | |
CN103364650A (en) | Testing system and testing method | |
CN105955911A (en) | Hot-plug control circuit and control method thereof | |
CN104484255A (en) | Fault injection device for verifying system level single particle soft error protection ability | |
CN105743707A (en) | Method for testing BMC log analysis function based on Redhat system | |
CN115083510B (en) | Solid state disk testing method and device, storage medium, power supply and electronic equipment | |
CN204203971U (en) | A kind of credible accounting system | |
CN203465715U (en) | Automatic startup and shutdown test system | |
TW201710699A (en) | Detecting apparatus for CPU slot connection of motherboard based on boundary scan and method thereof | |
CN109117371A (en) | A kind of fault filling method improving period BIT verifying ability | |
CN103078740B (en) | RFID smart card digital baseband checking system | |
CN105511994A (en) | Startup/shutdown and reset test card for computer motherboard | |
CN105117566A (en) | Method and device of analyzing PCIe eye patterns | |
CN201638219U (en) | Real-time FPGA verification system | |
CN205302268U (en) | Computer motherboard switching on and shutting down and test card that resets | |
CN204790996U (en) | CPU and FPGA combinatorial circuit of multiplex bus | |
CN104281459A (en) | BIOS upgrading device | |
CN112798942A (en) | Chip batch test method and system |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
RJ01 | Rejection of invention patent application after publication | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160420 |