CN109117371A - A kind of fault filling method improving period BIT verifying ability - Google Patents
A kind of fault filling method improving period BIT verifying ability Download PDFInfo
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- CN109117371A CN109117371A CN201810898978.2A CN201810898978A CN109117371A CN 109117371 A CN109117371 A CN 109117371A CN 201810898978 A CN201810898978 A CN 201810898978A CN 109117371 A CN109117371 A CN 109117371A
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- fault
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
- G06F11/3624—Software debugging by performing operations on the source code, e.g. via a compiler
Abstract
The present invention relates to a kind of fault filling methods of raising period BIT verifying ability, and the fault filling method includes: selection fault mode；Write the direct fault location function that can simulate the fault mode；The direct fault location function call injection into controlling application program and is compiled；Direct fault location function, simulated failure mode shown in executing.The present invention only writes simple function by being added in embedded host applications software, and executes simple command and embedded host applications software is added, and the injection of failure can be completed, do not damage system or equipment hardware, do not increase the volume and weight of product；The present invention is by writing the corresponding different functions of multiple and different fault modes, only compile primary embedded host applications software, it can be stored in system or equipment, run respective function when needing to verify some fault mode, reduce and repeat to modify or compile embedded host applications software work amount.
Description
Technical field
The invention belongs to electronic product testability demonstration technical fields more particularly to a kind of raising period BIT to verify ability
Fault filling method.
Background technique
Built-in test (BIT) is defined as the automatic test capability of the detection provided inside system or equipment and isolated fault.
According to test opportunity, it is generally divided into power-up BIT, period BIT and maintenance BIT.It is powered on after BIT powers on for system or equipment certainly
It is dynamic to press defined test content, it carries out detection and external offer signal is not provided；Period BIT is the system period or constantly detects pass
Key functional characteristic (such as servo rotational angle, communication function, wherein communication function be main control chip to antenna subsystem, hair
It penetrates between machine subsystem, radio frequency component subsystem etc. and sends control command, the status information that main control chip HF receiving subsystem returns
Communication) whether break down；Maintenance BIT is the inspection that maintenance personnel passes through button, switchs or manually start system or equipment progress
It surveys.
Testability demonstration test based on direct fault location, can be used for checking system or equipment BIT design level.Generally have
Hardware fault injection and software fault inject two methods.
The system or equipment of hardware fault injection is generally basede on after testability demonstration is tested, if to power on BIT into
Row verifying, then need under power blackout situation, and the hardware of system or equipment is carried out to the operation of open circuit or short circuit etc., then starting electricity
Source needs to be returned to original state after the test；After testability demonstration is tested, (device pin is bent journey to assembled state
The contact pin depth degree of degree, connector), " three proofings " measure (three-proofing coating, shielded layer etc.) etc. will receive influence or destruction, even
Device is needed replacing, can not also support direct fault location operation long-term, repeatedly, therefore generally therefore to cannot effectively support to be
The operations such as the failure of system or equipment reproduction injection, generally use for the system or equipment with integrated data processing ability at present
Software fault injection method is to reduce the damage to system or equipment.
If being verified to period BIT, is injected under fault condition using hardware, need to arrange opening for on-off signal in advance
Close, in system or equipment normal course of operation, switch is set to need position (such as primary circuit be access, be set to by switch disconnected
Road), whether verifying system or equipment can detect failure.But such open cannot be arranged in some high-speed buses or radiofrequency signal
It closes, can work system or equipment and cause to directly affect, and such fault mode has complicated integrated data processing ability
Accounting is larger in system or equipment.
At present in the testability demonstration test of software fault injection, the system or equipment with integrated data processing ability
The generally application processing software of embedded OS and logic complexity carries out powering on BIT and period automatically after startup power supply
BIT.When carrying out software fault injection failure using software, after generally requiring modification application software, burning into system or is set again
In standby processor, work is re-powered to system or equipment, carries out BIT detection, it is successfully and former to judge whether its failure is injected
Whether barrier can be detected, and the method can only be verified and power on BIT ability., then face one of proving period BIT is difficult to solve
The problem of, i.e., the operation for generally not having means to change its software in system or equipment operational process, therefore the verifying of period BIT
Ability is restricted, and greatly reduces testability demonstration ability.
Summary of the invention
The object of the present invention is to provide a kind of fault filling methods of raising period BIT verifying ability, for solving or subtracting
The light above problem.
In order to achieve the above objectives, the technical solution adopted by the present invention is that: it is a kind of improve period BIT verifying ability failure note
Enter method, the fault filling method includes:
Choose fault mode；
Write the direct fault location function that can simulate the fault mode；
The direct fault location function call injection into controlling application program and is compiled；
Direct fault location function, simulated failure mode shown in executing.
Wherein, the fault mode includes that RS422 bus communication is abnormal, 1553B bus communication is abnormal, pulse signal is different
Often.
Wherein, the direct fault location function corresponds to one in the fault mode.
Wherein, the controlling application program can store multiple direct fault location functions, with direct fault location letter when calling
Several words execute the direct fault location function.
Wherein, one in the fault mode is only executed in the controlling application program implementation procedure.
Wherein, the installation environment of the controlling application program is VxWork operating system.
The present invention only writes simple function by being added in embedded host applications software, and executes simple command and add
Enter embedded host applications software, the injection of failure can be completed, do not damage system or equipment hardware, does not increase the volume of product
And weight；The present invention only compiles primary embedded host applications by writing the corresponding different functions of multiple and different fault modes
Software can be stored in system or equipment, run respective function when needing to verify some fault mode, reduces and repeats to repair
Change or compile embedded host applications software work amount；The function that the present invention writes answers VxWorks system Central Plains when not running
It is not influenced with software, after operation, as long as restarting systems or equipment, Failure elimination is highly-safe.The method of the present invention
Simplicity runs function by input function name, injects failure, may be applicable in system or equipment course of normal operation
The host applications software for carrying out a large amount of period BIT verifyings, improves the ability of proving period BIT.
Detailed description of the invention
The drawings herein are incorporated into the specification and forms part of this specification, and shows and meets implementation of the invention
Example, and be used to explain the principle of the present invention together with specification.
Fig. 1 is automatic Verification system block diagram of the invention.
Specific embodiment
To keep the purposes, technical schemes and advantages of the invention implemented clearer, below in conjunction in the embodiment of the present invention
Attached drawing, technical solution in the embodiment of the present invention is further described in more detail.
Embodiment one
Referring to Fig. 1, the present invention is existed so that primary control program is arranged for injecting the failure of RS422 bus communication exception herein
It runs, is controlled between system or equipment and debugging computer with serial ports RS232, the host applications after compiling on PowerPC
Program is updated by network interface to system or equipment by Wind River workbench development platform, is once only injected into an event
Barrier
Step 1, selection needs the fault mode injected, and here for simulating RS422 bus communication exception, RS422 is logical
News are a critical functions in system or equipment, and each subsystem receives the control that primary control program is sent in integrated treatment subsystem
Order controls respective working condition and timing, and the self-test BIT information that respective status information includes respective subsystem is sent out
Primary control program is sent back to be judged and handled, if RS422 communication it is abnormal, gently if cannot report back self-test BIT information, it is heavy then each
Subsystem cisco unity malfunction；
Step 2 is write direct fault location function (the entitled dis_rs422 of function), the function by integrated treatment subsystem with penetrate
RS422 bus between frequency component subsystem, which is sent in transmitter register address corresponding to data, writes 0, and (simulation sends data
Mistake, register address should be control word under normal circumstances, not for 0), and RS422 bus be read reception corresponding to data
Also 0 is write in register address, and (the status data mistake that simulation receives, register address should be status word under normal circumstances, no
For 0) (premise of this two operations is modified register address without other module uses)；
Under normal circumstances, radio frequency component subsystem is by the transmission reading data in transmitter register, and in this fault simulation
In, register address content corresponding to data is set as 0, i.e. error in data.
The specific position that the function write is added to host applications software (can be increased this function of explanatory notes by step 3
Effect and purpose, convenient for searching and the later period is managed the function for direct fault location), and be compiled；
Step 4 judges whether to need once to write multiple direct fault location functions, if so, executing step 1, otherwise, executes
Step 5；
Step 5, system or equipment are connected in the power-offstate on RS232 serial ports and network interface to debugging computer；
Step 6, on debugging computer open RS232 Serial Communication Program (such as: hyper terminal, can be to embedded system
System send order, embedded system by the starting information of oneself, procedural information, to response message of order etc. be dealt into run it is super
On the debugging computer of terminal)；
Step 7 opens the power supply of system or equipment, and the time number of seconds shown on debugging computer is reduced to before 1,
It by debugging computer any key, is maintained at the process of system or equipment under uboot mode, stops entering VxWork operation system
System；
Step 8 is updated by network interface into system or equipment using u order by compiled host applications software；
Step 9, update finish, and restarting systems or equipment start to work normally,
Step 10, on debugging computer, input function name dis_rs422 in RS232 Serial Communication Program (or other therefore
Barrier mode injection function), whether observable system or equipment can detect the failure；
Step 11, if need to inject next failure, if then closing system or equipment power supply (is once only injected into one
A failure, in order to verify the period BIT ability under single failure mode), step 9 is executed, otherwise step 12；
Step 12, injection testing terminate.
Embodiment two
Step 1 selects fault mode, and here for simulating another bus 1553B bus communication exception, 1553B is logical
News are also that one in system or equipment carries out data exchange, such as phonic warning control word between critical function, with subsystem, such as
Fruit 1553B communication it is abnormal, then cannot to subsystem send signal, can not HF receiving subsystem return signal；
Step 2: writing direct fault location function (the entitled dis_1553B of function), and the function is by 1553B communication chip (Fig. 1
In 1553B interface in chip) on P11 pin be assigned a value of 0 so that P11 foot is always low level.
Under normal circumstances, the P11 pin on 1553B communication chip should be high level, and be set as in this fault simulation
Low level, i.e. 1553B communication failure.
The specific position that the function write is added to host applications software (can be increased this function of explanatory notes by step 3
Effect and purpose, convenient for searching and the later period is managed the function for direct fault location), and be compiled；
Step 4 judges whether to need once to write multiple direct fault location functions, if so, executing step 1, otherwise, executes
Step 5；
Step 5, system or equipment are connected in the power-offstate on RS232 serial ports and network interface to debugging computer；
Step 6, on debugging computer open RS232 Serial Communication Program (such as: hyper terminal, can be to embedded system
System send order, embedded system by the starting information of oneself, procedural information, to response message of order etc. be dealt into run it is super
On the debugging computer of terminal)；
Step 7 opens the power supply of system or equipment, and the time number of seconds shown on debugging computer is reduced to before 1,
It by debugging computer any key, is maintained at the process of system or equipment under uboot mode, stops entering VxWork operation system
System；
Step 8 is updated by network interface into system or equipment using u order by compiled host applications software；
Step 9, update finish, and restarting systems or equipment start to work normally,
Step 10, on debugging computer, input function name dis_1553B in RS232 Serial Communication Program (or other therefore
Barrier mode injection function), whether observable system or equipment can detect the failure；
Step 11, if need to inject next failure, if then closing system or equipment power supply (is once only injected into one
A failure, in order to verify the period BIT ability under single failure mode), step 9 is executed, otherwise step 12；
Step 12, injection testing terminate.
Embodiment three
Step 1: selection fault mode is sent to the frame pulse of antenna subsystem here with analog synthesis processing subsystem
For signal fault, frame signal is the clock sync signal that integrated treatment subsystem is sent, and makes scoring systems in same clock
Work, if subsystem does not receive frame signal or frame signal mistake, cannot work asynchronously with integrated treatment subsystem in period；
Step 2: direct fault location function (the entitled dis_PRF of function) is write, which is sent to integrated treatment subsystem
The frame pulse signal of antenna is set to 0 always, that is, simulates and do not send pulse signal.
Under normal circumstances, the frame pulse signal of transmission is the pulse signal of some cycles, this fault simulation is set to 0 always,
I.e. no pulse signal.
Step 3: following steps are with step 3 in example one, only when executing step 10, the entitled dis_PRF of the function of input.
The specific position that the function write is added to host applications software (can be increased this function of explanatory notes by step 3
Effect and purpose, convenient for searching and the later period is managed the function for direct fault location), and be compiled；
Step 4 judges whether to need once to write multiple direct fault location functions, if so, executing step 1, otherwise, executes
Step 5；
Step 5, system or equipment are connected in the power-offstate on RS232 serial ports and network interface to debugging computer；
Step 6, on debugging computer open RS232 Serial Communication Program (such as: hyper terminal, can be to embedded system
System send order, embedded system by the starting information of oneself, procedural information, to response message of order etc. be dealt into run it is super
On the debugging computer of terminal)；
Step 7 opens the power supply of system or equipment, and the time number of seconds shown on debugging computer is reduced to before 1,
It by debugging computer any key, is maintained at the process of system or equipment under uboot mode, stops entering VxWork operation system
System；
Step 8 is updated by network interface into system or equipment using u order by compiled host applications software；
Step 9, update finish, and restarting systems or equipment start to work normally,
Step 10, on debugging computer, input function name dis_PRF in RS232 Serial Communication Program (or other failures
Mode injection function), whether observable system or equipment can detect the failure；
Step 11, if need to inject next failure, if then closing system or equipment power supply (is once only injected into one
A failure, in order to verify the period BIT ability under single failure mode), step 9 is executed, otherwise step 12；
Step 12, injection testing terminate.
The present invention only writes simple function by being added in embedded host applications software, and executes simple command and add
Enter embedded host applications software, the injection of failure can be completed, do not damage system or equipment hardware, does not increase the volume of product
And weight；The present invention only compiles primary embedded host applications by writing the corresponding different functions of multiple and different fault modes
Software can be stored in system or equipment, run respective function when needing to verify some fault mode, reduces and repeats to repair
Change or compile embedded host applications software work amount；The function that the present invention writes answers VxWorks system Central Plains when not running
It is not influenced with software, after operation, as long as restarting systems or equipment, Failure elimination is highly-safe.The method of the present invention
Simplicity runs function by input function name, injects failure, may be applicable in system or equipment course of normal operation
The host applications software for carrying out a large amount of period BIT verifyings, improves the ability of proving period BIT.
The above, optimal specific embodiment only of the invention, but scope of protection of the present invention is not limited thereto,
In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by anyone skilled in the art,
It should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of the claim
Subject to enclosing.
Claims (6)
1. a kind of fault filling method for improving period BIT verifying ability, which is characterized in that the fault filling method includes:
Choose fault mode；
Write the direct fault location function that can simulate the fault mode；
The direct fault location function call injection into controlling application program and is compiled；
Direct fault location function, simulated failure mode shown in executing.
2. the fault filling method according to claim 1 for improving period BIT verifying ability, which is characterized in that the event
Barrier mode includes that RS422 bus communication is abnormal, 1553B bus communication is abnormal, pulse signal is abnormal.
3. the fault filling method according to claim 2 for improving period BIT verifying ability, which is characterized in that the event
Hinder one that injection function corresponds in the fault mode.
4. the fault filling method according to claim 3 for improving period BIT verifying ability, which is characterized in that the master
Control application program can store multiple direct fault location functions, execute the failure note with direct fault location function name when calling
Enter function.
5. the fault filling method according to claim 4 for improving period BIT verifying ability, which is characterized in that the master
One in the fault mode is only executed in control application program implementation procedure.
6. the fault filling method according to claim 5 for improving period BIT verifying ability, which is characterized in that the master
The installation environment for controlling application program is VxWork operating system.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110688313A (en) * | 2019-09-26 | 2020-01-14 | 天津津航计算技术研究所 | Fault injection method for software test under VxWorks operating system |
| CN111141501A (en) * | 2019-12-13 | 2020-05-12 | 中国航空综合技术研究所 | Test case generation system and method for testability test of airborne equipment |
| CN115563017A (en) * | 2022-11-10 | 2023-01-03 | 成都麟通科技有限公司 | Test system and method based on bus injection and computer equipment |
| CN115658370A (en) * | 2022-11-18 | 2023-01-31 | 辉羲智能科技(上海)有限公司 | Compiler-based real-time detection method for machine learning acceleration chip faults |
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| CN115658370A (en) * | 2022-11-18 | 2023-01-31 | 辉羲智能科技(上海)有限公司 | Compiler-based real-time detection method for machine learning acceleration chip faults |
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Application publication date: 20190101 |