CN103376396A - Test circuit for motherboard - Google Patents
Test circuit for motherboard Download PDFInfo
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- CN103376396A CN103376396A CN 201210109831 CN201210109831A CN103376396A CN 103376396 A CN103376396 A CN 103376396A CN 201210109831 CN201210109831 CN 201210109831 CN 201210109831 A CN201210109831 A CN 201210109831A CN 103376396 A CN103376396 A CN 103376396A
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- mainboard
- electrically connected
- controller
- effect transistor
- field effect
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Abstract
The invention provides a test circuit for a motherboard. The test circuit is connected to the motherboard to detect fault information of the motherboard. The fault information is represented by a debug code. The test circuit for the motherboard includes a controller, and a power supply circuit, a switch circuit, a first display module and an instruction module which are electrically connected with the controller. The controller is used for controlling the power supply circuit to supply or cut off power for the motherboard. The controller is used for controlling the switch circuit to switch on or off the motherboard. The controller is used for acquiring the debug code during a test after the motherboard is switched on, and for controlling the first display module to display the debug code. The controller is also used for controlling the instruction module to display a test status and a test result. The test circuit for the motherboard is easy to operate.
Description
Technical field
The present invention relates to a kind of mainboard test circuit, relate in particular to a kind of circuit of testing host failure message.
Background technology
Mainboard exploitation Qualify Phase at electronic installation often need to carry out fault detect to each hardware on the mainboard.Existing test mode generally is to utilize manually operating electronic devices, with control electronic installation switching on and shutting down repeatedly, and obtains the failure message of electronic installation by being connected in a debugging apparatus (such as the Debug card) on the mainboard.Yet this kind method of testing need to need ceaselessly switching on and shutting down of operator, and must constantly monitor test process further to debug electronic installation when test is not passed through, and brings more inconvenience to the operator easily.
Summary of the invention
In view of above situation, be necessary to provide a kind of mainboard test circuit easy and simple to handle.
A kind of mainboard test circuit, be connected in a mainboard with the failure message of detecting master plate, this failure message is levied by the debug code table, described mainboard test circuit comprises controller and the power circuit that is electrically connected with controller, on/off circuit, the first display module and indicating module, it is main board power supply or outage that described controller is used for the control power circuit, described controller is used for the dynamo-electric road of gauge tap so that mainboard start or shutdown, described controller obtains except error code for the test process after the mainboard start, and control the demonstration of the first display module and should remove error code, described controller also is used for control indicating module demonstration test mode and test result.
Above-mentioned mainboard test circuit arranges controller, with the powering on and cut off the power supply of control mainboard, and the start of control mainboard and shutdown, need not manually-operated during test, to realize automatic test.Simultaneously, the present invention shows except error code by the first display module, by indicating module indication test mode and test result.So, in test process, need not the operator and constantly monitor, save manpower.
Description of drawings
Fig. 1 and Fig. 2 are the circuit diagram of the mainboard test circuit of preferred embodiments of the present invention.
The main element symbol description
| Mainboard test circuit | 100 |
| Controller | U1 |
| The first universal input and output port | GPIO1 |
| The second universal input and output port | GPIO2 |
| Failure message reads pin | IO53-IO58 |
| The first display module control pin | IO26-IO34 |
| Indicating module control pin | IO96-IO100 |
| The second display module control pin | IO66-IO74 |
| |
10 |
| Field effect transistor | Q1-Q7 |
| Grid | G1-G7 |
| Drain electrode | D1-D7 |
| Source electrode | S1-S7 |
| Resistance R 1 | R1-R7 |
| Light emitting diode | LED1-LED5 |
| Relay | RLY1、RLY2 |
| Power supply | P |
| Power supply | V |
| On/off |
20 |
| Diode | D11 |
| The |
30 |
| |
40 |
| Hummer | BZ |
| Anodal | + |
| Negative pole | - |
| The |
50 |
| |
200 |
Following embodiment further specifies the present invention in connection with above-mentioned accompanying drawing.
Embodiment
See also Fig. 1 and Fig. 2, preferred embodiments of the present invention provides a kind of mainboard test circuit (figure is mark not), and it is used for the failure message of the mainboard 200 of detecting electronic installation.This mainboard test circuit comprises controller U1 and the power circuit 10, on/off circuit 20, the first display module 30, indicating module 40 and the second display module 50 that are electrically connected with this controller U1 simultaneously.
In the present embodiment, this controller U1 is CPLD (Complex Programmable Logic Device, CPLD), it comprises that the first universal input and output port GPIO1, the second universal input and output port GPIO2, failure message read pin IO53-IO58, the first display module control pin IO26-IO34, indicating module control pin IO96-IO100 and the second display module control pin IO66-IO74.
This first universal input and output port GPIO1 and power circuit 10 are electrically connected, and this controller U1 exports high/low level with control power circuit 10 by the first universal input and output port GPIO1, and can preset the interval time of this high/low level, such as 12 hours.This second universal input and output port GPIO2 and on/off circuit 20 are electrically connected, this controller U1 exports high/low level with the dynamo-electric road 20 of gauge tap by the second universal input and output port GPIO2, can preset the interval time of this high/low level, such as 10 minutes.
This failure message reads the LPC(Low Pin Count of pin IO53-IO58 and mainboard 200) the interface (not shown) is electrically connected, the representative electronic device failure information of exporting to obtain mainboard 200 operation self-check programs from the LPC interface except error code.
This first display module control pin IO26-IO34 and the first display module 30 are electrically connected, this controller U1 is used for parsing should remove error code, and controlled the first display module control pin IO26-IO34 according to analysis result and export high/low level with further control the first display module 30.
This indicating module control pin IO96-IO100 and indicating module 40 are electrically connected, and this controller U1 is used for exporting high/low level with further control indicating module 40 according to current test mode and test result control indicating module control pin IO96-IO100.
This second display module control pin IO66-IO74 and the second display module 50 are electrically connected, this controller U1 is used for record mainboard 200 by the test number of times of (as without producing except error code), and exports high/low level with further control the second display module 50 according to controlling the second display module control pin IO66-IO74 by testing time.
Please further consult Fig. 2, this power circuit 10 is used to mainboard 200 power supplies, and this power circuit 10 comprises field effect transistor Q1, resistance R 1, R2, R3, LED 1, relay R LY1 and power supply P(such as 220V power supply).This field effect transistor Q1 comprises grid G 1, source S 1 and drain D 1.This grid G 1 is electrically connected this source S 1 ground connection by resistance R 1 and the first universal input and output port GPIO1.These resistance R 2 one end ground connection, the other end and the first universal input and output port GPIO1 are electrically connected.The drain D 1 of the negative electrode of this LED 1 and field effect transistor Q1 is electrically connected, and anode is electrically connected by resistance R 3 and a power supply V.The drain D 1 of this relay R LY1 and field effect transistor Q1 is electrically connected, and this relay R LY1 is electrically connected between power supply P and the mainboard 200 simultaneously.When the first universal input and output port GPIO1 output high level, drain D 1 output low level of field effect transistor Q1, relay R LY1 adhesive, power supply P is mainboard 200 power supplies.At this moment, this LED1 lights to indicate mainboard 200 to power on.When the first universal input and output port GPIO1 output low level, the drain D 1 output high level of field effect transistor Q1, relay R LY1 disconnects.
This on/off circuit 20 is used for control mainboard 200 and realizes start or shutdown, and this on/off circuit 20 comprises field effect transistor Q2, resistance R 4, R5, diode D11 and relay R LY2.This field effect transistor Q2 comprises grid G 2, source S 2 and drain D 2.This grid G 2 is electrically connected these source S 2 ground connection by resistance R 4 and the second universal input and output port GPIO2.These resistance R 5 one end ground connection, the other end and the second universal input and output port GPIO2 are electrically connected.The negative electrode of this diode D11 and the drain D of field effect transistor Q2 2 are electrically connected, and anode and power supply V are electrically connected.This relay R LY2 comprises a telefault L and a switch S, and this telefault L telecommunications is connected in the two ends of diode D11, and this switch S and mainboard 200 are electrically connected.When the second universal input and output port GPIO2 output high level, drain D 2 output low levels of field effect transistor Q2, the telefault L energising of relay R LY2 is so that the switch S adhesive, and mainboard 200 is realized start.When the second universal input and output port GPIO2 output low level, the drain D 2 output high level of field effect transistor Q2, switch S disconnects, and mainboard 200 is realized shutdown.
Please consult Fig. 1, in the present embodiment, this first display module 30 is 28 segment numeral pipes again, is used for showing except error code.For example, when the processor (not shown) on the mainboard 200 breaks down, controller U1 reads pin IO53-IO58 by failure message and obtains except error code EE, and this is removed error code EE resolve, export high/low level by the first display module control pin IO26-IO34 again and show EE with further control the first display module 30.
This indicating module 40 is used to indicate mainboard 200 current test mode and test result.In the present embodiment, this indicating module 40 comprises field effect transistor Q3-Q7, LED 2-LED5, resistance R 6, R7 and hummer BZ.This field effect transistor Q3-Q7 grid (G3-G7) separately is electrically connected with indicating module control pin IO96-IO100 respectively, field effect transistor Q3-Q7 source electrode (S3-S7) separately is ground connection all, the drain D 3 of field effect transistor Q3 is electrically connected with the negative electrode of LED 2, and the anode of LED 2 is electrically connected with power supply V by resistance R 6.The drain D 4 of field effect transistor Q4 is electrically connected with the negative electrode of LED 3, and the anode of LED 3 is electrically connected with power supply V by resistance R 7.The drain D 5 of field effect transistor Q5 is electrically connected with the negative electrode of LED 4, and the anode of LED 4 and power supply V are electrically connected.The drain D 6 of field effect transistor Q6 is electrically connected with the negative electrode of LED 5, and the anode of LED 5 and power supply V are electrically connected.In the present embodiment, this LED2-LED5 be respectively applied to indication except error code read, read reset, mainboard 200 by test and mainboard 200 by four kinds of states of test.For example when mainboard 200 passed through test, indicating module control pin IO99 exported high level, field effect transistor Q5 conducting, and LED 4 lights to indicate mainboard 200 by testing.This hummer BZ comprise positive pole+with negative pole-, this positive pole+be electrically connected with power supply V, negative pole-with drain D 7 electric connections of field effect transistor Q7.When mainboard 200 does not pass through test, indicating module control pin IO100 output high level, field effect transistor Q7 conducting, this hummer BZ sounds, and passes through to test with further prompting operation person's mainboard 200.So, in test process, need not the operator and constantly monitor test result.
In the present embodiment, this second display module 50 is 28 segment numeral pipes, is used for showing that mainboard 200 is by the number of times of test.Behind the number of times by test, control this second display module 50 and show that mainboard 200 is by the number of times of test in setting-up time (such as 12 hours) when controller U1 has recorded mainboard 200.Owing to be 28 segment numeral pipes, so this second display module 50 can support at most that mainboard 200 is that 256(namely counts from 00 to FF by the number of times of test).
The below further specifies the use principle of this mainboard test circuit: when needs carried out detecting fault to mainboard 200, controller U1 was at first by the first universal input and output port GPIO1 control power circuit 10, so that power circuit 10 is mainboard 200 power supplies.After mainboard 200 powered on, controller U1 was by the dynamo-electric road 20 of the second universal input and output port GPIO2 gauge tap, so that mainboard 200 is realized start.Thereafter, mainboard 200 brings into operation, and exports except error code by moving self-check program, and controller U1 reads the error code of removing that pin IO53-IO58 obtains mainboard 200 outputs by failure message, and controls 30 demonstrations of the first display module and should remove error code.Indicate in real time current test mode and test result with Time Controller U1 by indicating module 40, as reading by LED 2 luminous expression debug codes, or having when producing except error code by LED 5 luminous expression mainboards 200 by test, and report to the police by hummer BZ.
After mainboard 200 was finished the primary fault detecting, controller U1 controlled first mainboard 200 shutdown, controlled power circuit 10 outages again.Thereafter, controller U1 controls power circuit 10 again for 200 starts of mainboard 200 electricity supply and control mainboards, makes mainboard 200 again carry out detecting fault, so repeats above-mentioned steps until reach the predetermined test duration.At last, controller U1 record mainboard 200 number of times by test, and by the second display module 50 these number of times of demonstration.
Mainboard test circuit of the present invention arranges controller U1, with the powering on and cut off the power supply of control mainboard 200, and 200 starts of control mainboard and shutdown, need not manually-operated during test, to realize automatic test.Simultaneously, this case shows respectively except error code, test mode and test result, the number of times of mainboard 200 by testing by the first display module 30, indicating module 40, the second display module 50.So, in test process, need not the operator and constantly monitor, save manpower.
Claims (10)
1. mainboard test circuit, be connected in a mainboard with the failure message of detecting master plate, this failure message is levied by the debug code table, it is characterized in that: described mainboard test circuit comprises controller and the power circuit that is electrically connected with controller, on/off circuit, the first display module and indicating module, it is main board power supply or outage that described controller is used for the control power circuit, described controller is used for the dynamo-electric road of gauge tap so that mainboard start or shutdown, described controller obtains except error code for the test process after the mainboard start, and control the demonstration of the first display module and should remove error code, described controller also is used for control indicating module demonstration test mode and test result.
2. mainboard test circuit as claimed in claim 1, it is characterized in that: described controller comprises the first universal input and output port, described power circuit comprises field effect transistor, resistance, relay and power supply, described field effect transistor comprises grid, source electrode and drain electrode, described grid is electrically connected by resistance and the first universal input and output port, described source ground, described drain electrode and relay are electrically connected, described relay is electrically connected between power supply and the mainboard, when the first universal input and output port output high level, relay adhesive, power supply are main board power supply.
3. mainboard test circuit as claimed in claim 2, it is characterized in that: described power circuit also comprises light emitting diode, the negative electrode of described light emitting diode and the drain electrode of field effect transistor are electrically connected, the anode of described light emitting diode and power supply electric connection.
4. mainboard test circuit as claimed in claim 1, it is characterized in that: described controller comprises the second universal input and output port, described on/off circuit comprises field effect transistor, resistance, diode and relay, described field effect transistor comprises grid, source electrode and drain electrode, described grid is electrically connected by resistance and the second universal input and output port, described source ground, the negative electrode of described drain electrode and diode is electrically connected, the anode of diode and a power supply are electrically connected, described relay comprises a telefault and a switch, described telefault is electrically connected at the two ends of diode, and described switch and mainboard are electrically connected.
5. mainboard test circuit as claimed in claim 4, it is characterized in that: when described the second universal input and output port output high level, the telefault energising of relay is so that the switch adhesive, mainboard is realized start, when the second universal input and output port output low level, switch disconnects, and mainboard is realized shutdown.
6. mainboard test circuit as claimed in claim 1, it is characterized in that: controller comprises that a plurality of failure messages read pin, described failure message reads pin and mainboard is electrically connected, to obtain except error code.
7. mainboard test circuit as claimed in claim 1, it is characterized in that: described controller comprises a plurality of the first display module control pins, described the first display module control pin and the first display module are electrically connected, described controller is resolved removing error code, and exports high/low level according to output control the first display module control pin of resolving to the first display module.
8. mainboard test circuit as claimed in claim 1, it is characterized in that: described indicating module comprises four field effect transistor and four light emitting diodes, described controller comprises four indicating module control pins, each described field effect transistor comprises grid, source electrode and drain electrode, the grid of described four field effect transistor is electrically connected with four indicating module control pins respectively, the source grounding of described four field effect transistor, the drain electrode of described four field effect transistor is electrically connected by a light emitting diode and a power supply respectively, and described four light emitting diodes are respectively applied to indication and read except error code, read and reset, mainboard does not pass through four kinds of states of test by test and mainboard.
9. mainboard test circuit as claimed in claim 1, it is characterized in that: described indicating module comprises field effect transistor and hummer, described controller comprises indicating module control pin, described field effect transistor comprises grid, source electrode and drain electrode, described hummer comprises positive pole and negative pole, and described grid and indicating module control pin are electrically connected described source ground, the negative pole of described drain electrode and hummer is electrically connected, and the positive pole of described hummer and a power supply are electrically connected.
10. mainboard test circuit as claimed in claim 1, it is characterized in that: described mainboard test circuit also comprises the second display module that is electrically connected with controller, described controller is used for the record mainboard by the number of times of test, and controls the second display module and show this number of times.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201210109831 CN103376396A (en) | 2012-04-16 | 2012-04-16 | Test circuit for motherboard |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201210109831 CN103376396A (en) | 2012-04-16 | 2012-04-16 | Test circuit for motherboard |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103376396A true CN103376396A (en) | 2013-10-30 |
Family
ID=49461815
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201210109831 Pending CN103376396A (en) | 2012-04-16 | 2012-04-16 | Test circuit for motherboard |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103376396A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105511994A (en) * | 2015-12-28 | 2016-04-20 | 天津浩丞恒通科技有限公司 | Startup/shutdown and reset test card for computer motherboard |
| CN106250279A (en) * | 2015-06-09 | 2016-12-21 | 广达电脑股份有限公司 | Except wrong method and device thereof |
| CN108928337A (en) * | 2018-08-31 | 2018-12-04 | 珠海市思卡净化技术有限公司 | A kind of vehicle air dryer control system |
-
2012
- 2012-04-16 CN CN 201210109831 patent/CN103376396A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106250279A (en) * | 2015-06-09 | 2016-12-21 | 广达电脑股份有限公司 | Except wrong method and device thereof |
| CN106250279B (en) * | 2015-06-09 | 2019-07-05 | 广达电脑股份有限公司 | Except wrong method and device thereof |
| CN105511994A (en) * | 2015-12-28 | 2016-04-20 | 天津浩丞恒通科技有限公司 | Startup/shutdown and reset test card for computer motherboard |
| CN108928337A (en) * | 2018-08-31 | 2018-12-04 | 珠海市思卡净化技术有限公司 | A kind of vehicle air dryer control system |
| CN108928337B (en) * | 2018-08-31 | 2024-03-01 | 珠海市思卡净化技术有限公司 | Vehicle-mounted air dryer control system |
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| Date | Code | Title | Description |
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| PB01 | Publication | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20131030 |